CN202406095U - High-speed parallel interface circuit - Google Patents
High-speed parallel interface circuit Download PDFInfo
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- CN202406095U CN202406095U CN2011205583963U CN201120558396U CN202406095U CN 202406095 U CN202406095 U CN 202406095U CN 2011205583963 U CN2011205583963 U CN 2011205583963U CN 201120558396 U CN201120558396 U CN 201120558396U CN 202406095 U CN202406095 U CN 202406095U
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Abstract
The utility model provides a high-speed parallel interface circuit and is suitable for the field of digital communication. The high-speed parallel interface circuit comprises an LVDS (Low Voltage Differential Signaling) receiving module, a sampling conversion module, a bit synchronization module and a word synchronization module, wherein the LVDS receiving module is used for receiving and shaping data; the sampling conversion module is connected with the LVDS receiving module and is used for sampling the data output by the LVDS receiving module under a sampling clock and converting the data into parallel data; the bit synchronization module is connected with the sampling conversion module and is used for providing the sampling clock for the sampling conversion module and adjusting the sampling clock to an optimal sampling point according to the data output by the sampling conversion module; and the word synchronization module is connected with the bit synchronization module and is used for performing shift adjustment on the data output by the bit synchronization module. Source synchronization data are correctly sampled and recovered by means of purely digital phase adjustment and word adjustment of the sampling clock, the output is fed back to a multiplexer of the sampling clock through calculating a phase of a training data sampling clock so as to change the phase of the sampling clock, so that the sampling of the clock is performed in the centre of data effective windows.
Description
Technical field
The utility model belongs to digital communicating field, relates in particular to a kind of high speed parallel interface circuit.
Background technology
Along with the flourish communication system that causes of digital communication service has proposed higher challenge to transmission bandwidth, for example the 10Gbps high speed parallel interface has a wide range of applications at aspects such as optical fiber communication, exchanges data, network services.One of bottleneck of high-speed parallel transmission is the efficient recovery that has to data; Two problems of main existence during data are recovered: the one, when the single line transmission rate is more and more faster; Corresponding bits per inch constantly reduces according to shared time window, and the valid window that causes clock to be difficult in data is accurately sampled; The 2nd, because that each data paths of parallel transmission postpones is different, cause receiving terminal can't efficient synchronization to receive each circuit-switched data of parallel transmission.
In the prior art; High speed data transfer mainly adopts the mode of clock and data recovery to carry out; Promptly from the data flow of high-speed transfer, extract clock information, come data stream is sampled with the clock that extracts again, guarantee that clock sampling is along dropping in the effective sampling window.Clock data recovery circuit mainly is made up of marginal detector, frequency acquisition device, phase tracker and clock recovery device; At first detect the saltus step extraction phase information on data edge through marginal detector; Adjust the phase place of clock then through the self-oscillation of phase extraction circuit, through the clock frequency of clock recovery device with supervision and the output of adjustment phase extraction circuit, wherein the clock recovery device is made up of high frequency reference clock oscillation source, filter, phase discriminator and frequency divider at last; These all are to design complicated, high to required precision analog circuit; Production technology to integrated circuit also has special requirement, and clock data recovery circuit for the burst data-signal, the shake of its big phase place causes the phase-locked loop losing lock easily; Phase lock loop lock on time is longer, often can not satisfy requirement synchronously fast.
The utility model content
The purpose of the utility model is: a kind of high speed parallel interface circuit is provided, is intended to solve the problem that exists in the above-mentioned background technology.
The purpose of the utility model is achieved in that
A kind of high speed parallel interface circuit comprises:
Receive the LVDS receiver module of data and shaping;
Be connected with the LVDS receiver module, under sampling clock, the data of LVDS receiver module output sampled and convert the sample conversion module of parallel data into;
Be connected with the sample conversion module, for the sample conversion module provides sampling clock, and according to the bit synchronization module of data adjustment sampling clock to the optimum sampling point of sample conversion module output; And
Be connected the word synchronization module that the data of contraposition synchronization module output are shifted and adjust with the bit synchronization module.
Said sample conversion module comprises:
With under the sampling clock respectively at the rising edge of the data of LVDS receiver module output and rising edge sampling unit and the trailing edge sampling unit that trailing edge is sampled and stored; And
Be connected with the trailing edge sampling unit with the rising edge sampling unit, the sampled data of rising edge sampling unit and the output of trailing edge sampling unit be combined into the sampling assembled unit of parallel data.
Said bit synchronization module comprises:
Produce the DLL phase-locked loop of the sampling clock of n phase place, said n is the integer greater than 1;
Be connected with the DLL phase-locked loop, from a said n phase clock, select a MUX as the sampling clock of sample conversion module; And
Be connected with MUX with the sample conversion module; Comparative result according to sample conversion module data of exporting and the reference data of presetting; The control MUX is correspondingly adjusted the phase clock of output, is the sampling clock adjusting module of optimum sampling point until the phase clock of exporting.
Said DLL phase-locked loop produces the sampling clock of n phase place based on the source synchronous clock signal.
Said n is 16.
Said sampling clock adjusting module detects the hopping edge that receives data; When the hopping edge takes place in data; The control MUX is with the phase place of the sampling clock of the precision adjustment output of each 1/n; And calculate phase shift number of times counter1 that receives data variation to middle edge and the phase shift number of times counter2 that receives data variation to left margin, and calculate and store sample clock jayrator (counter1+counter2)/2; Said MUX is according to said sampling clock jayrator output optimum sampling point.
Said word synchronization module comprises displacement computing unit and asynchronous FIFO unit; Said displacement computing unit is used in the training stage based on preset synchronization character the asynchronous digital data that the receives adjustment that is shifted; Calculate and the storage carry digit; And data are shifted according to depositing carry digit in the normal data transfer stage, and the adjusted data that will be shifted write the asynchronous FIFO unit.
Said displacement computing unit also is used for after accomplishing displacement and calculating carry digit, producing the WrdRdy signal; Read signal to said asynchronous FIFO unit has all produced the WrdRdy signal at the displacement computing unit of each passage, and all WrdRdy signals are all effective effectively the time.
Said WrdRdy signal to each passage carries out logical AND to be handled and to obtain the AllRdy signal, when AllRdy effectively and synchronization character data are deposited in the said asynchronous FIFO unit when arriving; Read signal for said asynchronous FIFO unit is effective after effective at least one clock cycle at AllRdy.
The outstanding advantage of the utility model is: the sampling clock phase adjustment of the utility model employing pure digi-tal and tone of Chinese characters perfect square formula are accurately sampled to source-synchronous data and are recovered; The phase place that the MUX that outputs to sampling clock changes sampling clock is fed back in calculating through to the training data sampling clock phase; Thereby make clock sampling occur in the central authorities of data valid window, and can not receive the influence of ambient temperature, humidity, interference etc.
Description of drawings
Fig. 1 is the structure chart of the high speed parallel interface circuit that provides of the utility model;
Fig. 2 is the structure chart of sample conversion module in the high speed parallel interface circuit that provides of the utility model;
Fig. 3 is the structure chart of the high speed parallel interface circuit meta synchronization module that provides of the utility model;
Fig. 4 is the structure chart of word synchronization module in the high speed parallel interface circuit that provides of the utility model.
Embodiment
For the purpose, technical scheme and the advantage that make the utility model is clearer,, the utility model is further elaborated below in conjunction with accompanying drawing and embodiment.Should be appreciated that specific embodiment described herein only in order to explanation the utility model, and be not used in qualification the utility model.
The transmission of high-speed parallel data is made up of a plurality of passages, and in the utility model, the high speed parallel interface circuit structure of each passage is as shown in Figure 1.Each single channel (one digit number in the parallel data is according to the path) comprises bit synchronization and synchronous two parts of word.
Bit synchronization partly comprises low-voltage differential signal (LVDS) receiver module 1, sample conversion module 2 and the bit synchronization module 3 that electrically connects successively.LVDS receiver module 1 receives the data in each passage and carries out exporting after the shaping; Sample conversion module 2 is sampled to the data that receive under sampling clock and is converted parallel data into; Bit synchronization module 3 provides sampling clock for sample conversion module 2, the data that receive are recovered, and according to the data adjustment sampling clock that receives to optimum sampling point; Word synchronization module 4 makes the word alignment of each channel data through adjustment that the data that receive are shifted.
When the high speed parallel interface operate as normal, transmitting terminal will send the training sequence of preset certain series earlier, accomplish initial bit synchronization and word Synchronous Processing for receiving terminal.
Fig. 2 shows the structure of the above-mentioned sample conversion module 2 that the utility model provides, and comprises rising edge sampling unit 21, trailing edge sampling unit 22 and sampling assembled unit 23.
The data of LVDS receiver module 1 output are with inputing to rising edge sampling unit 21 and trailing edge sampling unit 22 simultaneously.Rising edge sampling unit 21 and trailing edge sampling unit 22 are sampled and are stored at the rising edge of data and trailing edge respectively under with a sampling clock; In the utility model; Under each sampling clock; Rising edge sampling unit 21 and trailing edge sampling unit 22 2 bit data (dividing 2 clock cycle to accomplish) of sampling are respectively made up these 4 sampled datas by sampling assembled unit 23, synthesize 4 parallel-by-bit data through the order adjustment; So that reduce the clock that internal data is handled, also be convenient to thereafter bit synchronization and handle the word Synchronous Processing with training sequence.The utility model need not special two edge collection registers just can realize the conversion of the serial data of input to parallel data.
Fig. 3 shows the structure of the above-mentioned bit synchronization module 3 that the utility model provides, and comprises that DLL phase-locked loop 31, multiphase clock do not have MUX 32 and sampling clock adjusting module 33 that burr switches.
In the utility model; DLL phase-locked loop 31 produces n based on the source synchronous clock of LVDS receiver module 1 output (promptly send data terminal send with the road clock) signal, and (n is for greater than 1 integer; For example n is 8,16 etc.) sampling clock of individual phase place, MUX 32 is selected the sampling clock as sample conversion module 2 from this n phase clock.To the sample parallel data of assembled unit 23 output of sampling clock adjusting module 33 recovers initial data; And according to receiving the comparative result of data with the reference data of presetting; Output respective phase adjustment signal; 32 phase clocks of MUX according to this phase adjustment signal adjustment output; Phase clock until output is an optimum sampling point, is about to the rising edge of clock and the central authorities that trailing edge is adjusted to the data sampling window, and sampling clock adjusting module 33 will calculate and store the data of phase place adjustment.Said optimum sampling point in the utility model, is the optimum sampling clock in the said n phase sample clock, and the clock that is in the centre of the corresponding sampling clock of the data of two adjacent generation hopping edges usually can be thought optimum sampling point.
An embodiment as the utility model; Training data is one group with " 0000_0000_0000_0000_0011_1111_1111_1111_1111 " and is repeatedly sent by transmitting terminal; With " 0011 " is reference data; When the data that receive were non-reference data, sampling clock adjusting module 33 was according to itself and reference data result relatively, and what transmission added/subtract phase place accordingly controls signal to MUX 32; The data that for example receive are " 0001 ", and then sampling clock adjusting module 33 sends the control signal that subtracts phase place.Further, sampling clock adjusting module 33 can also be according to the carry digit that will receive data shift to reference data, and control MUX 32 adds/subtract the phase place of corresponding figure place, and the minimum precision of MUX 32 adjustment phase places is 1/n.
In another embodiment of the utility model; Sampling clock adjusting module 33 is through detecting the hopping edge that receives data level; For example can detect through 4 bit data are carried out XOR; As being example, will obtain the right along " 001 " through XOR, when receiving data generation hopping edge with " 0001 "; Sampling clock adjusting module 33 will send triggering signal and give MUX 32; Sampling clock phase is added/subtract 1/n by MUX 32, middle along " 010 " (i.e. the XOR value of " 0011 ") along being changed to up to the data that sampling clock adjusting module 33 receives, sampling clock adjusting module 33 calculates phase shift number of times counter1 (i.e. phase shift number of times from " 001 " to " 010 ") at this moment at every turn; And continue control MUX 32 and carry out the phase place adjustment; The data edge that receives up to sampling clock adjusting module 33 is changed to left margin " 100 ", and sampling clock adjusting module 33 calculates phase shift number of times counter2 (i.e. phase shift number of times from " 001 " to " 100 ") once more at this moment, finally calculates sampling clock jayrator (counter1+counter2)/2 and storage; When normal data transfer, sampling clock adjusting module 33 will be according to the sampling clock of these sampling clock jayrator control MUX 32 output optimum phases.In the process of above-mentioned phase place adjustment, the data of 33 pairs of receptions of sampling clock adjusting module will be exported to word synchronization module 4 after recovering in real time.
Each channel data provides the BitRdy signal after recovering to accomplish, and control word synchronization module 4 can carry out Synchronous Processing to data.The structure of said word synchronization module 4 is as shown in Figure 4, comprises displacement computing unit 41 and the asynchronous FIFO unit of handling based on stream 42.
The hopping edge of training data can be used synchronously equally in word; For example; Training sequence is " 0000_0000_0000_0000_0011_1111_1111_1111_1111 ", and is synchronization character with " 0011 ", displacement computing unit 41 based on preset synchronization character to the asynchronous digital data that the receives adjustment that is shifted; The figure place that calculating and storage are moved, and the adjusted data that will be shifted write asynchronous FIFO unit 42.For example, be " 0001 " when receiving parallel data, the computing unit 41 that then is shifted moves to left one with data.Displacement computing unit 41 will produce the WrdRdy signal after accomplishing displacement and calculating carry digit; When the displacement computing unit 41 of each passage has all produced the WrdRdy signal; And all WrdRdy signals are all effectively the time, the control unit that triggers receiving terminal are read the data in the asynchronous FIFO unit 42 of each passage.A preferred embodiment as the utility model; To carry out the logical AND processing to the WrdRdy signal that each passage produces and obtain the AllRdy signal; When AllRdy effectively and synchronization character data are deposited in the asynchronous FIFO unit 42 when arriving, for the read signal of asynchronous FIFO unit 42 then be preferably in AllRdy effectively after at least one clock cycle effectively.After training was accomplished, during normal data transfer, displacement computing unit 41 calculates gained in the time of will be according to training carry digit was to the data that the receive adjustment that is shifted.
Above-mentioned training sequence data, reference data, synchronization character and shifting function can design arbitrarily, do not receive above-mentioned the limit.
The sampling clock phase adjustment of the utility model employing pure digi-tal and tone of Chinese characters perfect square formula are accurately sampled to source-synchronous data and are recovered; The phase place that the MUX that outputs to sampling clock changes sampling clock is fed back in calculating through to the training data sampling clock phase; Thereby make clock sampling occur in the central authorities of data valid window; And can not receive the influence of ambient temperature, humidity, interference etc., and then make the data sync on the parallel data bus line through the tone of Chinese characters is whole.The utility model does not rely on concrete integrated circuit production technology; Employed IP kernel is to provide free on the main flow technology of main flow flow manufacturer; Cost that can be relatively low is realized high speed data transmission interface on asic chip; The data sync of the utility model only needs the lower stand-by period simultaneously, and can tolerate higher shake and transmission delay.
The above is merely the preferred embodiment of the utility model; Not in order to restriction the utility model; Any modification of being done within all spirit and principles at the utility model, be equal to replacement and improvement etc., all should be included within the protection range of the utility model.
Claims (9)
1. a high speed parallel interface circuit is characterized in that, comprising:
Receive the LVDS receiver module of data and shaping;
Be connected with the LVDS receiver module, under sampling clock, the data of LVDS receiver module output sampled and convert the sample conversion module of parallel data into;
Be connected with the sample conversion module, for the sample conversion module provides sampling clock, and according to the bit synchronization module of data adjustment sampling clock to the optimum sampling point of sample conversion module output; And
Be connected the word synchronization module that the data of contraposition synchronization module output are shifted and adjust with the bit synchronization module.
2. high speed parallel interface circuit as claimed in claim 1 is characterized in that, said sample conversion module comprises:
With under the sampling clock respectively at the rising edge of the data of LVDS receiver module output and rising edge sampling unit and the trailing edge sampling unit that trailing edge is sampled and stored; And
Be connected with the trailing edge sampling unit with the rising edge sampling unit, the sampled data of rising edge sampling unit and the output of trailing edge sampling unit be combined into the sampling assembled unit of parallel data.
3. high speed parallel interface circuit as claimed in claim 1 is characterized in that, said bit synchronization module comprises:
Produce the DLL phase-locked loop of the sampling clock of n phase place, said n is the integer greater than 1;
Be connected with the DLL phase-locked loop, from a said n phase clock, select a MUX as the sampling clock of sample conversion module; And
Be connected with MUX with the sample conversion module; Comparative result according to sample conversion module data of exporting and the reference data of presetting; The control MUX is correspondingly adjusted the phase clock of output, is the sampling clock adjusting module of optimum sampling point until the phase clock of exporting.
4. high speed parallel interface circuit as claimed in claim 3 is characterized in that, said DLL phase-locked loop produces the sampling clock of n phase place based on the source synchronous clock signal.
5. high speed parallel interface circuit as claimed in claim 3 is characterized in that, said n is 16.
6. high speed parallel interface circuit as claimed in claim 3; It is characterized in that; Said sampling clock adjusting module detects the hopping edge that receives data, and when the hopping edge took place data, the control MUX was with the phase place of the sampling clock of the precision adjustment output of each 1/n; And calculate phase shift number of times counter1 that receives data variation to middle edge and the phase shift number of times counter2 that receives data variation to left margin, and calculate and store sample clock jayrator (counter1+counter2)/2; Said MUX is according to said sampling clock jayrator output optimum sampling point.
7. high speed parallel interface circuit as claimed in claim 1; It is characterized in that; Said word synchronization module comprises displacement computing unit and asynchronous FIFO unit, and said displacement computing unit is used in the training stage based on preset synchronization character the asynchronous digital data that the receives adjustment that is shifted, and carry digit is also stored in calculating; And data are shifted according to depositing carry digit in the normal data transfer stage, and the adjusted data that will be shifted write the asynchronous FIFO unit.
8. high speed parallel interface circuit as claimed in claim 7 is characterized in that, said displacement computing unit also is used for after accomplishing displacement and calculating carry digit, producing the WrdRdy signal; Read signal to said asynchronous FIFO unit has all produced the WrdRdy signal at the displacement computing unit of each passage, and all WrdRdy signals are all effective effectively the time.
9. high speed parallel interface circuit as claimed in claim 8 is characterized in that, said WrdRdy signal to each passage carries out logical AND to be handled and to obtain the AllRdy signal, when AllRdy effectively and synchronization character data are deposited in the said asynchronous FIFO unit when arriving; Read signal for said asynchronous FIFO unit is effective after effective at least one clock cycle at AllRdy.
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| CN2011205583963U CN202406095U (en) | 2011-12-28 | 2011-12-28 | High-speed parallel interface circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102522981A (en) * | 2011-12-28 | 2012-06-27 | 成都三零嘉微电子有限公司 | High-speed parallel interface circuit |
| CN109213703A (en) * | 2017-06-30 | 2019-01-15 | 华为技术有限公司 | A kind of data detection method and data detection device |
| CN112055128A (en) * | 2019-06-06 | 2020-12-08 | 海信视像科技股份有限公司 | Image data sampling method and device, electronic equipment and storage medium |
-
2011
- 2011-12-28 CN CN2011205583963U patent/CN202406095U/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102522981A (en) * | 2011-12-28 | 2012-06-27 | 成都三零嘉微电子有限公司 | High-speed parallel interface circuit |
| CN102522981B (en) * | 2011-12-28 | 2014-12-31 | 成都三零嘉微电子有限公司 | High-speed parallel interface circuit |
| CN109213703A (en) * | 2017-06-30 | 2019-01-15 | 华为技术有限公司 | A kind of data detection method and data detection device |
| CN109213703B (en) * | 2017-06-30 | 2021-12-14 | 华为技术有限公司 | Data detection method and data detection device |
| CN112055128A (en) * | 2019-06-06 | 2020-12-08 | 海信视像科技股份有限公司 | Image data sampling method and device, electronic equipment and storage medium |
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Granted publication date: 20120829 Termination date: 20181228 |
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