CN109213703B - Data detection method and data detection device - Google Patents
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Abstract
The application provides a data detection method and a data detection device, which are characterized in that at least two groups of sampling clocks with phase difference are used for sampling input data, so that the data edges of the input data can be detected certainly, and an optimal sampling phase window is determined. The method in the embodiment of the application comprises the following steps: when the chip reads data of external equipment, at least two groups of sampling clocks are used for sampling input data of the interface controller to obtain a sampling data set, and phase difference exists between any two groups of sampling clocks in the at least two groups of sampling clocks; determining a data edge of the input data from the sampled data set; a target sampling phase window is determined from the data edges.
Description
Technical Field
The present disclosure relates to the field of computers, and in particular, to a data detection method and a data detection apparatus.
Background
In the existing chip architecture, a Secure Digital (SD) Card, an Embedded Multi Media Card (eMMC), and the like are provided, and the SD Card and the eMMC are external devices and storage interfaces belonging to a chip and can be used for starting and storing a chip system.
When a chip reads data of an external device such as an SD card or an eMMC, adjustment of read data is required in a read data direction in order to ensure the accuracy of the read data. Therefore, data detection is required in each data reading process of the chip, and one data detection method is as follows: when the chip reads the data of the external equipment, the data of the peripheral interface of the chip are sampled by adopting a plurality of clocks with different phases to obtain a plurality of sampling data, the sampling data are compared with the read data obtained by the chip, and the sampling data are judged to be wrong, so that the optimal sampling phase window is determined.
In the above conventional data detection method, the determination of the optimal sampling phase window depends on the accuracy of the sampling clock phase, and when the data window is large, even if the accuracy of the sampling clock phase is infinitely increased, a correct and incorrect boundary data position cannot be found, so that a read data error cannot be detected.
Disclosure of Invention
The application provides a data detection method and a data detection device, which are characterized in that at least two groups of sampling clocks with phase difference are used for sampling input data, so that the data edges of the input data can be detected certainly, and an optimal sampling phase window is determined.
A first aspect of the present application provides a data detection method, which is applied to a peripheral interface system of a chip, where the peripheral interface system of the chip includes an interface controller and an external device, and the data detection method includes:
when the chip reads the data of the external equipment, at least two groups of sampling clocks are used for sampling the input data of the interface controller to obtain a sampling data set, and phase difference exists between any two groups of sampling clocks in the at least two groups of sampling clocks;
determining a data edge of the input data from the sampled data set;
and determining a target sampling phase window according to the data edge.
The peripheral interface system of the chip comprises an interface controller and external equipment, the external equipment comprises an SD card, an eMMC, an SDIO card and the like, the interface controller is used for controlling a plurality of peripheral interfaces in a chip structure, the peripheral interfaces comprise an SDIO interface, an eMMC interface and the like, data and instruction interaction between the chip and the external equipment is realized through the interface controller, when the chip reads data of the external equipment, in order to ensure the correctness of the read data, the data at the input end of the interface controller needs to be sampled and judged, the determination of an optimal sampling phase window needs to be realized through a data detection device, the data detection device uses at least two groups of sampling clocks to sample the input data of the interface controller to obtain a sampling data set, and as any two groups of sampling clocks in the at least two groups of sampling clocks have phase differences, the data jump point of the input data can be sampled necessarily, after data analysis is performed on the sampling data set, the data edge of the input data can be determined, and under the condition of known data edge, a target sampling phase window can be determined according to the data edge, wherein the target sampling phase window is the optimal sampling phase window. Compared with the existing data detection method, at least two groups of sampling clocks with phase difference are used for sampling input data, so that the data edge of the input data can be detected certainly, and the optimal sampling phase window can be determined.
In combination with the first aspect of the present application, in the first embodiment of the first aspect of the present application, the sampling clocks are N groups, N is an integer greater than 1, the number of sampling points of each group of sampling clocks is M, M is an integer greater than 0,
the sampling of the input data of the interface controller by using at least two sets of sampling clocks to obtain a sampling data set includes:
respectively sampling input data of the interface controller by using each group of sampling clocks of N groups of sampling clocks to obtain N groups of sampling data, wherein each group of sampling data has M sampling values;
and according to the phase difference between any two groups of sampling clocks in the N groups of sampling clocks, carrying out phase front-back sequencing on N x M sampling values of the N groups of sampling data to obtain a sampling data set.
The sampling method comprises the steps of assuming that sampling clocks are N groups, N is an integer larger than 1, the number of sampling points of each group of sampling clocks is M, M is an integer larger than 0, the sampling points are a clock with a preset phase, sampling input data of an interface controller is respectively carried out by adopting each group of sampling clocks of the N groups of sampling clocks, M sampling values are obtained after one group of sampling clocks are sampled, N M sampling values are obtained by the N groups of sampling clocks, and the phases of the sampling points corresponding to the N M sampling values are different because phase difference exists between any two groups of sampling clocks, and according to the phase difference between any two groups of sampling clocks of the N groups of sampling clocks, the N M sampling values of the N groups of sampling data are subjected to phase front-back sequencing to obtain a sampling data set.
With reference to the first embodiment of the first aspect of the present application, in a second embodiment of the first aspect of the present application, the determining a data edge of the input data according to the sampled data set includes:
comparing whether any two adjacent sampling values in the sampling data set are the same;
if two adjacent sampling values are the same, determining that the two adjacent sampling values are not the data edge of the input data;
and if the two adjacent sampling values are different, determining that the two adjacent sampling values are the data edge of the input data.
The detection of the data edge of the input data is obtained by judging a sampling data set, specifically, any two adjacent sampling values in the sampling data set are compared, if the sampling data set comprises 4 sampling values, the 1 st sampling value is 1, the 2 nd sampling value is 1, the 3 rd sampling value is 1, the 4 th sampling value is 0, the two adjacent sampling values of the 1 st sampling value and the 2 nd sampling value are compared, and the data edge of the input data is not determined because the sampling values are all 1; comparing two adjacent sampling values of the 2 nd sampling value and the 3 rd sampling value, and determining the data edge which is not the input data as the sampling values are all 1; and comparing two adjacent sampling values of the 3 rd sampling value and the 4 th sampling value, wherein the 3 rd sampling value is 1, and the fourth sampling value is 0, determining that the sampling value is the data edge of the input data.
With reference to the second implementation manner of the first aspect of the present application, in a third implementation manner of the first aspect of the present application, the determining an optimal sampling phase window according to the data edge includes:
determining two sampling points corresponding to the two adjacent sampling values according to the two adjacent sampling values corresponding to the data edge;
and determining a target sampling phase window according to the phase values of the two sampling points.
After the data edge of the input data is determined, according to two adjacent sampling values corresponding to the data edge, two corresponding sampling points can be determined by the two adjacent sampling values, and under the condition that the phase values of all sampling points in each group of sampling clocks are known, the phase values of the two sampling points can also be known, and the target sampling phase window can be determined by knowing the phase values of the two sampling points.
With reference to the first aspect, the first implementation manner of the first aspect, the second implementation manner of the first aspect, or the third implementation manner of the first aspect, in a fourth implementation manner of the first aspect of the present application, before sampling the input data of the interface controller by using at least two sets of sampling clocks, the method further includes:
and generating at least two groups of sampling clocks, wherein phase difference exists between any two groups of sampling clocks, and the number of the clocks adopted in each group is the same.
The sampling clocks used for sampling are generated by the data detection device, and the generated sampling clocks have at least two groups, any two groups of sampling clocks have phase difference, and the number of sampling points of each group of sampling clocks is the same.
With reference to the fourth embodiment of the first aspect of the present application, in the fifth embodiment of the first aspect of the present application, the phase difference between any two sets of sampling clocks is a fixed phase difference.
In order to avoid the phenomenon that sampling points overlap when sampling is performed by using different groups of sampling clocks, the phase difference between any two groups of sampling clocks is generally set to be a fixed value, which is beneficial for determining the data edge of input data.
A second aspect of the present application provides a data detection apparatus, which is applied to a peripheral interface system of a chip, where the peripheral interface system of the chip includes an interface controller and an external device, and the data detection apparatus includes:
the data acquisition module is used for sampling input data of the interface controller by using at least two groups of sampling clocks to obtain a sampling data set when the chip reads data of the external equipment, phase difference exists between any two groups of sampling clocks in the at least two groups of sampling clocks, and the number of sampling points of each group of sampling clocks is the same;
a data processing module for determining a data edge of the input data from the sampled data set;
and the data processing module is also used for determining a target sampling phase window according to the data edge.
The peripheral interface system of the chip comprises an interface controller and external equipment, the external equipment comprises an SD card, an eMMC, an SDIO card and the like, the interface controller is used for controlling a plurality of peripheral interfaces in a chip structure, the peripheral interfaces comprise an SDIO interface, an eMMC interface and the like, data and instruction interaction between the chip and the external equipment is realized through the interface controller, when the chip reads data of the external equipment, in order to ensure the correctness of the read data, the data at the input end of the interface controller needs to be sampled and judged, the determination of an optimal sampling phase window needs to be realized through a data detection device, a data acquisition module samples the input data of the interface controller by using at least two groups of sampling clocks to obtain a sampling data set, and as the phase difference exists between any two groups of the at least two groups of sampling clocks, the data jump point of the input data can be sampled necessarily, after the data processing module performs data analysis on the sampling data set, the data edge of the input data can be determined, and under the condition that the data edge is known, the data acquisition module can determine a target sampling phase window according to the data edge, wherein the target sampling phase window is the optimal sampling phase window. Compared with the existing data detection method, at least two groups of sampling clocks with phase difference are used for sampling input data, so that the data edge of the input data can be detected certainly, and the optimal sampling phase window can be determined.
In combination with the second aspect of the present application, in the first embodiment of the second aspect of the present application, the sampling clocks are N groups, N is an integer greater than 1, the number of sampling points of each group of sampling clocks is M, M is an integer greater than 0,
the data acquisition module is further configured to sample input data of the interface controller by using each of N sets of sampling clocks to obtain N sets of sampling data, and each set of sampling data has M sampling values;
and the data acquisition module is further used for sequencing N × M sampling values of the N groups of sampling data in a front-back phase manner according to the phase difference between any two groups of sampling clocks in the N groups of sampling clocks to obtain a sampling data set.
The data acquisition module respectively adopts each group of sampling clocks of the N groups of sampling clocks to sample input data of the interface controller, M sampling values are obtained after one group of sampling clocks are sampled, N M sampling values are obtained by the N groups of sampling clocks, and because phase difference exists between any two groups of sampling clocks, the phases of the sampling points corresponding to the N M sampling values are different, and according to the phase difference between any two groups of sampling clocks in the N groups of sampling clocks, the N M sampling values of the N groups of sampling data are subjected to phase front-back sequencing to obtain a sampling data set.
In combination with the first embodiment of the second aspect of the present application, in the second embodiment of the second aspect of the present application,
the data processing module is further configured to compare whether any two adjacent sampling values in the sampling data set are the same;
the data processing module is further configured to determine that the data edge is not the data edge of the input data if two adjacent sampling values are the same;
the data processing module is further configured to determine that the data edge of the input data is the data edge if two adjacent sampling values are different.
The detection of the data edge of the input data is obtained by judging a sampling data set, specifically, a data processing module compares any two adjacent sampling values in the sampling data set, if the sampling data set comprises 4 sampling values, the 1 st sampling value is 1, the 2 nd sampling value is 1, the 3 rd sampling value is 1, the 4 th sampling value is 0, the 1 st sampling value and the 2 nd sampling value are compared, and the two adjacent sampling values are both 1, so that the data edge of the input data is determined not; comparing two adjacent sampling values of the 2 nd sampling value and the 3 rd sampling value, and determining the data edge which is not the input data as the sampling values are all 1; and comparing two adjacent sampling values of the 3 rd sampling value and the 4 th sampling value, wherein the 3 rd sampling value is 1, and the fourth sampling value is 0, determining that the sampling value is the data edge of the input data.
In combination with the second embodiment of the second aspect of the present application, in the third embodiment of the second aspect of the present application,
the data processing module is further used for determining two sampling points corresponding to two adjacent sampling values according to the two adjacent sampling values corresponding to the data edge;
and the data processing module is also used for determining a target sampling phase window according to the phase values of the two sampling points.
After the data processing module determines the data edge of the input data, the data processing module can determine two corresponding sampling points according to two adjacent sampling values corresponding to the data edge, and under the condition that the phase values of all the sampling points in each group of sampling clocks are known, the phase values of the two sampling points can also be known, and the target sampling phase window can be determined by knowing the phase values of the two sampling points.
With reference to the second aspect, the first embodiment of the second aspect, the second embodiment of the second aspect, or the third embodiment of the second aspect of the present application, in a fourth embodiment of the second aspect of the present application, the data detection apparatus further includes:
the clock generation module is used for generating at least two groups of sampling clocks, phase difference exists between any two groups of sampling clocks, and the number of sampling points of each group adopting the clocks is the same.
The sampling clocks used for sampling are generated by the clock generation module, and the generated sampling clocks are at least two groups, any two groups of sampling clocks have phase difference, and the number of sampling points of each group of sampling clocks is the same.
With reference to the fourth embodiment of the second aspect of the present application, in the fifth embodiment of the second aspect of the present application, the phase difference between any two sets of sampling clocks is a fixed phase difference.
In order to avoid the phenomenon that sampling points overlap when sampling is performed by using different groups of sampling clocks, the phase difference between any two groups of sampling clocks is generally set to be a fixed value, which is beneficial for determining the data edge of input data.
A third aspect of the present application provides a computer-readable storage medium having stored therein instructions, which, when run on a computer, cause the computer to perform the method of the above-described aspects.
A fourth aspect of the present application provides a computer program product comprising instructions which, when run on a computer, cause the computer to perform the method of the above-described aspects.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings used in the description of the embodiments and the prior art will be briefly described below.
Fig. 1 is a schematic diagram of a chip structure provided in the present application;
FIG. 2 is a schematic structural diagram of a peripheral interface system of a chip provided in the present application;
FIG. 3 is a schematic diagram of sampled data of a prior art data detection method provided herein;
FIG. 4 is a schematic flow chart diagram illustrating an embodiment of a data detection method provided herein;
FIG. 5 is a schematic diagram of the present application providing input data sampling using 2 sets of sampling clocks;
FIG. 6 is a schematic structural diagram of an embodiment of a data detection apparatus provided in the present application;
fig. 7 is a schematic structural diagram of another embodiment of a data detection apparatus provided in the present application.
Detailed Description
The application provides a data detection method and a data detection device, which are characterized in that at least two groups of sampling clocks with phase difference are used for sampling input data, so that the data edges of the input data can be detected certainly, and an optimal sampling phase window is determined.
The technical solutions in the present application will be clearly and completely described below with reference to the accompanying drawings in the present application.
First, a system architecture or scenario in which the present application is applied will be briefly described.
Fig. 1 is a diagram showing a chip structure, which includes the following components: a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a Video Display Processor (Video and Display Processor), a Video Decoder (Video Decoder), a Video compression Decoder (HEVC Encoder) of the HEVC (high Efficiency Video coding) standard, an image Decoder (JPEG/PNG Decoder) based on the JPEG/PNG Graphics format, an Instruction Register (IR), a Universal Asynchronous Receiver Transmitter/Transmitter (UART), and the like.
In order to realize the data and instruction interaction between the chip and the external device, the chip structure further needs to include the following interfaces: a Secure Digital Input and Output Card (SDIO) Interface, a Joint Test Action Group (JTAG) Interface, a Double Data Rate (DDR) Interface, a Nand/eMMC/SPI Interface, a High Definition Multimedia Interface (HDMI), a USB2.0 Interface, a USB3.0 Interface, a PCIE2.0 Interface, and a SATA3.0 Interface.
External equipment of the chip is accessed into the chip structure through the interfaces, for example, an SD card is connected with an SDIO interface, a double-rate synchronous dynamic random access memory (DDR SDRAM) is connected with a DDR interface, a Nand Flash card, an eMMC, an SPI Flash card and a Nor Flash card are connected with a Nand/eMMC/SPI interface, a USB2.0 equipment is connected with a USB2.0 interface, a USB3.0, a PCIE and SATA equipment is connected with a USB3.0, a PCIE2.0 and an SATA3.0 interface, and therefore data and instruction interaction of the chip and the external equipment such as the SD card, the DDR SDRAM, the eMMC, the Nand Flash card and the USB equipment can be achieved. The SD card and the like are external devices of the chip, and the eMMC is an external device, but is actually a memory interface of the chip.
The peripheral interface system of the chip mainly comprises an interface controller and external equipment, as shown in fig. 2, a CPU is connected with the interface controller through a bus, the interface controller comprises a CPU interface, a control channel, a data channel and a frequency division and clock control functional module, and data and instruction interaction between the external equipment and the CPU is realized through the interface controller. When a chip reads data of an external device such as an SD card or an eMMC, adjustment of read data is required in a read data direction in order to ensure the accuracy of the read data. Therefore, data detection is required in the chip data reading process, and an existing data detection method is as follows: when the chip reads data of an external device, a plurality of sampling data are obtained by using input data at the input end of the interface controller by using a plurality of clocks with different phases, as shown in fig. 3, the input data are respectively sampled by using clocks with 8 phases in one clock cycle, if data detection is to be realized, the data detection depends on clock sampling to data jump (jump from high level (1) to low level (0) or jump from 0 to 1), for example, a phase window between the 4 th clock and the 5 th clock in fig. 3 is an optimal sampling phase window. However, this method has a very high requirement on the precision of the clock, and if the data window is very large, the sampling points of 8 clocks in fig. 3 will all be in 1 or 0 of the input data, so that the data jump cannot be detected, if the detection accuracy is to be improved, the phase modulation precision of the clock must be improved, which increases the chip cost, and even if the phase modulation precision is improved, there still exists a probability that the best phase window cannot be obtained.
In order to solve the above-described problems, the present application provides a data detection method for obtaining an optimal sampling phase window by using multiple sets of sampling clocks, and the data detection method is described below by a flow embodiment.
Referring to fig. 4, an embodiment of the present application provides a data detection method applied to a peripheral interface system of a chip, an interface controller of the peripheral interface system, and an external device, where the data detection method includes:
401. sampling input data of an interface controller by using at least two groups of sampling clocks to obtain a sampling data set;
in this embodiment, the peripheral interface system of the chip includes an interface controller and external devices, the external devices include an SD card, an eMMC, an SDIO card, and the like, the interface controller is used to control a plurality of peripheral interfaces in the chip structure, the peripheral interfaces include an SDIO interface, an eMMC interface, and the like, data and command interaction between the chip and the external devices is implemented by the interface controller, when the chip reads the data of the external device, in order to ensure the correctness of the read data, the data at the input end of the interface controller needs to be sampled and judged, the determination of the optimal sampling phase window needs to be realized through a data detection device, the data detection device uses at least two groups of sampling clocks to sample input data of the interface controller to obtain a sampling data set, and any two groups of sampling clocks in the at least two groups of sampling clocks have phase differences.
402. Determining a data edge of the input data from the sampled data set;
in this embodiment, since any two sampling clocks in the at least two sampling clocks have a phase difference, a data transition point of the input data can be sampled inevitably, and after data analysis is performed on the sampling data set, a data edge of the input data can be determined.
403. A target sampling phase window is determined from the data edges.
In this embodiment, under the condition that the data edge is known, the target sampling phase window can be determined according to the data edge, and the target sampling phase window is the optimal sampling phase window.
In the embodiment of the application, at least two groups of sampling clocks with phase differences are used for sampling input data, so that the data edges of the input data can be detected certainly, and an optimal sampling phase window can be determined.
Optionally, in some embodiments of the present application, the sampling clocks are N groups, N is an integer greater than 1, the number of sampling points of each group of sampling clocks is M, M is an integer greater than 0,
sampling input data of an interface controller by using at least two groups of sampling clocks to obtain a sampling data set, comprising:
using each group of sampling clocks of N groups of sampling clocks to sample input data of the interface controller respectively to obtain N groups of sampling data, wherein each group of sampling data has M sampling values;
and according to the phase difference between any two groups of sampling clocks in the N groups of sampling clocks, carrying out phase front-back sequencing on N × M sampling values of the N groups of sampling data to obtain a sampling data set.
In the embodiment of the application, it is assumed that the sampling clocks are N groups, N is an integer greater than 1, the number of sampling points of each group of sampling clocks is M, M is an integer greater than 0, the sampling point is a clock with a preset phase, each group of sampling clocks of the N groups of sampling clocks is used for sampling input data of the interface controller, M sampling values are obtained after one group of sampling clocks are sampled, N × M sampling values are obtained by the N groups of sampling clocks, and because a phase difference exists between any two groups of sampling clocks, the phases of the sampling points corresponding to the N × M sampling values are different, and the N × M sampling values of the N groups of sampling data are subjected to phase front-back sequencing according to the phase difference between any two groups of sampling clocks in the N groups of sampling clocks to obtain a sampling data set. For example, the sampling clocks are 2 groups, each group has 2 sampling points, as shown in fig. 5, the sampling points of the 1 st group of sampling clocks are a and b, the sampling points of the 2 nd group of sampling clocks are c and d, the phase difference between the 1 st group of sampling clocks and the 2 nd group of sampling clocks is x, the sampling value of the a point is 1, the sampling value of the b point is 0, the sampling value of the c point is 1, and the sampling value of the d point is 0, the sampling values of the 4 sampling points, namely a, b, c and d, are sorted in front and back according to the phase difference x between the 1 st group of sampling clocks and the 2 nd group of sampling clocks, the obtained sampling data set is (1,1,0,0), and the corresponding sampling point sequence is (a, c, b, d).
It should be noted that fig. 5 shows that 2 sets of sampling clocks are used for sampling, and in practical applications, more than two sets of sampling clocks may be used. When the input data is periodic, one period can be equally divided into Y phases, and Y groups of clocks with phase difference are used for sampling data at one time, so that data edges of all periods can be obtained at one time.
Optionally, in some embodiments of the present application, determining a data edge of input data according to a sampled data set includes:
comparing whether any two adjacent sampling values in the sampling data set are the same;
if two adjacent sampling values are the same, determining that the two adjacent sampling values are not the data edge of the input data;
and if the two adjacent sampling values are not the same, determining that the two adjacent sampling values are the data edges of the input data.
In the embodiment of the present application, as shown in fig. 5, after obtaining the sample data set (1,1,0,0), comparing whether any two adjacent sample values in the sample data set are the same, for example, if both the 1 st sample value and the 2 nd sample value are 1, determining that the sample data set is not a data edge of the input data; if the 2 nd sampling value is different from the 3 rd sampling value, determining the data edge of the input data; the 3 rd sample value and the 4 th sample value are both 0, and it is determined that it is not a data edge of the input data.
Optionally, in some embodiments of the present application, determining an optimal sampling phase window according to a data edge includes:
determining two sampling points corresponding to two adjacent sampling values according to the two adjacent sampling values corresponding to the data edge;
and determining a target sampling phase window according to the phase values of the two sampling points.
In the embodiment of the present application, according to the data edge of the input data determined in the above embodiment, the 2 nd sampling value and the 3 rd sampling value corresponding to the 2 nd sampling value and the 3 rd sampling value, two sampling points corresponding to the 2 nd sampling value and the 3 rd sampling value can be determined as b and c, and since the phase values of the sampling points in the 1 st set of sampling clock and the 2 nd set of sampling clock are determined, the phase values of the sampling points b and c are known, so that it can be determined that the target sampling phase window is the phase window between the sampling point b and the sampling point c, and since the target sampling phase window is the data edge of the input data, the target sampling phase window is the optimal sampling phase window.
Optionally, in some embodiments of the present application, before sampling the input data of the interface controller by using at least two sets of sampling clocks, the method further includes:
and generating at least two groups of sampling clocks, wherein phase difference exists between any two groups of sampling clocks, and the number of the clocks adopted in each group is the same.
In the embodiment of the present application, the sampling clocks used for sampling in the above embodiments are generated by the data detection apparatus, and the generated sampling clocks are at least two groups, any two groups of sampling clocks have a phase difference therebetween, and the number of sampling points of each group of sampling clocks is the same.
Optionally, in some embodiments of the present application, the phase difference between any two sets of sampling clocks is a fixed phase difference.
In the embodiment of the present application, in order to avoid a phenomenon that sampling points overlap when sampling is performed by using different sets of sampling clocks, it is assumed that a phase difference between a 1 st set of sampling clocks and a 2 nd set of sampling clocks is 45 °, a phase difference between a 2 nd set of sampling clocks and a3 rd set of sampling clocks is 135 °, then a phase difference between the 1 st set of sampling clocks and the 3 rd set of sampling clocks is 180 °, which may cause a phenomenon that sampling points of the 1 st set of sampling clocks and the 3 rd set of sampling clocks overlap, and a phase difference between any two sets of sampling clocks is generally set to be a fixed value, which is beneficial for determining a data edge of input data.
The data detection method is explained in the above embodiment, and the data detection apparatus is explained below by the embodiment.
Referring to fig. 6, an embodiment of the present application provides a data detection apparatus for a peripheral interface system of a chip, where the peripheral interface system of the chip includes an interface controller and an external device, and the data detection apparatus includes:
the data acquisition module 601 is configured to sample input data of the interface controller by using at least two sets of sampling clocks to obtain a sampling data set when the chip reads data of an external device, where any two sets of sampling clocks in the at least two sets of sampling clocks have a phase difference, and the number of sampling points of each set of sampling clocks is the same;
a data processing module 602 for determining data edges of the input data from the sampled data set;
the data processing module 602 is further configured to determine a target sampling phase window according to the data edge.
In the embodiment of the application, a peripheral interface system of a chip comprises an interface controller and external equipment, the external equipment comprises an SD card, an eMMC, an SDIO card and the like, the interface controller is used for controlling a plurality of peripheral interfaces in a chip structure, the peripheral interfaces comprise an SDIO interface, an eMMC interface and the like, data and command interaction between the chip and the external equipment needs to be realized through the interface controller, when the chip reads data of the external equipment, in order to ensure the correctness of the read data, sampling judgment needs to be performed on data at an input end of the interface controller, and determination of an optimal sampling phase window needs to be realized through a data detection device, a data acquisition module 601 samples input data of the interface controller by using at least two sets of sampling clocks to obtain a sampling data set, because a phase difference exists between any two sets of the at least two sets of sampling clocks, then, the data transition point of the input data can be sampled certainly, the data processing module 602 can determine the data edge of the input data after performing data analysis on the sampled data set, and under the condition that the data edge is known, the data processing module 602 can determine the target sampling phase window according to the data edge, and the target sampling phase window is the optimal sampling phase window. Compared with the existing data detection method, at least two groups of sampling clocks with phase difference are used for sampling input data, so that the data edge of the input data can be detected certainly, and the optimal sampling phase window can be determined.
Optionally, in some embodiments of the present application, the sampling clocks are N groups, N is an integer greater than 1, the number of sampling points of each group of sampling clocks is M, M is an integer greater than 0,
the data acquisition module 601 is further configured to use each of the N sets of sampling clocks to respectively sample input data of the interface controller, so as to obtain N sets of sampling data, where each set of sampling data has M sampling values;
the data acquisition module 601 is further configured to perform phase front-back ordering on N × M sampling values of the N groups of sampling data according to a phase difference between any two groups of sampling clocks in the N groups of sampling clocks, so as to obtain a sampling data set.
In the embodiment of the present application, it is assumed that the sampling clocks are N groups, N is an integer greater than 1, the number of sampling points of each group of sampling clocks is M, M is an integer greater than 0, the sampling point is a clock with a preset phase, the data acquisition module 601 samples input data of the interface controller by using each group of sampling clocks of the N groups of sampling clocks, after sampling by one group of sampling clocks, M sampling values are obtained, and N × M sampling values obtained by the N groups of sampling clocks, and because a phase difference exists between any two groups of sampling clocks, phases of sampling points corresponding to the N × M sampling values are different, and according to the phase difference between any two groups of sampling clocks of the N groups of sampling clocks, the N × M sampling values of the N groups of sampling data are ordered front and back in phase to obtain a sampling data set.
Alternatively, in some embodiments of the present application,
the data processing module 602 is further configured to compare whether any two adjacent sampling values in the sampling data set are the same;
the data processing module 602 is further configured to determine that the data edge is not the input data if two adjacent sampling values are the same;
the data processing module 602 is further configured to determine that the data edge of the input data is a data edge if two adjacent sample values are not the same.
In this embodiment of the present application, the detection of the data edge of the input data is obtained by judging a sampling data set, specifically, the data processing module 602 compares any two adjacent sampling values in the sampling data set, if the sampling data set includes 4 sampling values, a 1 st sampling value is 1, a 2 nd sampling value is 1, a3 rd sampling value is 1, and a 4 th sampling value is 0, compares the 1 st sampling value and the 2 nd sampling value, and determines that the sampling value is not the data edge of the input data because the sampling values are all 1; comparing two adjacent sampling values of the 2 nd sampling value and the 3 rd sampling value, and determining the data edge which is not the input data as the sampling values are all 1; and comparing two adjacent sampling values of the 3 rd sampling value and the 4 th sampling value, wherein the 3 rd sampling value is 1, and the fourth sampling value is 0, determining that the sampling value is the data edge of the input data.
Alternatively, in some embodiments of the present application,
the data processing module 602 is further configured to determine two sampling points corresponding to two adjacent sampling values according to the two adjacent sampling values corresponding to the data edge;
the data processing module 602 is further configured to calculate a phase window to the target sample according to the phase values of the two sample points.
In this embodiment of the application, after the data processing module 602 determines the data edge of the input data, the data processing module 602 may determine two corresponding sampling points according to two adjacent sampling values corresponding to the data edge, and when the phase values of all sampling points in each set of sampling clocks are known, the phase values of the two sampling points may also be known, and when the phase values of the two sampling points are known, a target sampling phase window may be determined.
Optionally, as shown in fig. 7, in some embodiments of the present application, the data detecting device further includes:
the clock generating module 701 is configured to generate at least two sets of sampling clocks, where any two sets of sampling clocks have a phase difference therebetween, and the number of clocks used in each set is the same.
In the embodiment of the present application, the sampling clocks used for sampling are generated by the clock generation module 701, and at least two sets of the generated sampling clocks have a phase difference between any two sets of the sampling clocks, and the number of sampling points of each set of the sampling clocks is the same. It should be noted that the clock generation module 701 may be a clock generator or a clock generation circuit that can generate a clock signal when being implemented.
Optionally, as shown in fig. 7, in some embodiments of the present application, the phase difference between any two sets of sampling clocks is a fixed phase difference.
In the embodiment of the present application, in order to avoid a phenomenon that sampling points overlap when sampling is performed by using different sets of sampling clocks, it is assumed that a phase difference between a 1 st set of sampling clocks and a 2 nd set of sampling clocks is 45 °, a phase difference between a 2 nd set of sampling clocks and a3 rd set of sampling clocks is 135 °, then a phase difference between the 1 st set of sampling clocks and the 3 rd set of sampling clocks is 180 °, which may cause a phenomenon that sampling points of the 1 st set of sampling clocks and the 3 rd set of sampling clocks coincide, and a phase difference between any two sets of sampling clocks of at least two sets of sampling clocks generated by the clock generation module 701 is generally set to be a fixed value, which is beneficial for determining a data edge of input data.
The present application also provides a computer-readable storage medium having stored therein instructions, which when run on a computer, cause the computer to perform the data detection method described in the above embodiments.
The present application also provides a computer program product containing instructions which, when run on a computer, cause the computer to perform the data detection method described in the above embodiments.
In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product.
The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the application to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website site, computer, server, or data center to another website site, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that a computer can store or a data storage device, such as a server, a data center, etc., that is integrated with one or more available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.
It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.
The above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.
Claims (13)
1. A data detection method is characterized in that the method is applied to a peripheral interface system of a chip, the peripheral interface system of the chip comprises an interface controller and external equipment, and the data detection method comprises the following steps:
when the chip reads data of the external equipment, at least two groups of sampling clocks are used for sampling input data of the interface controller to obtain a sampling data set, phase difference exists between any two groups of sampling clocks in the at least two groups of sampling clocks, the sampling data set comprises two groups of sampling data, each group of sampling clocks in the at least two groups of sampling clocks samples the input data to obtain a group of sampling data, and each group of sampling data comprises a plurality of sampling points;
determining the data edge of the input data according to the relation of the sampling values of any two adjacent sampling points in the sampling data set;
and determining a target sampling phase window according to the data edge.
2. The method of claim 1, wherein the sampling clocks are N groups, N being an integer greater than 1, the number of sampling points of each group of sampling clocks is M, M being an integer greater than 0,
the sampling of the input data of the interface controller by using at least two sets of sampling clocks to obtain a sampling data set includes:
respectively sampling input data of the interface controller by using each group of sampling clocks of N groups of sampling clocks to obtain N groups of sampling data, wherein each group of sampling data has M sampling values;
and according to the phase difference between any two groups of sampling clocks in the N groups of sampling clocks, carrying out phase front-back sequencing on N x M sampling values of the N groups of sampling data to obtain a sampling data set.
3. The method of claim 2, wherein determining the data edge of the input data from the relationship of the sample values of any two adjacent sample points in the sample data set comprises:
comparing whether any two adjacent sampling values in the sampling data set are the same;
if two adjacent sampling values are the same, determining that the two adjacent sampling values are not the data edge of the input data;
and if the two adjacent sampling values are different, determining that the two adjacent sampling values are the data edge of the input data.
4. The method of claim 3, wherein determining a target sampling phase window from the data edges comprises:
determining two sampling points corresponding to the two adjacent sampling values according to the two adjacent sampling values corresponding to the data edge;
and determining a target sampling phase window according to the phase values of the two sampling points.
5. The method of any of claims 1 to 4, wherein prior to sampling the input data of the interface controller using at least two sets of sampling clocks, further comprising:
and generating at least two groups of sampling clocks, wherein phase difference exists between any two groups of sampling clocks, and the number of sampling points of each group of sampling clocks is the same.
6. The method of claim 5, wherein the phase difference between any two sets of sampling clocks is a fixed phase difference.
7. A data detection device is characterized in that the data detection device is applied to a peripheral interface system of a chip, the peripheral interface system of the chip comprises an interface controller and external equipment, and the data detection device comprises:
the data acquisition module is used for sampling input data of the interface controller by using at least two groups of sampling clocks to obtain a sampling data set when the chip reads data of the external equipment, wherein a phase difference exists between any two groups of sampling clocks in the at least two groups of sampling clocks, the number of sampling points of each group of sampling clocks is the same, the sampling data set comprises two groups of sampling data, each group of sampling clocks in the at least two groups of sampling clocks samples the input data to obtain a group of sampling data, and each group of sampling data comprises a plurality of sampling points;
the data processing module is used for determining the data edge of the input data according to the relation of the sampling values of any two adjacent sampling points in the sampling data set;
and the data processing module is also used for determining a target sampling phase window according to the data edge.
8. The apparatus of claim 7, wherein the sampling clocks are N groups, N is an integer greater than 1, the number of sampling points of each group of sampling clocks is M, M is an integer greater than 0,
the data acquisition module is further configured to sample input data of the interface controller by using each of N sets of sampling clocks to obtain N sets of sampling data, and each set of sampling data has M sampling values;
and the data acquisition module is further used for sequencing N × M sampling values of the N groups of sampling data in a front-back phase manner according to the phase difference between any two groups of sampling clocks in the N groups of sampling clocks to obtain a sampling data set.
9. The apparatus of claim 8,
the data processing module is further configured to compare whether any two adjacent sampling values in the sampling data set are the same;
the data processing module is further configured to determine that the data edge is not the data edge of the input data if two adjacent sampling values are the same;
the data processing module is further configured to determine that the data edge of the input data is the data edge if two adjacent sampling values are different.
10. The apparatus of claim 9,
the data processing module is further used for determining two sampling points corresponding to two adjacent sampling values according to the two adjacent sampling values corresponding to the data edge;
and the data processing module is also used for determining a target sampling phase window according to the phase values of the two sampling points.
11. The apparatus of any one of claims 7 to 10, wherein the data detection apparatus further comprises:
the clock generation module is used for generating at least two groups of sampling clocks, phase difference exists between any two groups of sampling clocks, and the number of sampling points of each group of sampling clocks is the same.
12. The apparatus of claim 11, wherein the phase difference between any two sets of sampling clocks is a fixed phase difference.
13. A computer-readable storage medium comprising instructions which, when executed on a computer, cause the computer to perform the method of any of claims 1 to 6.
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| CN112202518B (en) * | 2019-07-08 | 2023-11-17 | 中兴通讯股份有限公司 | Method and device for detecting phase of clock signal and communication equipment |
| CN111124978B (en) | 2019-10-30 | 2021-07-06 | 苏州浪潮智能科技有限公司 | Method and device for correcting phase of parallel bus |
| WO2021207972A1 (en) * | 2020-04-15 | 2021-10-21 | 深圳市大疆创新科技有限公司 | Data transmission method, data transmission device, electronic device and storage medium |
| CN117407346B (en) * | 2023-12-13 | 2024-04-05 | 芯能量集成电路(上海)有限公司 | Sampling point adjusting system and method for FLASH outside vehicle-gauge chip |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1799198A (en) * | 2003-06-04 | 2006-07-05 | 皇家飞利浦电子股份有限公司 | Bit-detection arrangement and apparatus for reproducing information |
| CN101567767A (en) * | 2009-05-19 | 2009-10-28 | 华为技术有限公司 | Window sampling control method and device |
| CN202406095U (en) * | 2011-12-28 | 2012-08-29 | 成都三零嘉微电子有限公司 | High-speed parallel interface circuit |
| CN106656182A (en) * | 2016-11-24 | 2017-05-10 | 深圳市鼎阳科技有限公司 | Digital chip ADC output data receiving method and digital chip |
| CN106850179A (en) * | 2016-12-23 | 2017-06-13 | 深圳市紫光同创电子有限公司 | A kind of data window querying method and circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3622685B2 (en) * | 2000-10-19 | 2005-02-23 | セイコーエプソン株式会社 | Sampling clock generation circuit, data transfer control device, and electronic device |
-
2017
- 2017-06-30 CN CN201710527455.2A patent/CN109213703B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1799198A (en) * | 2003-06-04 | 2006-07-05 | 皇家飞利浦电子股份有限公司 | Bit-detection arrangement and apparatus for reproducing information |
| CN101567767A (en) * | 2009-05-19 | 2009-10-28 | 华为技术有限公司 | Window sampling control method and device |
| CN202406095U (en) * | 2011-12-28 | 2012-08-29 | 成都三零嘉微电子有限公司 | High-speed parallel interface circuit |
| CN106656182A (en) * | 2016-11-24 | 2017-05-10 | 深圳市鼎阳科技有限公司 | Digital chip ADC output data receiving method and digital chip |
| CN106850179A (en) * | 2016-12-23 | 2017-06-13 | 深圳市紫光同创电子有限公司 | A kind of data window querying method and circuit |
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