CN101621346A - Source synchronous receiving device with adaptive feedback and source synchronizing method - Google Patents
Source synchronous receiving device with adaptive feedback and source synchronizing method Download PDFInfo
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Abstract
The invention provides a source synchronous receiving device with adaptive feedback and a source synchronizing method. The source synchronous receiving device comprises a source synchronous unit and a source synchronous feedback unit which are connected, wherein the source synchronous unit is used for sampling a received data flow and sending the sampled data to the source synchronous feedback unit and is also used for resetting operation after receiving a resetting trigger of the source synchronous feedback unit; the source synchronous feedback unit is used for receiving and detecting the sampled data and triggering the source synchronous unit to reset after detecting data abnormality. On the premise of not increasing the cost, only a small amount of circuits need to be added on the periphery of a general source synchronous receiving unit so that the source synchronous receiving unit automatically tracks the phase change of an input clock, and the stability of the source synchronous receiving device is improved.
Description
Technical field
The present invention relates to the Optical synchronization digital transmission network field, especially a kind of synchronous receiving system in source and source method for synchronous with self adaptation feedback.
Background technology
Along with the continuous development of the communication technology, more and more higher to the rate requirement of data processing and transmission.The development of high speed data bus not only make processing speed become faster, but also the change system is to the timing mode of data.Because Bus Speed is more and more faster, clock frequency is more and more higher, and it is higher to cause settling time of data sampling and retention time to require, and traditional system synchronization mode is difficult to accomplish the stable sampling to high speed signal.
In order to realize stable sampling, many employings source simultaneous techniques in the existing field to high speed signal.As shown in Figure 1, the interface that connects source end chip (also can be described as source end processor) and place end chip (also can be described as place end processor) is the source sync cap, and this interface is a parallel interface of handling the two-forty high band wide data.Source end chip sends to place end chip simultaneously with high-speed data and corresponding high-frequency clock, in the end chip of place the synchronous receiving system in source (mainly comprising the high-frequency clock processing module) with the high-frequency clock received as the reference clock, produce with the high-frequency clock frequently and the low-speed clock of frequency division, and high-speed data being converted into low speed data according to the low-speed clock behind high-frequency clock and the frequency division, the main control module that offers place end chip uses.
The key of source simultaneous techniques is the high-frequency clock processing module in the synchronous receiving system in source, by processing modes such as minute frequency delay, the rising edge of clock is alignd (rising of clock is alignd with the steady component of data and can be guaranteed that sampling time and retention time are simultaneously for optimum) with the steady component (being the mid portion of data) of data in clock-unit's time, thereby improved the surplus of the settling time and the retention time of data sampling, with respect to the sequential requirement of traditional easier satisfied sampling of system synchronization mode, improved the stability of data sampling.
Along with the raising of programming device scale, and the decline of cost, a large amount of programming devices that use carry out signal processing on the communication apparatus at present.Programming device receives the clock signal of input, recover module (as phase-locked loop etc.) by clock internal, the recovering clock signals of input is become clock signal of system, the system clock that keep to recover and the clock signal frequency of input, phase place consistent used the service signal that recovered clock is handled input like this.Because technical reason, there is inherent shortcoming in current programming device internal clocking processing unit: the clock that recovers can be consistent with the input clock holding frequency, but can only keep initial tracking phase place on the phase place.
There is such problem equally in the synchronous receiving system in realization source in programming device.Its high-frequency clock processing module mainly is made up of a state machine, when electrification reset, state machine carries out phase alignment according to the high-speed clock signal of input, when meeting certain requirements, state machine enters the phase alignment state, and after this no matter how clock changes, state machine state no longer changes, the phase place of can not aliging again again that is to say the phase change that can not follow the tracks of input clock in the programming device more automatically.Like this when the input the clock phase saltus step time, recovered clock signal just keeps phase place consistent with old clock signal, rather than and new input clock signal phase place be consistent, clock recovered mistake can occur when handling new incoming traffic, be difficult to again to keep justified with new input data, can't operate as normal.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of synchronous receiving system in source and source method for synchronous with self adaptation feedback, makes the phase place of the synchronous receiving system in source from the motion tracking input clock, thus the stability of the synchronous receiving system in raising source.
In order to address the above problem, the invention provides a kind of synchronous receiving system in source with self adaptation feedback, the synchronous receiving system in described source is arranged in the place end processor of Optical synchronization digital transmission network network, described place end processor is from source end processor receive clock and data, described clock is carried out divide operation, and according to the clock that produces after the divide operation to the described data generation sampled data of sampling, the synchronous receiving system in described source comprises continuous source lock unit and source synchronous feedback unit, described source lock unit, after being used for the data flow that receives carried out sampling operation, sampled data is sent to described source synchronous feedback unit; Also be used for after the reset trigger that receives described source synchronous feedback unit, carrying out reset operation; Described source synchronous feedback unit is used for receiving and detecting described sampled data, and after detecting data exception, triggers described source lock unit and reset.
Further, the synchronous receiving system in above-mentioned source also has following characteristics:
Described source synchronous feedback unit comprises the local reset feedback unit; Described local reset feedback unit comprises local reset detection module and local reset indicating module; Described source lock unit has the local reset port, and links to each other with the output of described local reset indicating module by described local reset port; Described local reset detection module is used for described sampled data is detected, and after detecting data exception, sends triggering message to described local reset indicating module; Described local reset indicating module is after being used to receive the triggering message of described local reset detection module, to the local reset port transmission triggering message of described source lock unit; Described source lock unit after also being used for receiving triggering signal from described local reset port, carries out local reset, to the clock phase adjustment of delaying time.
Further, the synchronous receiving system in above-mentioned source also has following characteristics:
Described local reset feedback unit also comprises respectively the local reset accumulator that links to each other with the local reset indicating module with the local reset detection module; Described local reset detection module is used for described sampled data is detected, and after detecting data exception, sends triggering message to described local reset accumulator; Described local reset accumulator is used for the triggering message that described local reset detection module sends is added up, and sends triggering message to described local reset indicating module after triggering times is added to the default number of times; Described local reset indicating module after being used to receive the triggering message of described local reset accumulator, sends triggering message to described source lock unit.
Further, the synchronous receiving system in above-mentioned source also has following characteristics:
Described source synchronous feedback unit also comprises the Global reset feedback unit; Described Global reset feedback unit comprises Global reset detection module and Global reset indicating module; Described source lock unit has the Global reset port, and links to each other with the output of described Global reset indicating module by described Global reset port; Described Global reset detection module is used for described sampled data is detected, and after detecting data exception, sends triggering message to described Global reset indicating module; Described Global reset indicating module is after being used to receive the triggering message of described Global reset detection module, to the Global reset port transmission triggering message of described source lock unit; Described source lock unit after also being used for receiving triggering signal from described Global reset port, carries out Global reset, and clock phase again aligns.
Further, the synchronous receiving system in above-mentioned source also has following characteristics:
Described Global reset feedback unit also comprises respectively the Global reset accumulator that links to each other with the Global reset indicating module with the Global reset detection module; Described Global reset detection module is used for described sampled data is detected, and after detecting data exception, sends triggering message to described Global reset accumulator; Described Global reset accumulator is used for the triggering message that described Global reset detection module sends is added up, and sends triggering message to described Global reset indicating module after triggering times is added to the default number of times; Described Global reset indicating module after being used to receive the triggering message of described Global reset accumulator, sends triggering message to described source lock unit.
Further, the synchronous receiving system in above-mentioned source also has following characteristics:
Described Global reset detection module is used for described sampled data is carried out the LOF alarm detection; Described local reset detection module is used for described sampled data is carried out Error detection; Perhaps; Described Global reset detection module is used for described sampled data is carried out Error detection; Described local reset detection module is used for described sampled data is carried out the LOF alarm detection.
In order to solve the problems of the technologies described above, the present invention also provides a kind of source method for synchronous that uses the synchronous receiving system in the described source of claim 1, comprise: the source lock unit is sent to the source synchronous feedback unit with sampled data after the data flow that receives is carried out sampling operation; The source synchronous feedback unit receives and detects described sampled data, and after detecting data exception, triggers described source lock unit and reset; Described source lock unit carries out reset operation after the reset trigger that receives described source synchronous feedback unit.
Further, above-mentioned source method for synchronous also has following characteristics:
The local reset detection module of source synchronous feedback unit detects described sampled data, send to trigger message detecting the data exception backward office portion accumulator blocks that resets; The local reset accumulator adds up to the triggering message that described local reset detection module sends, and sends triggering message to described local reset indicating module after triggering times is added to the default number of times; After the local reset indicating module receives described triggering message, to the local reset port transmission triggering message of described source lock unit; Described source lock unit carries out local reset after receiving triggering signal from described local reset port, to the clock phase adjustment of delaying time.
Further, above-mentioned source method for synchronous also has following characteristics:
The Global reset detection module of source synchronous feedback unit detects described sampled data, after detecting data exception, sends triggering message to the Global reset accumulator; The Global reset accumulator adds up to the triggering message that described Global reset detection module sends, and sends triggering message to described Global reset indicating module after triggering times is added to the default number of times; After described Global reset indicating module receives described triggering message, to the Global reset port transmission triggering message of described source lock unit; Described source lock unit carries out Global reset after receiving triggering signal from described Global reset port, and clock phase again aligns.
Further, above-mentioned source method for synchronous also has following characteristics:
Described Global reset detection module carries out the LOF alarm detection to described sampled data; Described local reset detection module carries out Error detection to described sampled data; Perhaps; Described Global reset detection module carries out Error detection to described sampled data; Described local reset detection module carries out the LOF alarm detection to described sampled data.
The synchronous receiving system in source of self adaptation feedback of the present invention, the data by after the synchronous receiving system sampling of detection resources produce alarm indication signal, further utilize alarm indication signal to produce reset signal.And, utilize the characteristics of its Global reset and local reset according to the circuit characteristic of the synchronous receiving element in source, the reset signal of generation is carried out different resetting to the source lock unit, thereby can make the synchronous receiving system in source can follow the tracks of the phase change of input clock automatically.The present invention only needs to add a spot of circuit in the synchronous receiving element of universal source periphery under the prerequisite that does not increase cost, makes the synchronous receiving element in source from motion tracking input clock phase change, thus the stability of the synchronous receiving system in raising source.
Description of drawings
Fig. 1 is the schematic diagram of source sync cap in the prior art;
Fig. 2 is the composition structure chart of the synchronous receiving system in source among the embodiment;
Fig. 3 is the circuit diagram of source lock unit among the embodiment;
Fig. 4 is the schematic diagram that the clock alignment unit of source lock unit among the embodiment is carried out phase alignment;
Fig. 5 is the composition structure chart of source synchronous feedback unit among the embodiment;
Fig. 6 is the Business Processing schematic diagram that comprises the STM-16 business board of active synchronous receiving system in the specific embodiment.
Embodiment
In the present embodiment, the synchronous receiving system in source is arranged in the place end processor of Optical synchronization digital transmission network network, place end processor receives high-frequency clock and high-speed data from source end processor, described high-frequency clock is carried out divide operation, and according to the low-speed clock that produces after the divide operation high-speed data is sampled that to produce sampled data be low speed data.
As shown in Figure 2, the synchronous receiving system in source with self adaptation feedback comprises continuous source lock unit and source synchronous feedback unit, and the source lock unit has local reset port and Global reset port, links to each other with two outputs of source synchronous feedback unit respectively.
The source lock unit is used to receive high-speed data, and after the data flow that receives carried out sampling operation, sampled data is sent to the source synchronous feedback unit; Also be used for after the local reset that receives described source synchronous feedback unit triggers, carrying out the local reset operation, after the Global reset that receives described source synchronous feedback unit triggers, carry out the Global reset operation;
Described source synchronous feedback unit is used to detect the sampled data that receives, and after detecting data exception, triggers described source lock unit and reset.
The source lock unit by adjusting the phase place of input clock, makes the justified of the data in the clock-unit that adjusts back rising edge clock and input, and utilizes this clock data are gone here and there and to change, and realization is to the correct sampling of data.As shown in Figure 3, the source lock unit comprises clock alignment module, time delay module, serial data and modular converter, clock string and modular converter;
Clock alignment module, an output are the Global reset ports of source synchronizer, and after the source synchronizer resetted, the state machine of clock alignment module carried out phase alignment according to the clock signal of input.The value of the sampling clock that clock alignment module receive clock serial-parallel conversion circuit sends, as shown in Figure 4, with 4 frequency divisions is example, when detecting the input sample value and be 0000, output clock speed (INC) index signal, the control delay unit is delayed time to input clock, continuing then to detect the clock sampling value, is 1111 up to detecting sampled value, thinks that the rising edge of clock this moment aligns with the data middle, state machine enters the phase alignment state, after this no matter how clock changes, state machine state no longer changes, the phase place of can not aliging again again, only after resetting, just can restart clock alignment module alignment phase place.
Delay circuit, enable in the clock alignment circuit under the state of (ICE) its operation, after receiving clock speed (INC) index signal of clock alignment circuit output, the clock that receives is delayed time, and the clock after will delaying time is input to the clock alignment unit and carries out phase alignment again, till state machine alignment phase place.Delay circuit has two reseting ports, and one is the Global reset port (Reset) of the synchronous receiving element in source, and this reset signal resets to all circuit of the synchronous receiving element in whole source; Another one is the distinctive local reset port of delay circuit (Idly_reset), and delay circuit only resets.The effect of these two reset signals is inequality, wherein global reset signal since can reset clock alignment circuit, thereby the clock phase that can cause exporting produces bigger saltus step; The local reset circuit only works to delay circuit, by the time-delay of the clock signal of input being controlled the phase place of clock.From effect, global reset signal is equivalent to the coarse adjustment signal of the synchronous receiving element in source, and local reset signal is equivalent to the fine tuning signal of the synchronous receiving element in source.
Serial data and modular converter are used for according to the clock after the time-delay high-speed data being sampled;
Clock string and modular converter, being used for according to the clock after the time-delay high-frequency clock being sampled is frequency division (for example 4 frequency divisions), utilize clock behind the frequency division finish the string and the conversion of clock signal and will change after the clock sampling value output to clock alignment unit (under 4 frequency division situations, string and conversion back clock sampling value only may be 0000 or 1111).
As shown in Figure 5, the source synchronous feedback unit that links to each other with the source lock unit comprises local reset feedback unit and Global reset feedback unit; The local reset feedback unit comprises local reset detection module and the local reset indicating module that links to each other successively, the output of local reset indicating module links to each other with the local reset interface of source lock unit, and the local reset detection module can also link to each other by a local reset accumulator with the local reset indicating module; The Global reset feedback unit comprises continuous Global reset detection module and local reset indicating module, the output of Global reset indicating module links to each other with the Global reset interface of source lock unit, and the Global reset detection module can also link to each other by a Global reset accumulator with the Global reset indicating module;
The local reset detection module is used for the sampled data that receives from the source lock unit is detected, and after detecting data exception, directly sends to the local reset indicating module and triggers message or send triggering message to the local reset accumulator;
The local reset accumulator, be used for after receiving the triggering message of local reset detection module, the triggering message that local reset detection module is sent adds up, after being added to the default number of times, triggering times sends triggering message to described local reset indicating module, and with the triggering times zero clearing of writing down.
The local reset indicating module after being used to receive after the triggering message of local reset detection module or receiving the triggering message that the local reset accumulator sends, sends to the local reset port of described source lock unit and to trigger message.
The Global reset detection module is used for the sampled data that receives from the source lock unit is detected, and after detecting data exception, directly sends to the Global reset indicating module and triggers message or send triggering message to the Global reset accumulator;
The Global reset accumulator, be used for after receiving the triggering message of Global reset detection module, the triggering message that the Global reset detection module is sent adds up, after being added to the default number of times, triggering times sends triggering message to described Global reset indicating module, and with the triggering times zero clearing of writing down.
The Global reset indicating module after being used to receive after the triggering message of Global reset detection module or receiving the triggering message that the Global reset accumulator sends, sends to the Global reset port of described source lock unit and to trigger message.
Described source lock unit after also being used for receiving triggering signal from described local reset port, carries out local reset, to the clock phase adjustment of delaying time; After receiving triggering signal from described Global reset port, carry out Global reset, clock phase again aligns.
When the Global reset detection module carried out the LOF alarm detection to described sampled data in the said apparatus, the local reset detection module carried out Error detection to described sampled data; Perhaps; When the Global reset detection module carries out Error detection to described sampled data; The local reset detection module carries out the LOF alarm detection to described sampled data.The LOF alarm detection is to be used for detecting whether frame losing of data, for example: when continuous 24 frames in data detect less than frame head, then produce the LOF alarm, in the time of after continuous 24 frames find frame head, do not produce the LOF alarm.Accumulator adds up to LOF alarm, be added to default value after, the indicating module that resets produces reset trigger.Error detection is used for detecting data and error code whether occurs, for example, the B1 Error detection, every frame data are carried out BIP8 to be calculated, and result calculated and the B1 value received compared, if unanimity then illustrate that the explanation of this frame does not have error code, if inconsistent, illustrate that then these frame data have the B1 error code, produce an error code alarm signal.Accumulator adds up to LOF alarm, be added to default value after, the indicating module that resets produces reset trigger.
When the indicating module that all resets produced reset trigger, source lock unit reset clock alignment module made the clock phase saltus step, thereby makes service disconnection.When the local reset indicating module produced reset trigger, the source lock unit only resetted to Postponement module, and the source lock unit only carries out small time-delay adjustment (for example time-delay adjustment of 75PS) to phase place, can not make service disconnection.
Use the source method for synchronous of the synchronous receiving system in above-mentioned source to comprise: the source lock unit is sent to the source synchronous feedback unit with sampled data after the data flow that receives is carried out sampling operation; The source synchronous feedback unit receives and detects described sampled data, and after detecting data exception, triggers described source lock unit and reset; Described source lock unit carries out reset operation after the reset trigger that receives described source synchronous feedback unit.
The processing procedure of local reset specifically comprises: the local reset detection module of source synchronous feedback unit detects described sampled data, send to trigger message detecting the data exception backward office portion accumulator blocks that resets; The local reset accumulator adds up to the triggering message that described local reset detection module sends, and sends triggering message to described local reset indicating module after triggering times is added to the default number of times; After the local reset indicating module receives described triggering message, to the local reset port transmission triggering message of described source lock unit; Described source lock unit carries out local reset after receiving triggering signal from described local reset port, to the clock phase adjustment of delaying time.
The processing procedure of Global reset specifically comprises: the Global reset detection module of source synchronous feedback unit detects described sampled data, after detecting data exception, sends triggering message to the Global reset accumulator; The Global reset accumulator adds up to the triggering message that described Global reset detection module sends, and sends triggering message to described Global reset indicating module after triggering times is added to the default number of times; After described Global reset indicating module receives described triggering message, to the Global reset port transmission triggering message of described source lock unit; Described source lock unit carries out Global reset after receiving triggering signal from described Global reset port, and clock phase again aligns.
Specific embodiment:
As shown in Figure 6, the source Synchronous Processing with STM-16 business board in the SDH (Synchronous Digital Hierarchy) (SDH) is that example is described in further detail.
In the STM-16 business board, the data of external chip output 622M with road clock and 4bit * 622M, in Business Processing field programmable gate array (Field Programmable Gate Array is called for short FPGA), adopt the source lock unit of band self adaptation feedback that data are sampled.
In the running, after the data with road clock and 4bit * 622M of the 622M of input are sampled through the source lock unit, the clock of output 311M and the data of 8 * 311M, feedback unit detects data then, and for example detection of loss of frames detects or the B1 Error detection.Because the generation of alarm and disappearance all have time-delay, more excellent selection is, alarm signal is added up, when the alarm signal number is added to default numerical value, produce indication of local reset feedback or the indication of Global reset feedback to the source lock unit, for example the numerical value of default is 30, and when promptly accumulator meter record accumulative total had 30 frame data LOF or error code are arranged, the indicating module that resets produced to the source lock unit.For example, LOF is added up, for example adopt the 66M clock to carry out counting statistics, when the LOF alarm reaches certain hour (such as 30 frames), produce a reset pulse, and to the summary counter zero clearing, this reset pulse is as the global reset signal of source sync cap, and be linked into Global reset port shown in Figure 5.Adopt every frame to add up to adding up of B1 error code frame in the frame head position, the counter of certain bit wide is set, when the counting of B1 error code frame satisfies this and requires, produce a reseting pulse signal, and, this reseting pulse signal is inserted local reset port shown in Figure 5 to the summary counter zero clearing.
The present invention in the synchronous receiving system in source, after each clock phase saltus step (for example plugging optical fiber), can both correctly follow the tracks of the variation of input clock phase place, has quoted above-mentioned clock-reset function with self adaptation feedback.The present invention only needs to add a spot of circuit in the synchronous receiving element of universal source periphery under the prerequisite that does not increase cost, makes the synchronous receiving element in source from motion tracking input clock phase change, thus the stability of the synchronous receiving system in raising source.
Above specific implementation method is a concrete enforcement example of the present invention, is not limited to the present invention, every in realization principle of the present invention and spirit any modification, be equal to replacement and work such as improvement, all should be included within protection scope of the present invention.
Claims (10)
1, a kind of synchronous receiving system in source with self adaptation feedback, the synchronous receiving system in described source is arranged in the place end processor of Optical synchronization digital transmission network network, described place end processor is from source end processor receive clock and data, described clock is carried out divide operation, and according to the clock that produces after the divide operation to the described data generation sampled data of sampling, it is characterized in that
The synchronous receiving system in described source comprises continuous source lock unit and source synchronous feedback unit,
Described source lock unit after being used for the data flow that receives carried out sampling operation, is sent to described source synchronous feedback unit with sampled data; Also be used for after the reset trigger that receives described source synchronous feedback unit, carrying out reset operation;
Described source synchronous feedback unit is used for receiving and detecting described sampled data, and after detecting data exception, triggers described source lock unit and reset.
2, the synchronous receiving system in source as claimed in claim 1 is characterized in that,
Described source synchronous feedback unit comprises the local reset feedback unit; Described local reset feedback unit comprises local reset detection module and local reset indicating module; Described source lock unit has the local reset port, and links to each other with the output of described local reset indicating module by described local reset port;
Described local reset detection module is used for described sampled data is detected, and after detecting data exception, sends triggering message to described local reset indicating module;
Described local reset indicating module is after being used to receive the triggering message of described local reset detection module, to the local reset port transmission triggering message of described source lock unit;
Described source lock unit after also being used for receiving triggering signal from described local reset port, carries out local reset, to the clock phase adjustment of delaying time.
3, the synchronous receiving system in source as claimed in claim 2 is characterized in that,
Described local reset feedback unit also comprises respectively the local reset accumulator that links to each other with the local reset indicating module with the local reset detection module;
Described local reset detection module is used for described sampled data is detected, and after detecting data exception, sends triggering message to described local reset accumulator;
Described local reset accumulator is used for the triggering message that described local reset detection module sends is added up, and sends triggering message to described local reset indicating module after triggering times is added to the default number of times;
Described local reset indicating module after being used to receive the triggering message of described local reset accumulator, sends triggering message to described source lock unit.
4, as claim 1, the synchronous receiving system in 2 or 3 described sources, it is characterized in that,
Described source synchronous feedback unit also comprises the Global reset feedback unit; Described Global reset feedback unit comprises Global reset detection module and Global reset indicating module; Described source lock unit has the Global reset port, and links to each other with the output of described Global reset indicating module by described Global reset port;
Described Global reset detection module is used for described sampled data is detected, and after detecting data exception, sends triggering message to described Global reset indicating module;
Described Global reset indicating module is after being used to receive the triggering message of described Global reset detection module, to the Global reset port transmission triggering message of described source lock unit;
Described source lock unit after also being used for receiving triggering signal from described Global reset port, carries out Global reset, and clock phase again aligns.
5, the synchronous receiving system in source as claimed in claim 4 is characterized in that,
Described Global reset feedback unit also comprises respectively the Global reset accumulator that links to each other with the Global reset indicating module with the Global reset detection module;
Described Global reset detection module is used for described sampled data is detected, and after detecting data exception, sends triggering message to described Global reset accumulator;
Described Global reset accumulator is used for the triggering message that described Global reset detection module sends is added up, and sends triggering message to described Global reset indicating module after triggering times is added to the default number of times;
Described Global reset indicating module after being used to receive the triggering message of described Global reset accumulator, sends triggering message to described source lock unit.
6, the synchronous receiving system in source as claimed in claim 5 is characterized in that,
Described Global reset detection module is used for described sampled data is carried out the LOF alarm detection; Described local reset detection module is used for described sampled data is carried out Error detection; Perhaps;
Described Global reset detection module is used for described sampled data is carried out Error detection; Described local reset detection module is used for described sampled data is carried out the LOF alarm detection.
7, a kind of source method for synchronous that uses the synchronous receiving system in the described source of claim 1 comprises:
The source lock unit is sent to the source synchronous feedback unit with sampled data after the data flow that receives is carried out sampling operation; The source synchronous feedback unit receives and detects described sampled data, and after detecting data exception, triggers described source lock unit and reset; Described source lock unit carries out reset operation after the reset trigger that receives described source synchronous feedback unit.
8, source as claimed in claim 1 method for synchronous is characterized in that,
The local reset detection module of source synchronous feedback unit detects described sampled data, send to trigger message detecting the data exception backward office portion accumulator blocks that resets; The local reset accumulator adds up to the triggering message that described local reset detection module sends, and sends triggering message to described local reset indicating module after triggering times is added to the default number of times; After the local reset indicating module receives described triggering message, to the local reset port transmission triggering message of described source lock unit; Described source lock unit carries out local reset after receiving triggering signal from described local reset port, to the clock phase adjustment of delaying time.
9, source as claimed in claim 1 method for synchronous is characterized in that,
The Global reset detection module of source synchronous feedback unit detects described sampled data, after detecting data exception, sends triggering message to the Global reset accumulator; The Global reset accumulator adds up to the triggering message that described Global reset detection module sends, and sends triggering message to described Global reset indicating module after triggering times is added to the default number of times; After described Global reset indicating module receives described triggering message, to the Global reset port transmission triggering message of described source lock unit; Described source lock unit carries out Global reset after receiving triggering signal from described Global reset port, and clock phase again aligns.
10, source method for synchronous as claimed in claim 8 or 9 is characterized in that,
Described Global reset detection module carries out the LOF alarm detection to described sampled data; Described local reset detection module carries out Error detection to described sampled data; Perhaps;
Described Global reset detection module carries out Error detection to described sampled data; Described local reset detection module carries out the LOF alarm detection to described sampled data.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910159124 CN101621346B (en) | 2009-07-09 | 2009-07-09 | Source synchronous receiving device with adaptive feedback and source synchronizing method |
| PCT/CN2010/073682 WO2011003318A1 (en) | 2009-07-09 | 2010-06-08 | Source synchronization receiving device and source synchronization method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910159124 CN101621346B (en) | 2009-07-09 | 2009-07-09 | Source synchronous receiving device with adaptive feedback and source synchronizing method |
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| Publication Number | Publication Date |
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| CN101621346A true CN101621346A (en) | 2010-01-06 |
| CN101621346B CN101621346B (en) | 2013-03-27 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200910159124 Expired - Fee Related CN101621346B (en) | 2009-07-09 | 2009-07-09 | Source synchronous receiving device with adaptive feedback and source synchronizing method |
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| Country | Link |
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| CN (1) | CN101621346B (en) |
| WO (1) | WO2011003318A1 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011003318A1 (en) * | 2009-07-09 | 2011-01-13 | 中兴通讯股份有限公司 | Source synchronization receiving device and source synchronization method |
| CN101951313A (en) * | 2010-09-08 | 2011-01-19 | 烽火通信科技股份有限公司 | FPGA-based SFI4.1 device |
| CN103840934B (en) * | 2014-02-20 | 2017-01-04 | 烽火通信科技股份有限公司 | A kind of expense transmission method automatically recovered based on clock and device |
| CN107168220A (en) * | 2017-04-05 | 2017-09-15 | 深圳市恒扬数据股份有限公司 | A kind of programmable logic controller (PLC) part and its high speed signal method of reseptance |
| CN109831274A (en) * | 2017-11-23 | 2019-05-31 | 杭州海康威视数字技术股份有限公司 | A kind of data transmission method and equipment and receiver |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3565966B2 (en) * | 1995-12-20 | 2004-09-15 | 株式会社ルネサステクノロジ | Communication device |
| US6311285B1 (en) * | 1999-04-27 | 2001-10-30 | Intel Corporation | Method and apparatus for source synchronous transfers at frequencies including an odd fraction of a core frequency |
| CN1322715C (en) * | 2003-03-20 | 2007-06-20 | 华为技术有限公司 | Method and device for extending routing distance of network processor medium access interface |
| CN1286289C (en) * | 2003-04-25 | 2006-11-22 | 中兴通讯股份有限公司 | Circuit for recovering timing data and implementing method |
| US7135905B2 (en) * | 2004-10-12 | 2006-11-14 | Broadcom Corporation | High speed clock and data recovery system |
| CN1645810A (en) * | 2004-11-18 | 2005-07-27 | 北京锐安科技有限公司 | Local resetting method and device for improving reliability of FPGA |
| CN101621346B (en) * | 2009-07-09 | 2013-03-27 | 中兴通讯股份有限公司 | Source synchronous receiving device with adaptive feedback and source synchronizing method |
-
2009
- 2009-07-09 CN CN 200910159124 patent/CN101621346B/en not_active Expired - Fee Related
-
2010
- 2010-06-08 WO PCT/CN2010/073682 patent/WO2011003318A1/en active Application Filing
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011003318A1 (en) * | 2009-07-09 | 2011-01-13 | 中兴通讯股份有限公司 | Source synchronization receiving device and source synchronization method |
| CN101951313A (en) * | 2010-09-08 | 2011-01-19 | 烽火通信科技股份有限公司 | FPGA-based SFI4.1 device |
| CN101951313B (en) * | 2010-09-08 | 2013-04-10 | 烽火通信科技股份有限公司 | FPGA-based SFI4.1 device |
| CN103840934B (en) * | 2014-02-20 | 2017-01-04 | 烽火通信科技股份有限公司 | A kind of expense transmission method automatically recovered based on clock and device |
| CN107168220A (en) * | 2017-04-05 | 2017-09-15 | 深圳市恒扬数据股份有限公司 | A kind of programmable logic controller (PLC) part and its high speed signal method of reseptance |
| CN107168220B (en) * | 2017-04-05 | 2019-09-06 | 深圳市恒扬数据股份有限公司 | A kind of programmable logic controller (PLC) part and its high speed signal method of reseptance |
| CN109831274A (en) * | 2017-11-23 | 2019-05-31 | 杭州海康威视数字技术股份有限公司 | A kind of data transmission method and equipment and receiver |
| CN109831274B (en) * | 2017-11-23 | 2021-07-20 | 杭州海康威视数字技术股份有限公司 | Data transmission method and equipment and receiver |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101621346B (en) | 2013-03-27 |
| WO2011003318A1 (en) | 2011-01-13 |
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Effective date of registration: 20171229 Address after: The town of West Bay 075000 Zhangjiakou city of Hebei province Chongli County Changqing Road, Washington still Residential District 1 Building 1 unit 303 room Patentee after: Liu Guichen Address before: 518057 Nanshan District high tech Industrial Park, Guangdong, South Road, science and technology, ZTE building, legal department Patentee before: ZTE Corporation |
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