CN201918891U - High-voltage MOSFET (metal-oxide semiconductor field effect transistor) driving circuit - Google Patents

Abstract

Disclosed is a high-voltage MOSFET (metal-oxide semiconductor field effect transistor) driving circuit which comprises a first high-voltage switching circuit PMOSFET (positive metal-oxide semiconductor field effect transistor) and a secondary high-voltage switching circuit NMOSFET (negative metal-oxide semiconductor field effect transistor) of a driving switch component and also comprises a first level displacement circuit, a secondary level displacement circuit, a first voltage-distributing circuit, a secondary voltage-distributing circuit, a first grid-controlling circuit and a secondary grid-controlling circuit; on main channels of the high-voltage PMOSFET and the high-voltage NMOSFET of the driving switch component, a voltage-regulator diode is used for replacing an audion in the traditional high-voltage MOSFET driving circuit, so that the static power consumption of the whole circuit is greatly reduced; and the voltage is directly distributed by a resistor, so as to ensure that the grid-source interelectrode voltage between the high-voltage PMOSFET and the high-voltage NMOSFET of the driving switch component does not exceed the highest value of the grid-source interelectrode voltage, therefore, the limit of the highest grid-source interelectrode voltage is guaranteed, and the load regulation of the whole circuit can be effectively reduced.

Description

The high-voltage MOSFET drive circuit

Technical field

The utility model relates to the MOSFET Drive and Control Circuit, refers to a kind of drive circuit of high-voltage MOSFET especially.

Background technology

Traditional high-voltage MOSFET (metal-oxide semiconductor fieldeffect transistor) drive circuit circuit diagram such as Fig. 1, its annexation is: input signal Vin directly links to each other with the base stage of triode NPN pipe Q1 and the base stage of triode PNP pipe Q2, the emitter of triode NPN pipe Q1 links to each other with the ground of whole high-voltage MOSFET drive circuit with the emitter of triode PNP pipe Q2, the collector electrode of triode Q1 links to each other with an end of resistance R 2, the other end of resistance R 2 is coupled directly to the grid of driving switch assembly high voltage PMOS FET P1, capacitor C 1 and resistance R 1 parallel coupled are between the grid source of driving switch assembly high voltage PMOS FET, the anode of voltage stabilizing didoe DZ1 links to each other with the grid of driving switch assembly high voltage PMOS FET, and the negative electrode of voltage stabilizing didoe DZ1 links to each other with the source electrode of driving switch assembly high voltage PMOS FET and is coupled in high direct voltage positive supply Vdd; The collector electrode of triode Q2 links to each other with an end of resistance R 3, the other end of resistance R 3 is coupled directly to the grid of driving switch assembly high pressure NMOS FET, capacitor C 2 and resistance R 4 parallel coupled are between the grid source of driving switch assembly high pressure NMOS FET, the negative electrode of voltage stabilizing didoe DZ2 links to each other with the grid of driving switch assembly high pressure NMOS FET, and the anode of voltage stabilizing didoe DZ2 links to each other with the source electrode of driving switch assembly high pressure NMOS FET and is coupled in high direct voltage negative supply-Vss; The drain electrode of driving switch assembly high voltage PMOS FET P1 directly links to each other as the output Vout of whole high-voltage MOSFET drive circuit with the drain electrode of driving switch assembly high pressure NMOS FET.The shortcoming of this traditional high-voltage MOSFET drive circuit is: 1, at the main channel triode Q1 of driving switch assembly high voltage PMOS FET P1 and high pressure NMOS FET N1, Q2 when high voltage source is worked, will certainly increase the quiescent dissipation of entire circuit; 2, because driving switch assembly high voltage PMOS FET and their gate-source voltage of high pressure NMOS FET all have the restriction of maximum gate voltage between source electrodes in the high-voltage MOSFET drive circuit, (generally can not surpass 20V), if surpass this restriction, device MOSFET just damages easily, the grid source electrode of driving switch assembly high voltage PMOS FET and high pressure NMOS FET directly meets voltage stabilizing didoe DZ1, DZ2, guarantee that their gate-source voltage of driving switch assembly MOSFET is no more than maximum gate voltage between source electrodes value, but will make the turn-off time of driving switch assembly high voltage PMOS FET and high pressure NMOS FET prolong like this, thereby cause the conducting simultaneously of driving switch assembly high voltage PMOS FET and high pressure NMOS FET upper and lower bridge arm, not only consume extra power consumption and load regulation bigger beyond, even can cause burning out of driving switch assembly high voltage PMOS FET and high pressure NMOS FET.

The utility model content

The utility model provides a kind of novel high-voltage MOSFET drive circuit that can overcome driving switch assembly high voltage PMOS FET and high pressure NMOS FET upper and lower bridge arm conducting simultaneously phenomenon.

For this reason, adopt following technical scheme: a kind of high-voltage MOSFET drive circuit, comprise the driving switch assembly first high voltage switch circuit PMOSFET and the second high voltage switch circuit NMOSFET, it also comprises first level displacement circuit, second level displacement circuit, first bleeder circuit, second bleeder circuit, first grid control circuit and second grid control circuit; The maximum potential of one termination entire circuit of described first bleeder circuit, an end of its other end and described first level displacement circuit is coupled to A; And the other end of this first level displacement circuit links to each other with an end of described second level displacement circuit and be coupled to input signal Vin; One end of the other end of this second level displacement circuit and second bleeder circuit is coupled to B; The minimum level of another termination entire circuit of second bleeder circuit; The output C of described first bleeder circuit links to each other with the input of first grid control circuit, the output E of first grid control circuit directly controls the first high voltage switch circuit PMOSFET, and high direct voltage positive supply Vdd also links to each other with first high-voltage switch gear electricity PMOSFET with the first grid control circuit simultaneously; The output D of described second bleeder circuit links to each other with the input of second grid control circuit, the output F of second grid control circuit directly controls the second high voltage switch circuit NMOSFET, and high direct voltage negative supply-Vss also links to each other with the second high voltage switch circuit NMOSFET with the second grid control circuit simultaneously.

As optimization: described first, second level displacement circuit is voltage stabilizing didoe, voltage stabilizing didoe anode in first level displacement circuit connects input signal, negative electrode is coupled to A, and the voltage stabilizing didoe negative electrode in second level displacement circuit connects input signal, and anode is coupled to B.

Described first, second bleeder circuit is a plurality of resistance and is in series, series resistance in first bleeder circuit must guarantee the first high voltage switch circuit gate source voltage greater than its cut-in voltage, less than its maximum gate source voltage, series resistance in second bleeder circuit must guarantee the second high voltage switch circuit gate source voltage greater than its cut-in voltage, less than its maximum gate source voltage.

Described first, second grid control circuit all is made up of electric capacity and fast recovery diode; Electric capacity and fast recovery diode are in parallel in the first grid control circuit, and the anode of this fast recovery diode links to each other with the grid of first high voltage switch circuit, and negative electrode is coupled to high direct voltage positive supply Vdd; Electric capacity and fast recovery diode parallel connection in the second grid control circuit, the anode of this fast recovery diode links to each other with the grid of second high voltage switch circuit, and negative electrode is coupled to high direct voltage negative supply-Vss.

The utility model is compared with conventional high-tension MOSFET drive circuit following advantage: replace triode Q1 in the conventional high-tension MOSFET drive circuit with voltage stabilizing didoe on the main channel of driving switch assembly high voltage PMOS FET and high pressure NMOS FET, Q2 has reduced the quiescent dissipation of whole drive circuit greatly.

The utility model directly guarantees that with the mode of electric resistance partial pressure driving switch assembly high voltage PMOS FET and their grid voltage between source electrodes of high pressure NMOS FET are no more than maximum gate voltage between source electrodes value, both can guarantee the restriction of maximum gate voltage between source electrodes, can also effectively reduce the load regulation of entire circuit, divider resistance guarantees that switch module high voltage PMOS FET and high pressure NMOS FET their gate-source voltage when opening (is generally 2V～4V), less than the restriction of maximum gate voltage between source electrodes (being generally 20V) greater than their cut-in voltage.

The utility model is directly with voltage stabilizing didoe DZ1, DZ2 in the traditional high-voltage MOSFET drive circuit of fast recovery diode replacement, increase the turn-off speed of driving switch assembly high voltage PMOS FET and high pressure NMOS FET, strict like this conducting when having avoided driving switch assembly high voltage PMOS FET and high pressure NMOS FET upper and lower bridge arm.

Description of drawings

Fig. 1 is traditional high-voltage MOSFET drive circuit schematic diagram; Fig. 2 is a schematic diagram of the present utility model; Fig. 3 is the utility model embodiment circuit diagram; Fig. 4 is the input voltage waveform schematic diagram of the utility model embodiment; Fig. 5 is the grid voltage waveform schematic diagram of the utility model embodiment switch module; Fig. 6 is the output voltage waveforms schematic diagram of the utility model embodiment.

Specific embodiments

Below in conjunction with accompanying drawing the utility model is further described.

With reference to Fig. 2, a kind of high-voltage MOSFET drive circuit, comprise the driving switch assembly first high voltage switch circuit PMOSFET and the second high voltage switch circuit NMOSFET, it also comprises first level displacement circuit, second level displacement circuit, first bleeder circuit, second bleeder circuit, first grid control circuit and second grid control circuit; The maximum potential of one termination entire circuit of described first bleeder circuit is generally high direct voltage positive supply Vdd, and an end of its other end and described first level displacement circuit is coupled to A; And the other end of this first level displacement circuit links to each other with an end of described second level displacement circuit and be coupled to input signal Vin; One end of the other end of this second level displacement circuit and second bleeder circuit is coupled to B; The minimum level of another termination entire circuit of second bleeder circuit is generally high direct voltage negative supply-Vss; The output C of described first bleeder circuit links to each other with the input of first grid control circuit, the output E of first grid control circuit directly controls the first high voltage switch circuit PMOSFET, and high direct voltage positive supply Vdd also links to each other with first high-voltage switch gear electricity PMOSFET with the first grid control circuit simultaneously; The output D of described second bleeder circuit links to each other with the input of second grid control circuit, the output F of second grid control circuit directly controls the second high voltage switch circuit NMOSFET, and high direct voltage negative supply-Vss also links to each other with the second high voltage switch circuit NMOSFET with the second grid control circuit simultaneously.

Described first, second level displacement circuit is voltage stabilizing didoe, and the voltage stabilizing didoe anode in first level displacement circuit connects input signal, and negative electrode is coupled to A, and the voltage stabilizing didoe negative electrode in second level displacement circuit connects input signal, and anode is coupled to B.

Described first, second bleeder circuit is a plurality of resistance and is in series, series resistance in first bleeder circuit must guarantee the first high voltage switch circuit gate source voltage greater than its cut-in voltage, less than its maximum gate source voltage, series resistance in second bleeder circuit must guarantee the second high voltage switch circuit gate source voltage greater than its cut-in voltage, less than its maximum gate source voltage.

Described first, second grid control circuit all is made up of electric capacity and fast recovery diode; Electric capacity and fast recovery diode are in parallel in the first grid control circuit, and the anode of this fast recovery diode links to each other with the grid of first high voltage switch circuit, and negative electrode is coupled to high direct voltage positive supply Vdd; Electric capacity and fast recovery diode parallel connection in the second grid control circuit, the anode of this fast recovery diode links to each other with the grid of second high voltage switch circuit, and negative electrode is coupled to high direct voltage negative supply-Vss.

With specific embodiment the utility model is described in further detail below.

With reference to Fig. 3, a kind of high-voltage MOSFET drive circuit comprises driving switch assembly high voltage PMOS FET and high pressure NMOS FET, also comprises voltage stabilizing didoe DZ3, DZ4, fast recovery diode D1, D2, divider resistance R5, R6, R7, R8 and capacitor C 3, C4; Its annexation is as follows: input signal Vin links to each other with anode, the negative electrode of voltage stabilizing didoe DZ3, DZ4 respectively, the negative electrode of this voltage stabilizing didoe DZ3 links to each other with an end of resistance R 6, the other end of this resistance R 6 is coupled directly to the grid of described driving switch assembly high voltage PMOS FET P2, and described capacitor C 3 and described resistance R 5 parallel coupled are between the grid source of described driving switch assembly high voltage PMOS FET P2; The anode of described fast recovery diode D1 links to each other with the grid of driving switch assembly high voltage PMOS FET P2, and its negative electrode links to each other with the source electrode of driving switch assembly high voltage PMOS FET P2 and is coupled in high direct voltage positive supply Vdd; The anode of described voltage stabilizing didoe DZ4 links to each other with an end of described resistance R 7, the other end of this resistance R 7 is coupled directly to the grid of described driving switch assembly high pressure NMOS FET N2, described capacitor C 4 and described resistance R 8 parallel coupled are between the grid source of described driving switch assembly high pressure NMOS FET N2, the negative electrode of described fast recovery diode D2 links to each other with the grid of described driving switch assembly high pressure NMOS FET N2, and the anode of this fast recovery diode D2 links to each other with the source electrode of described driving switch assembly high pressure NMOS FET N2 and is coupled in high direct voltage negative supply-Vss; The drain electrode of described driving switch assembly high voltage PMOS FET P2 directly links to each other as the output Vout of whole high-voltage MOSFET drive circuit with the drain electrode of described driving switch assembly high pressure NMOS FET N2.

Operation principle of the present utility model is specific as follows: with reference to Fig. 4, Fig. 5, Fig. 6, input signal Vin is ± square wave of V1, (t is the input time of input signal when 0≤t≤t1, at 0≤t≤t1 time period input signal is high level), input signal Vin is V1, voltage stabilizing didoe DZ4 work, its anode potential is (V1-UZ), wherein UZ is the voltage stabilizing value of voltage stabilizing didoe DZ4, resistance R 7, total voltage sum is (V1-UZ+Vss) above the R8, by resistance R 7, the electric resistance partial pressure of R8 makes voltage above the resistance R 8, the i.e. gate source voltage of driven unit high pressure NMOS FET N2, reach the cut-in voltage of driven unit high pressure NMOS FET N2, but can not surpass maximum gate voltage between source electrodes value, this moment, the grid B point current potential of driven unit high pressure NMOS FET N2 was V2, wherein: $V2=-(V1-\mathrm{UZ}+\mathrm{Vss})\×\frac{R7}{R7+R8}+(V1-\mathrm{UZ})---\left(1\right)$ Driven unit high pressure NMOS FET N2 conducting this moment, the drain electrode of the drain electrode of driven unit high voltage PMOS FET P2 and driven unit high pressure NMOS FET N2 is the output Vout of whole high-voltage MOSFET drive circuit, driven unit high pressure NMOS FETN2 conducting, make the output Vout of whole high-voltage MOSFET drive circuit directly be pulled to high pressure negative supply-Vss, opening process for driven unit high pressure NMOS FET N2, mainly still lean on the charging of the grid source capacitance of capacitor C 4 and driven unit high pressure NMOS FET N2 to finish, because this charging capacitor is the grid source capacitance sum of capacitor C 4 and driven unit high pressure NMOS FET N2, therefore can satisfy the requirement of unlatching slowly of the high NMOSFET N2 of driven unit.

Corresponding, when 0≤t≤t1, input signal Vin is V1, voltage stabilizing didoe DZ3 does not work, the electric charge that capacitor C 3 is filled previous state need all unload and bleed off, to turn-off driven unit high voltage PMOS FET P2, because the anode of fast recovery diode D1 links to each other with the grid of driven unit high voltage PMOS FET P2, the negative electrode of fast recovery diode D1 links to each other with the source electrode of driven unit high voltage PMOS FET P2, be coupled in high pressure positive supply Vdd, fast recovery diode D1 just can quicken the quick shutoff of driven unit high voltage PMOS FET P2 like this, in this process, can guarantee opening slowly and the quick shutoff of driving switch assembly high voltage PMOS FET P2 of driving switch assembly high pressure NMOS FET N2, thus conducting when driving switch assembly high voltage PMOS FET P2 and high pressure NMOS FET N2 have been avoided in strictness.

When t1≤t≤t2 (is low level at t1≤t≤t2 time period input signal), input signal Vin is-V1, voltage stabilizing didoe DZ3 work, its cathode potential is (UZ-V1), wherein UZ is the voltage stabilizing value of voltage stabilizing didoe DZ3, voltage stabilizing didoe DZ3, the voltage stabilizing value of DZ4 all is UZ, resistance R 5, total voltage sum is (V1-UZ+Vdd) above the R6, by resistance R 5, the electric resistance partial pressure of R6, make voltage above the resistance R 5, it is the gate source voltage of driven unit high voltage PMOS FET P2, reach the cut-in voltage of driven unit high voltage PMOS FET P2, but can not surpass maximum gate voltage between source electrodes value, this moment, the grid A point current potential of driven unit high voltage PMOS FET P2 was V3, wherein: $V3=(V1-\mathrm{UZ}+\mathrm{Vdd})\×\frac{R6}{R5+R6}-(V1-\mathrm{UZ})---\left(2\right)$ Driven unit high voltage PMOS FET P2 conducting this moment, the drain electrode of the drain electrode of driven unit high voltage PMOS FET P2 and driven unit high pressure NMOS FET N2 is the output Vout of whole high-voltage MOSFET drive circuit, driven unit high voltage PMOS FETP2 conducting, make the output Vout of whole high-voltage MOSFET drive circuit directly be pulled to high pressure positive supply Vdd, opening process for driven unit high voltage PMOS FET P2, mainly still lean on the charging of the grid source capacitance of capacitor C 3 and driven unit high voltage PMOS FET P2 to finish, because this charging capacitor is the grid source capacitance sum of capacitor C 3 and driven unit high voltage PMOS FET P2, therefore can satisfy the requirement of unlatching slowly of driven unit high voltage PMOS FET P2.

Corresponding, when t1≤t≤t2, input signal Vin is-V1, voltage stabilizing didoe DZ4 does not work, the electric charge that capacitor C 4 is filled previous state need all unload and bleed off, to turn-off driven unit high pressure NMOS FET N2, because the negative electrode of fast recovery diode D2 links to each other with the grid of driven unit high voltage PMOS FET P2, the anode of fast recovery diode D2 links to each other with the source electrode of driven unit high voltage PMOS FET P2, be coupled in high pressure negative supply-Vss, fast recovery diode D2 just can quicken the quick shutoff of driven unit high pressure NMOS FET N2 like this, in this process, can guarantee opening slowly and the quick shutoff of driving switch assembly high pressure NMOS FET N2 of driving switch assembly high voltage PMOS FET P2, thus conducting when driving switch assembly high voltage PMOS FET P2 and high pressure NMOS FET N2 have been avoided in strictness.

The above; it only is preferred embodiment of the present utility model; be not that the utility model is done any pro forma restriction; any those skilled in the art; in the scope that does not break away from the utility model and disclosed; any simple modification of being done, equivalent variations and modification all belong in the protection range of technical solutions of the utility model.

Claims (4)

1. high-voltage MOSFET drive circuit, comprise the driving switch assembly first high voltage switch circuit PMOSFET and the second high voltage switch circuit NMOSFET, it is characterized in that: it also comprises first level displacement circuit, second level displacement circuit, first bleeder circuit, second bleeder circuit, first grid control circuit and second grid control circuit; The maximum potential of one termination entire circuit of described first bleeder circuit, an end of its other end and described first level displacement circuit is coupled to A; And the other end of this first level displacement circuit links to each other with an end of described second level displacement circuit and be coupled to input signal Vin; One end of the other end of this second level displacement circuit and second bleeder circuit is coupled to B; The minimum level of another termination entire circuit of second bleeder circuit; The output C of described first bleeder circuit links to each other with the input of first grid control circuit, the output E of first grid control circuit directly controls the first high voltage switch circuit PMOSFET, and high direct voltage positive supply Vdd also links to each other with the first high voltage switch circuit PMOSFET with the first grid control circuit simultaneously; The output D of described second bleeder circuit links to each other with the input of second grid control circuit, the output F of second grid control circuit directly controls the second high voltage switch circuit NMOSFET, and high direct voltage negative supply-Vss also links to each other with the second high voltage switch circuit NMOSFET with the second grid control circuit simultaneously.

2. circuit as claimed in claim 1, it is characterized in that: described first, second level displacement circuit is voltage stabilizing didoe, voltage stabilizing didoe anode in first level displacement circuit connects input signal, negative electrode is coupled to A, voltage stabilizing didoe negative electrode in second level displacement circuit connects input signal, and anode is coupled to B.

3. circuit as claimed in claim 1, it is characterized in that: described first, second bleeder circuit is a plurality of resistance and is in series, series resistance in first bleeder circuit must guarantee the first high voltage switch circuit gate source voltage greater than its cut-in voltage, less than its maximum gate source voltage, series resistance in second bleeder circuit must guarantee the second high voltage switch circuit gate source voltage greater than its cut-in voltage, less than its maximum gate source voltage.

4. circuit as claimed in claim 1 is characterized in that, described first, second grid control circuit all is made up of electric capacity and fast recovery diode; Electric capacity and fast recovery diode are in parallel in the first grid control circuit, and the anode of this fast recovery diode links to each other with the grid of first high voltage switch circuit, and negative electrode is coupled to high direct voltage positive supply Vdd; Electric capacity and fast recovery diode parallel connection in the second grid control circuit, the anode of this fast recovery diode links to each other with the grid of second high voltage switch circuit, and negative electrode is coupled to high direct voltage negative supply-Vss.

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