CN105335327A - Reconfigurable/dual redundancy VPX3U signal processing carrier board based on Soc - Google Patents
Reconfigurable/dual redundancy VPX3U signal processing carrier board based on Soc Download PDFInfo
- Publication number
- CN105335327A CN105335327A CN201510675988.6A CN201510675988A CN105335327A CN 105335327 A CN105335327 A CN 105335327A CN 201510675988 A CN201510675988 A CN 201510675988A CN 105335327 A CN105335327 A CN 105335327A
- Authority
- CN
- China
- Prior art keywords
- support plate
- interface
- high speed
- soc
- vpx
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0012—High speed serial bus, e.g. IEEE P1394
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0024—Peripheral component interconnect [PCI]
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Hardware Redundancy (AREA)
- Bus Control (AREA)
- Multi Processors (AREA)
Abstract
The invention discloses a reconfigurable/dual redundancy VPX3U signal processing carrier board based on Soc, under VPX control surface 1GEx1 signalization, a carrier board Soc controller can perform control command dynamic loading and logical function on-line reorganization on a high-performance reconfigurable FPGA (Field Programmable Gate Array), and board-level power and timer management and condition monitoring are completed; a reconfigurable FPGA chip is in interaction with front-end received signals through a standard FMC interface, and multi-function real-time digital signal processing is realized according to a loading program. Meanwhile, a dual-redundancy data bus interface is designed in a VPX connector, and a signal processing carrier board can be in data interaction with other board cards such as a master control switch card, an adjacent board card and the like in the system by a VPX dual redundancy data bus interface.
Description
Technical field
The invention belongs to digital signal processing technique field, more specifically say, relate to a kind of restructural based on Soc/bis-redundancy VPX3U signal transacting support plate.
Background technology
Take FPGA as the signal transacting support plate of core, as digital front-end igh-speed wire-rod production line module, be widely used in airborne/carrier-borne information load system, observing and controlling/field such as communication/navigator, signal testing analytical instrument.Traditional FPGA signal transacting support plate, usually only for simple function design, only focuses on the lifting of single performance, cannot dynamic configuration circuit function according to the actual requirements, and dirigibility, Universal and scalability can be poor.
VPX is the senior embedded platform bus standard of the next generation in order to meet high reliability under rugged surroundings, high bandwidth requirement organized to set up by VITA, have that transmission bandwidth is high, high, the interconnect architecture of the transmission fiduciary level feature such as configurable flexibly, be more and more used in as in the embedded signal processing system under particular job conditions such as Aero-Space.Define three kinds of high-speed serial bus such as SRIO (SerialRapidIO), PCIe (PCIExpress), 10GbEthernet in VPX bus, meet the high-speed data communication requirement of different application.But, current majority is all only provided with one group based on the external high speed data bus of the signal transacting support plate identical function of VPX bus, do not consider the problem of high speed data bus redundancy backup, cause its functional reliability under extreme environment condition to be difficult to ensure.
The developing direction of following embedded real time signal processing platform, not only requires to possess high-performance, high flexible, high reliability, extendible feature, has strict volume, weight and power consumption constraints simultaneously to signal processing platform.Therefore, with FPGA be the signal transacting support plate of core just progressively to the evolution of integrated flexible reconstruction structure, its comprehensive method is progressively developed to " structure composition " by " function synthesized ".Requirement can according to different mission requirements, and Configuration Online software/hardware order and parameter, realize the switching at runtime of multi-signal processing capacity.Meanwhile, also should possess the data transmission and processing ability of high reliability, big data quantity, multi tate, guarantee the security of data communication, promptness and reliability.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, a kind of restructural based on Soc/bis-redundancy VPX3U signal transacting support plate is provided, under the system architecture of " FMC+FPGA+Soc+VPX ", realize support plate logic function on-line reorganization and the two redundancy of VPX high speed data bus interface, effectively promote the dirigibility of support plate, versatility and reliability.
For achieving the above object, a kind of restructural based on Soc of the present invention/bis-redundancy VPX3U signal transacting support plate, is characterized in that, comprising:
One VPX connector, comprises universal plane interface, datum plane interface, control plane interface, expansion plane interface and User Defined interface;
Wherein, datum plane interface provides 2 groups of SRIOx4 high speed data bus interfaces and 2 groups of PCIex1 high speed data bus interfaces; Control plane interface provides 2 groups of 1GEx1 high speed data bus interfaces; Expand plane interface and 2 groups of SRIOx4 or 2 groups of PCIex4 high speed data bus interfaces are provided; Universal plane interface provides input power, reference clock and reset signal for support plate; User Defined interface provides 24 pairs of differential signal line interfaces and 8 single-ended signal line interfaces;
One PHY chip, input end is connected with group 1GEx1 high speed data bus interface of 2 in VPX control plane, and output terminal is connected with Soc controller; PHY chip receives main control switchboard by the control command of 1GEx1 high speed data bus interface input or configuration file, and is RGMII form by the order that receives or file transform, exports in Soc controller;
One Soc controller, based on " ARM core+FPGA " structure, is namely integrated with arm processor subsystem and programmable logic cells on a single chip; Soc controller PS end is connected with PHY chip, a DDR3 storer, and PL end is connected with the configuration interface of reconfigurable FPGA;
Described Soc controller is as FPGA reconfigurable controller, under VPX control plane 1GEx1 signal function, Soc controller receives file or data from PHY chip output terminal, and be stored in a DDR3 and carry out buffer memory, after receiving, file or data are read from a DDR3, according to different task demand, the logic function of online dynamic-configuration FPGA and parameter, by the time division multiplex to FPGA internal logic resource, realize the switching at runtime of multi-signal processing capacity;
Described Soc controller, also as plate level manager, implements power module management, clock module management and working state monitoring to signal transacting support plate;
One reconfigurable FPGA chip, be connected with FMC connector, Soc controller, the 2nd DDR3 large capacity data memory respectively, and with 2 groups of SRIOx4 in VPX datum plane interface and 2 groups of PCIex1 high speed data bus interfaces, expand 2 groups of SRIOx4 or PCIeX4 high speed data bus interfaces in plane interface and User Defined interface is connected;
Described reconfigurable FPGA chip is its main operational processing apparatus of signal transacting support plate, according to the program that Soc controller loads, High speed real-time signal processing is carried out to the external signal inputted through FMC connector, result after process is stored in the 2nd DDR3 storer, or undertaken alternately by main control switchboard and adjacent slot board in two redundant high-speed data bus of providing in VPX connector and system, can also by VPX User Defined interface and system peripheral standby carry out mutual;
One FMC connector, adopts high number of pins (HPC) standard, can carry the FMC subcard of difference in functionality, realizes collection and the reception of variety classes external signal; Adopt LA/HA/HB data line and DPx10 high speed data lines and fpga chip interconnected, the data realized between FMC subcard and support plate are transmitted.
Goal of the invention of the present invention is achieved in that
The present invention is based on the restructural/bis-redundancy VPX3U signal transacting support plate of Soc, plate carries Soc controller under VPX control plane 1GEx1 signal function, control command dynamic load and logic function on-line reorganization are carried out to high-performance reconfigurable FPGA, and completes plate level power supply, Clock management and status monitoring; Reconfigurable FPGA chip is undertaken alternately, realizing multi-functional Real-time digital signal processing according to loading procedure by standard FMC interface and front end receiver signal.Meanwhile, the two redundancy data bus interface of design in VPX connector, signal transacting support plate can carry out data interaction by other boards in the two redundancy data bus interface of VPX and the system such as main control switchboard, adjacent board.
Meanwhile, the restructural/bis-redundancy VPX3U signal transacting support plate that the present invention is based on Soc also has following beneficial effect:
(1), signal transacting support plate can in system main control switchboard and Soc controller management under realize control command dynamic load and logic function on-line reorganization.Soc controller is under VPX control plane 1GEx1 signal function, according to different task demand, the logic function of online dynamic-configuration FPGA and parameter, by the time division multiplex to FPGA internal logic resource, realize the switching at runtime of multi-signal processing capacity, while optimization system performance, effectively improve dirigibility and the versatility of support plate.
(2), according to VPX agreement, design in VPX connector and have employed two redundancy data bus interface, achieve the Hot Spare of data transmission bus, that is: in VPX interface data plane, control plane and expansion plane, the high speed data bus of identical function all arranges two groups; Signal transacting support plate is subject to the Real-Time Monitoring of main control switchboard and Soc controller in system: when support plate normally runs, and two groups of high speed data buss of identical function work simultaneously, and equally loaded, effectively increases data throughout; When wherein one group of high speed data bus breaks down, rapidly on-line reorganization is targetedly implemented to signal transacting support plate, taken over and complete independently data transfer task by the high speed data bus of another group identical function, guarantee that support plate normally works, improve reliability and the security of support plate greatly.
Accompanying drawing explanation
Fig. 1 is the restructural/bis-redundancy VPX3U signal transacting support plate theory diagram that the present invention is based on Soc;
Fig. 2 is the interface diagram of VPX connector;
Fig. 3 is ZynqSoc chip internal structure figure;
Fig. 4 is FPGA control command dynamic load or logic function on-line reorganization theory diagram.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described, so that those skilled in the art understands the present invention better.Requiring particular attention is that, in the following description, when perhaps the detailed description of known function and design can desalinate main contents of the present invention, these are described in and will be left in the basket here.
Embodiment
For convenience of description, first the relevant speciality term occurred in embodiment is described:
FPGA (FieldProgrammableGateArray): field programmable gate array;
SRIO (SerialRapidIO): a kind of high-speed serial bus;
PCIe (PeripheralComponentInterconnectExpress): peripheral component interconnect bus;
1GE (1GbEthernet): gigabit Ethernet;
Soc (SystemOnChip): SOC (system on a chip);
PHY (PhysicalLayer): Physical layer;
ARM (AdvancedRISCMachine): advanced reduced instruction processor;
MAC (MediaAccessControl): media access control layer;
PS (ProcessingSystem): processor subsystem;
PL (ProgrammableLogic): FPGA (Field Programmable Gate Array);
AXI (AdvancedExtensibleInterface): a kind of bus on chip that ARM company proposes;
MIO (MultiuseInput/Output): multifunctional multiplexing I/O;
FMC (FPGAMezzanineCard): FPGA interlayer card;
HPC (HighPinCountConnector): high number of pins connector;
DDR3SDRAM (DoubleDataRate3SynchronousDynamicRandomAccessMemory): third generation Double Data Rate synchronous regime random access memory;
SerDes (Serializer-Deserializer): deserializer;
SGMII (SerialGigabitMediaIndependentInterface): serial gigabit Media Independent Interface;
RGMII (ReducedGigabitMediaIndependentInterface): simplify gigabit Media Independent Interface;
GPIO (GeneralPurposeInput/Output): universal input/output;
I2C (Inter-IntegratedCircuit): a kind of twin wire universal serial bus;
Fig. 1 is the restructural/bis-redundancy VPX3U signal transacting support plate theory diagram that the present invention is based on Soc.
In the present embodiment, as shown in Figure 1, a kind of restructural based on Soc of the present invention/bis-redundancy VPX3U signal transacting support plate, comprising: VPX connector, PHY chip, Soc controller, reconfigurable FPGA chip and FMC connector;
Wherein, as shown in Figure 2, VPX connector comprises universal plane interface, datum plane interface, control plane interface, expansion plane interface and User Defined interface; In the present embodiment, VPX attachment unit interface defines the SLT3-PAY-2F1F2U-14.2.1 in compatible VPX standard interface definition, SLT3-PAY-2F2U-14.2.3 and SLT3-PAY-2F4F2U-14.2.11 standard.
In the present embodiment, as shown in Figure 2, the universal plane of VPX connector provides 3.3V, 5V, 12V input power for support plate, and the system signal such as reference clock, reset signal; Datum plane provides 2 groups of SRIOx4 high speed bus interfaces and 2 groups of PCIex1 high speed bus interfaces; Control plane provides 2 groups of 1GEx1 high speed bus interfaces; Expand plane and 2 groups of SRIOx4 or 2 group PCIex4 high speed bus interface is provided; User Defined interface provides 24 pairs of differential signal line interfaces and 8 single-ended signal line interfaces;
In the present embodiment, design in VPX connector and have employed two redundancy data bus interface, achieve the Hot Spare of data transmission bus, that is: in VPX interface data plane, control plane and expansion plane, the high speed data bus of identical function all arranges two groups; When support plate normally runs, two groups of high speed data buss of identical function work simultaneously, and equally loaded, effectively increases data throughout; When wherein one group of high speed data bus breaks down, rapidly on-line reorganization is targetedly implemented to signal transacting support plate, taken over and complete independently data transfer task by the high speed data bus of another group identical function.
As shown in Figure 1, the input end of PHY chip is connected with group 1GEx1 high speed data bus interface of 2 in VPX control plane, and output terminal is connected with Soc controller; PHY chip receives main control switchboard by the control command of 1GEx1 high speed data bus interface input or configuration file, and is RGMII form by the order that receives or file transform, exports in Soc controller;
In the present embodiment, the BCM5482SA2IFB that PHY chip adopts Broadcom company to produce, it meets the requirement of 10/100/1000Mb ethernet communication protocol, supports that 2 SGMII/SerDes input interfaces and 2 RGMII interfaces are connected to MAC layer.
As shown in Figure 1, Soc controller PS end is connected with PHY chip, a DDR3 storer, and PL end is connected with the configuration interface of reconfigurable FPGA; Soc controller receives file or data from PHY chip output terminal, and be stored in a DDR3 and carry out buffer memory, after receiving, file or data are read from a DDR3, according to different task demand, the logic function of online dynamic-configuration FPGA and parameter, by the time division multiplex to FPGA internal logic resource, realize the switching at runtime of multi-signal processing capacity; Soc controller, also as plate level manager, implements power module management, clock module management and working state monitoring etc. to support plate;
In the present embodiment, the Zynq-7000 series Soc system integrated chip that Soc controller adopts Xilinx company newly to release, concrete model is XC7Z030-2SBG485I.This series of products collection with
cortex
tM-A9MPCore processor is that the processor system (PS) of core and 28nm FPGA (Field Programmable Gate Array) (PL) are integrated.PS end exploitation control program, PL end is as expanding platform, and two ends are closely connected by AXI bus in sheet.PS end comprises ARM core, Universal peripheral interface and memory interface; Wherein, Universal peripheral interface comprises Gigabit Ethernet controller, USB controller, CAN controller etc., is connected with corresponding peripheral hardware by MIO pin; Memory interface comprises the external storage controllers such as DDR3 controller, and can control external memory storage carries out data read-write operation; PL end comprises the abundant logical resource such as a large amount of configurable GPIO, integrated PCIe core;
In the present embodiment, as shown in Figure 3, configuration 2 Gigabit Ethernet controller (GigE) in Universal peripheral interface are held, as gigabit Ethernet MAC layer interface at Zynq chip PS; Hold configuration 1 DDR3 controller in memory interface at PS, control the reading and writing data of outside DDR3 storer; Definition one configuration control module in GPIO is held, by the realization of configuration control module to the order loading of FPGA and logical reconstruction at PL; Hold a definition power control unit in GPIO at PL, control the electric sequence of each module of support plate; Also hold definition clock control cell at PL, by I2C bus, support plate clock module is managed;
As shown in Figure 1, reconfigurable FPGA chip is as its main operational processing apparatus of signal transacting support plate, be connected with FMC connector, Soc controller, the 2nd DDR3 large capacity data memory respectively, and with SRIOx4 with the PCIex1 high speed data bus interface in VPX datum plane, expand SRIOx4 or PCIeX4 high speed data bus interface in plane and User Defined interface is connected;
The program that reconfigurable FPGA chip loads according to Soc controller carries out real time signal processing to the external signal inputted through FMC connector, result after process is stored in the 2nd DDR3 large capacity data memory, or undertaken alternately by main control switchboard and adjacent slot board in two redundant high-speed data bus of providing in VPX connector and system, can also by VPX User Defined interface and system peripheral standby carry out mutual.
In the present embodiment, the model that reconfigurable FPGA chip adopts is XC7VX485T-2FFG1158I, this model FPGA has 485760 logical blocks, 350 HPI/O pins, 48 GTX high speed serialization transceivers, maximum transmitting-receiving speed can reach 12.5Gb/s, can call IP kernel resource and realize multiple high-speed serial bus agreement, as 1GE, SRIO, PCIe etc.
As shown in Figure 1, FMC connector adopts high number of pins (HPC) standard of 400 pins, with LA/HA/HB data line and DPx10 high speed data lines and fpga chip interconnected, the data realized between FMC subcard and support plate are transmitted.In the present embodiment, the signal transmission rate up to 10Gb/S supported by FMC connector, and potential total bandwidth reaches 40Gb/s.
Fig. 4 is FPGA control command dynamic load or logic function on-line reorganization theory diagram.Its workflow is:
When signal transacting support plate is in running order and when needing to reload control command or online updating configuration file, in system, control command or configuration file are sent to support plate by the gigabit Ethernet in VPX control plane by main control switchboard, support plate PHY chip (BCM5482SA2IFB) by SGMII port receives data, and is converted into RGMII form; Soc controller (XC7Z030-2SBG485I) PS holds configuration 2 Gigabit Ethernet controller as gigabit Ethernet MAC layer interface, and is connected with PHY chip RGMII output terminal by MIO pin; Under DDR3 controller management, the data received are stored in a DDR3 external memory storage carries out buffer memory, after data write, again data are read from a DDR3 storer, and the configuration control module be connected with FPGA is held by PL, under certain configuration mode sequential, control command is implemented to FPGA (XC7VX485T-2FFG1158I) and loads or logic function on-line reorganization.
Although be described the illustrative embodiment of the present invention above; so that those skilled in the art understand the present invention; but should be clear; the invention is not restricted to the scope of embodiment; to those skilled in the art; as long as various change to limit and in the spirit and scope of the present invention determined, these changes are apparent, and all innovation and creation utilizing the present invention to conceive are all at the row of protection in appended claim.
Claims (3)
1., based on restructural/bis-redundancy VPX3U signal transacting support plate of Soc, it is characterized in that, comprising:
One VPX connector, comprises universal plane interface, datum plane interface, control plane interface, expansion plane interface and User Defined interface;
Wherein, datum plane interface provides 2 groups of SRIOx4 high speed data bus interfaces and 2 groups of PCIex1 high speed data bus interfaces; Control plane interface provides 2 groups of 1GEx1 high speed data bus interfaces; Expand plane interface and 2 groups of SRIOx4 or 2 groups of PCIex4 high speed data bus interfaces are provided; Universal plane interface provides input power, reference clock and reset signal for support plate; 24 pairs of differential signal line interfaces and 8 single-ended signal line interfaces are provided with User Defined interface;
One PHY chip, input end is connected with group 1GEx1 high speed data bus interface of 2 in VPX control plane, and output terminal is connected with Soc controller; PHY chip receives main control switchboard by the control command of 1GEx1 high speed data bus interface input or configuration file, and is RGMII form by the order that receives or file transform, exports in Soc controller;
One Soc controller, based on " ARM core+FPGA " structure, is namely integrated with arm processor subsystem and programmable logic cells on a single chip; Soc controller PS end is connected with PHY chip, a DDR3 storer, and PL end is connected with the configuration interface of reconfigurable FPGA;
Described Soc controller is as FPGA reconfigurable controller, under VPX control plane 1GEx1 signal function, Soc controller receives file or data from PHY chip output terminal, and be stored in a DDR3 and carry out buffer memory, after receiving, file or data are read from a DDR3, according to different task demand, the logic function of online dynamic-configuration FPGA and parameter, by the time division multiplex to FPGA internal logic resource, realize the switching at runtime of multi-signal processing capacity;
Described Soc controller, also as plate level manager, implements power module management, clock module management and working state monitoring to support plate;
One restructural PGA chip, be connected with FMC connector, Soc controller, the 2nd DDR3 large capacity data memory respectively, and with 2 groups of SRIOx4 in VPX datum plane interface and 2 groups of PCIex1 high speed data bus interfaces, expand 2 groups of SRIOx4 with PCIeX4 high speed data bus interfaces in plane interface and User Defined interface is connected.
Described reconfigurable FPGA chip is its main operational processing apparatus of support plate, according to the program that Soc controller loads, High speed real-time signal processing is carried out to the external signal inputted through FMC connector, result after process is stored in the 2nd DDR3 storer, or undertaken alternately by main control switchboard and adjacent slot board in two redundant high-speed data bus of providing in VPX connector and system, can also by VPX User Defined interface and system peripheral standby carry out mutual;
One FMC connector, adopts high number of pins (HPC) standard, can carry the FMC subcard of difference in functionality, realizes collection and the reception of variety classes external signal; Adopt LA/HA/HB data line and DPx10 high speed data lines and fpga chip interconnected, the data realized between FMC subcard and support plate are transmitted.
2. the restructural based on Soc according to claim 1/bis-redundancy VPX3U signal transacting support plate, it is characterized in that, described signal transacting support plate can realize control command dynamic load and logic function on-line reorganization under the management of main control switchboard and Soc controller;
Its specific implementation process is: when signal transacting support plate is in running order and when needing to reload control command or online updating configuration file, in system, control command or configuration file are sent to support plate by the gigabit Ethernet in VPX control plane by main control switchboard, signal transacting support plate PHY chip by SGMII port receives data, and converts data to RGMII form; Soc controller PS holds configuration 2 Gigabit Ethernet controller as gigabit Ethernet MAC layer interface, and is connected with PHY chip RGMII output terminal by MIO pin; Under DDR3 controller management, the data that Soc controller receives are stored in a DDR3 external memory storage carries out buffer memory, after data write, again data are read from a DDR3 storer, and by configuration control module that PL holds, under corresponding configuration mode sequential, control command is implemented to signal transacting support plate and loads or logic function on-line reorganization.
3. the restructural based on Soc according to claim 1/bis-redundancy VPX3U signal transacting support plate, is characterized in that, described VPX connector adopts two redundancy data bus interface, achieves the Hot Spare of data transmission bus;
In the datum plane of VPX connector, control plane and expansion plane interface, the high speed data bus of identical function all arranges two groups; Signal transacting support plate is subject to the Real-Time Monitoring of main control switchboard and Soc controller in system: when signal support plate normally runs, and two groups of high speed data buss of identical function work simultaneously, and equally loaded, effectively increases data throughout; When wherein one group of high speed data bus breaks down, rapidly on-line reorganization is targetedly implemented to FPGA, taken over and complete independently data transfer task by the high speed data bus of another group identical function.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510675988.6A CN105335327B (en) | 2015-10-13 | 2015-10-13 | Restructural based on Soc/dual redundant VPX3U signal transacting support plates |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510675988.6A CN105335327B (en) | 2015-10-13 | 2015-10-13 | Restructural based on Soc/dual redundant VPX3U signal transacting support plates |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105335327A true CN105335327A (en) | 2016-02-17 |
| CN105335327B CN105335327B (en) | 2017-11-21 |
Family
ID=55285873
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510675988.6A Expired - Fee Related CN105335327B (en) | 2015-10-13 | 2015-10-13 | Restructural based on Soc/dual redundant VPX3U signal transacting support plates |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105335327B (en) |
Cited By (33)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106094625A (en) * | 2016-06-27 | 2016-11-09 | 上海波汇科技股份有限公司 | A kind of collecting transmitter based on SOC |
| CN106452668A (en) * | 2016-08-31 | 2017-02-22 | 许继集团有限公司 | IED double-channel data transmission and double-logic verification system and method based on FPGA |
| CN106909525A (en) * | 2017-01-13 | 2017-06-30 | 电子科技大学 | A kind of control Switching Module based on VPX buses |
| CN107015212A (en) * | 2017-06-13 | 2017-08-04 | 中国电子科技集团公司第三十八研究所 | Universal interface board of the radar wave control based on VPX buses with monitoring platform of testing oneself |
| CN107196695A (en) * | 2017-04-07 | 2017-09-22 | 西安电子科技大学 | Inter-satellite Links test system based on Zynq |
| CN107264572A (en) * | 2017-06-23 | 2017-10-20 | 成都运达科技股份有限公司 | A kind of contactless logic control system for possessing hot redundant ability |
| CN107451481A (en) * | 2017-07-31 | 2017-12-08 | 山东超越数控电子有限公司 | The high-speed storage device and method of a kind of discretionary security |
| CN107463474A (en) * | 2017-09-22 | 2017-12-12 | 成都旋极历通信息技术有限公司 | A kind of high-speed reconfigurable test platform |
| CN107491404A (en) * | 2017-07-17 | 2017-12-19 | 成都普诺科技有限公司 | A kind of signal acquisition and playback system |
| CN107566524A (en) * | 2017-10-11 | 2018-01-09 | 中船重工（武汉）凌久电子有限责任公司 | A kind of remote loading management system and remote loading management method based on Ethernet |
| CN107992380A (en) * | 2017-11-28 | 2018-05-04 | 北京东土科技股份有限公司 | A kind of computer system, backup management method and computer-readable recording medium |
| CN108021529A (en) * | 2016-10-31 | 2018-05-11 | 中国科学院沈阳自动化研究所 | A kind of hardware configurable controller device for autonomous submersible |
| CN108256150A (en) * | 2017-12-15 | 2018-07-06 | 中国航空工业集团公司西安飞行自动控制研究所 | A kind of method realized a variety of buses and replaced with position |
| CN108255085A (en) * | 2016-12-28 | 2018-07-06 | 比亚迪股份有限公司 | Controller and rail vehicle based on system on chip |
| CN108303688A (en) * | 2018-04-27 | 2018-07-20 | 北京东远润兴科技有限公司 | Reconfiguration system, method and the radar system of Radar Signal Processing |
| CN108667753A (en) * | 2018-05-03 | 2018-10-16 | 济南浪潮高新科技投资发展有限公司 | A kind of exchange management method and device with redundancy feature |
| CN109144927A (en) * | 2018-08-22 | 2019-01-04 | 深圳忆联信息***有限公司 | A kind of more FPGA interconnect devices and method |
| CN109815186A (en) * | 2018-12-18 | 2019-05-28 | 北京航天晨信科技有限责任公司 | Dual redundant communication equipment and method |
| CN109814552A (en) * | 2018-12-28 | 2019-05-28 | 百度在线网络技术（北京）有限公司 | Vehicular control unit, the Vehicular automatic driving method and device based on FPGA |
| CN109889748A (en) * | 2019-01-29 | 2019-06-14 | 中国航空无线电电子研究所 | Restructural Avionics Databus |
| CN110398921A (en) * | 2019-07-24 | 2019-11-01 | 理工雷科电子(西安)有限公司 | A kind of multitask dynamic restructuring processing system and method based on FPGA control |
| CN110852931A (en) * | 2019-11-18 | 2020-02-28 | 天津津航计算技术研究所 | High-performance CPU blade device suitable for VPX framework |
| CN111555800A (en) * | 2020-05-15 | 2020-08-18 | 北京光润通科技发展有限公司 | Gigabit dual-optical-port server adapter |
| CN111857012A (en) * | 2020-08-04 | 2020-10-30 | 重庆航天工业有限公司 | Multi-path high-performance communication system based on OpenVpx standard |
| CN112230955A (en) * | 2020-10-14 | 2021-01-15 | 西安微电子技术研究所 | Computer FPGA reconstruction system based on dual-core ARM SoC and operation method |
| CN112235525A (en) * | 2020-09-15 | 2021-01-15 | 中国科学院微电子研究所 | ZYNQ-based GigE interface camera target identification method and system |
| CN112285530A (en) * | 2020-09-28 | 2021-01-29 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Universal testing device for VPX high-speed signal board |
| CN112306933A (en) * | 2019-07-15 | 2021-02-02 | 栾东海 | Dual-bus control panel card based on PCI and PXIE |
| CN112685342A (en) * | 2020-12-30 | 2021-04-20 | 湖南博匠信息科技有限公司 | VPX storage control module with pluggable storage disk |
| CN112711560A (en) * | 2021-02-10 | 2021-04-27 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Reconstruction method for single-point connection RapidIO bus of ZYNQ chip |
| CN115189817A (en) * | 2022-05-26 | 2022-10-14 | 华中光电技术研究所（中国船舶重工集团公司第七一七研究所） | Dual-redundancy network communication circuit |
| CN117332746A (en) * | 2023-12-01 | 2024-01-02 | 中国海洋大学三亚海洋研究院 | Signal processing board card design method considering normal low speed and short-time high speed |
| US12022237B2 (en) | 2018-12-28 | 2024-06-25 | Apollo Intelligent Driving Technology (Beijing) Co., Ltd. | Vehicle-mounted control unit, and method and apparatus for FPGA based automatic driving of vehicle |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7212961B2 (en) * | 2002-08-30 | 2007-05-01 | Lsi Logic Corporation | Interface for rapid prototyping system |
| CN203561933U (en) * | 2013-11-29 | 2014-04-23 | 北京华科博创科技有限公司 | FMC structure 3U universal carrier board based on VPX bus |
| CN103777716A (en) * | 2013-11-29 | 2014-05-07 | 北京华科博创科技有限公司 | 3U general substrate based on VPX bus and for FMC structures |
| CN104331282A (en) * | 2014-10-28 | 2015-02-04 | 电子科技大学 | Reconfigurable comprehensive development and test system of wireless product |
| CN204595692U (en) * | 2015-04-24 | 2015-08-26 | 无锡市同芯恒通科技有限公司 | Based on the VPX computer motherboard of Shen prestige 410 processor and Shen Wei nest plate |
-
2015
- 2015-10-13 CN CN201510675988.6A patent/CN105335327B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7212961B2 (en) * | 2002-08-30 | 2007-05-01 | Lsi Logic Corporation | Interface for rapid prototyping system |
| CN203561933U (en) * | 2013-11-29 | 2014-04-23 | 北京华科博创科技有限公司 | FMC structure 3U universal carrier board based on VPX bus |
| CN103777716A (en) * | 2013-11-29 | 2014-05-07 | 北京华科博创科技有限公司 | 3U general substrate based on VPX bus and for FMC structures |
| CN104331282A (en) * | 2014-10-28 | 2015-02-04 | 电子科技大学 | Reconfigurable comprehensive development and test system of wireless product |
| CN204595692U (en) * | 2015-04-24 | 2015-08-26 | 无锡市同芯恒通科技有限公司 | Based on the VPX computer motherboard of Shen prestige 410 processor and Shen Wei nest plate |
Non-Patent Citations (1)
| Title |
|---|
| 吉玉洁等: "VPX总线标准研究及其在无人机中的应用展望", 《计算机测量与控制》 * |
Cited By (47)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106094625B (en) * | 2016-06-27 | 2018-09-25 | 上海波汇科技股份有限公司 | A kind of collecting transmitter based on SOC |
| CN106094625A (en) * | 2016-06-27 | 2016-11-09 | 上海波汇科技股份有限公司 | A kind of collecting transmitter based on SOC |
| CN106452668A (en) * | 2016-08-31 | 2017-02-22 | 许继集团有限公司 | IED double-channel data transmission and double-logic verification system and method based on FPGA |
| CN106452668B (en) * | 2016-08-31 | 2020-08-11 | 许继集团有限公司 | FPGA-based IED dual-channel data transmission and dual-logic verification system and method |
| CN108021529A (en) * | 2016-10-31 | 2018-05-11 | 中国科学院沈阳自动化研究所 | A kind of hardware configurable controller device for autonomous submersible |
| CN108255085A (en) * | 2016-12-28 | 2018-07-06 | 比亚迪股份有限公司 | Controller and rail vehicle based on system on chip |
| CN108255085B (en) * | 2016-12-28 | 2021-09-03 | 比亚迪股份有限公司 | Controller based on system on chip and rail vehicle |
| CN106909525A (en) * | 2017-01-13 | 2017-06-30 | 电子科技大学 | A kind of control Switching Module based on VPX buses |
| CN106909525B (en) * | 2017-01-13 | 2019-07-12 | 电子科技大学 | A kind of control Switching Module based on VPX bus |
| CN107196695A (en) * | 2017-04-07 | 2017-09-22 | 西安电子科技大学 | Inter-satellite Links test system based on Zynq |
| CN107015212A (en) * | 2017-06-13 | 2017-08-04 | 中国电子科技集团公司第三十八研究所 | Universal interface board of the radar wave control based on VPX buses with monitoring platform of testing oneself |
| CN107015212B (en) * | 2017-06-13 | 2019-11-26 | 中国电子科技集团公司第三十八研究所 | The Universal interface board of radar wave control and monitoring based on VPX bus from survey platform |
| CN107264572A (en) * | 2017-06-23 | 2017-10-20 | 成都运达科技股份有限公司 | A kind of contactless logic control system for possessing hot redundant ability |
| CN107491404A (en) * | 2017-07-17 | 2017-12-19 | 成都普诺科技有限公司 | A kind of signal acquisition and playback system |
| CN107451481A (en) * | 2017-07-31 | 2017-12-08 | 山东超越数控电子有限公司 | The high-speed storage device and method of a kind of discretionary security |
| CN107463474A (en) * | 2017-09-22 | 2017-12-12 | 成都旋极历通信息技术有限公司 | A kind of high-speed reconfigurable test platform |
| CN107566524A (en) * | 2017-10-11 | 2018-01-09 | 中船重工（武汉）凌久电子有限责任公司 | A kind of remote loading management system and remote loading management method based on Ethernet |
| CN107992380A (en) * | 2017-11-28 | 2018-05-04 | 北京东土科技股份有限公司 | A kind of computer system, backup management method and computer-readable recording medium |
| CN108256150A (en) * | 2017-12-15 | 2018-07-06 | 中国航空工业集团公司西安飞行自动控制研究所 | A kind of method realized a variety of buses and replaced with position |
| CN108256150B (en) * | 2017-12-15 | 2021-09-14 | 中国航空工业集团公司西安飞行自动控制研究所 | Method for realizing parity replacement of multiple buses |
| CN108303688A (en) * | 2018-04-27 | 2018-07-20 | 北京东远润兴科技有限公司 | Reconfiguration system, method and the radar system of Radar Signal Processing |
| CN108303688B (en) * | 2018-04-27 | 2022-02-11 | 北京东远润兴科技有限公司 | Reconstruction system and method for radar signal processing and radar system |
| CN108667753A (en) * | 2018-05-03 | 2018-10-16 | 济南浪潮高新科技投资发展有限公司 | A kind of exchange management method and device with redundancy feature |
| CN109144927A (en) * | 2018-08-22 | 2019-01-04 | 深圳忆联信息***有限公司 | A kind of more FPGA interconnect devices and method |
| CN109815186A (en) * | 2018-12-18 | 2019-05-28 | 北京航天晨信科技有限责任公司 | Dual redundant communication equipment and method |
| CN109814552A (en) * | 2018-12-28 | 2019-05-28 | 百度在线网络技术（北京）有限公司 | Vehicular control unit, the Vehicular automatic driving method and device based on FPGA |
| US12022237B2 (en) | 2018-12-28 | 2024-06-25 | Apollo Intelligent Driving Technology (Beijing) Co., Ltd. | Vehicle-mounted control unit, and method and apparatus for FPGA based automatic driving of vehicle |
| CN109814552B (en) * | 2018-12-28 | 2024-05-24 | 阿波罗智能技术(北京)有限公司 | Vehicle-mounted control unit, and automatic vehicle driving method and device based on FPGA |
| CN109889748A (en) * | 2019-01-29 | 2019-06-14 | 中国航空无线电电子研究所 | Restructural Avionics Databus |
| CN109889748B (en) * | 2019-01-29 | 2021-10-26 | 中国航空无线电电子研究所 | Reconfigurable airborne video recorder |
| CN112306933A (en) * | 2019-07-15 | 2021-02-02 | 栾东海 | Dual-bus control panel card based on PCI and PXIE |
| CN110398921A (en) * | 2019-07-24 | 2019-11-01 | 理工雷科电子(西安)有限公司 | A kind of multitask dynamic restructuring processing system and method based on FPGA control |
| CN110852931A (en) * | 2019-11-18 | 2020-02-28 | 天津津航计算技术研究所 | High-performance CPU blade device suitable for VPX framework |
| CN110852931B (en) * | 2019-11-18 | 2023-08-22 | 天津津航计算技术研究所 | High-performance CPU blade device suitable for VPX architecture |
| CN111555800A (en) * | 2020-05-15 | 2020-08-18 | 北京光润通科技发展有限公司 | Gigabit dual-optical-port server adapter |
| CN111857012A (en) * | 2020-08-04 | 2020-10-30 | 重庆航天工业有限公司 | Multi-path high-performance communication system based on OpenVpx standard |
| CN112235525A (en) * | 2020-09-15 | 2021-01-15 | 中国科学院微电子研究所 | ZYNQ-based GigE interface camera target identification method and system |
| CN112285530A (en) * | 2020-09-28 | 2021-01-29 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Universal testing device for VPX high-speed signal board |
| CN112230955A (en) * | 2020-10-14 | 2021-01-15 | 西安微电子技术研究所 | Computer FPGA reconstruction system based on dual-core ARM SoC and operation method |
| CN112230955B (en) * | 2020-10-14 | 2023-03-21 | 西安微电子技术研究所 | Computer FPGA reconstruction system based on dual-core ARM SoC and operation method |
| CN112685342A (en) * | 2020-12-30 | 2021-04-20 | 湖南博匠信息科技有限公司 | VPX storage control module with pluggable storage disk |
| CN112711560B (en) * | 2021-02-10 | 2023-05-26 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Reconstruction method for single-point connection of ZYNQ chip to rapidIO bus |
| CN112711560A (en) * | 2021-02-10 | 2021-04-27 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Reconstruction method for single-point connection RapidIO bus of ZYNQ chip |
| CN115189817A (en) * | 2022-05-26 | 2022-10-14 | 华中光电技术研究所（中国船舶重工集团公司第七一七研究所） | Dual-redundancy network communication circuit |
| CN115189817B (en) * | 2022-05-26 | 2024-03-22 | 华中光电技术研究所（中国船舶重工集团公司第七一七研究所） | Dual-redundancy network communication circuit |
| CN117332746A (en) * | 2023-12-01 | 2024-01-02 | 中国海洋大学三亚海洋研究院 | Signal processing board card design method considering normal low speed and short-time high speed |
| CN117332746B (en) * | 2023-12-01 | 2024-03-08 | 中国海洋大学三亚海洋研究院 | Signal processing board card design method considering normal low speed and short-time high speed |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105335327B (en) | 2017-11-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105335327A (en) | Reconfigurable/dual redundancy VPX3U signal processing carrier board based on Soc | |
| CN106909525B (en) | A kind of control Switching Module based on VPX bus | |
| CN106095334B (en) | A kind of high-speed data acquisition storage system based on FPGA | |
| CN105607694B (en) | Self-adapting changeable redundancy 3U signal processing backboards based on VPX buses | |
| CN105279133A (en) | VPX parallel DSP signal processing board card based on SoC online reconstruction | |
| CN101588175B (en) | FPGA array processing board | |
| MX2012005934A (en) | Multi-interface solid state disk (ssd), processing method and system thereof. | |
| CN104021107A (en) | Design method for system supporting non-volatile memory express peripheral component interface express solid state disc (NVMe PCIE SSD) | |
| CN103180817A (en) | Storage expansion apparatus and server | |
| CN116841932B (en) | Flexibly-connectable portable high-speed data access equipment and working method thereof | |
| CN105515673B (en) | A kind of optical-fibre channel node card | |
| CN210864564U (en) | High-performance main control board with 6U CPCI specification | |
| CN113489594A (en) | PCIE real-time network card based on FPGA module | |
| CN104765570A (en) | Storage unit based on PCI-E multi-master share | |
| CN204203964U (en) | The portable type ground testing apparatus that a kind of multichannel data stores | |
| CN204557308U (en) | A kind of high density Novel cutter flap-type server based on fusion architecture | |
| CN203858630U (en) | Pcie interface switching device | |
| CN105159605A (en) | Storage server architecture | |
| CN112636932B (en) | Dynamic adjustment method and system for equipment power consumption | |
| CN105511990B (en) | Device based on fusion architecture dual redundant degree storage control node framework | |
| CN103902229A (en) | Blade storage device | |
| CN203366045U (en) | A digital quantity input-output device based on a CAN bus | |
| CN105630400A (en) | High-speed massive data storage system | |
| CN109753459A (en) | A kind of high capacity data record device | |
| CN212484353U (en) | Radar signal processing device based on Open VPX |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20171121 Termination date: 20201013 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |