CN107942781A - The dual processors synchronous method and device of security system - Google Patents
The dual processors synchronous method and device of security system Download PDFInfo
- Publication number
- CN107942781A CN107942781A CN201711116457.9A CN201711116457A CN107942781A CN 107942781 A CN107942781 A CN 107942781A CN 201711116457 A CN201711116457 A CN 201711116457A CN 107942781 A CN107942781 A CN 107942781A
- Authority
- CN
- China
- Prior art keywords
- logic gates
- dual processors
- output signal
- signal
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/25—Pc structure of the system
- G05B2219/25257—Microcontroller
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- Hardware Redundancy (AREA)
Abstract
This application provides the dual processors synchronous method and device of a kind of security system, which includes the first logic gates and the second logic gates；The output terminal of first CPU is connected to the first input end of the first logic gates and the first input end of the second logic gates, the output terminal of 2nd CPU is connected to the second input terminal of the first logic gates and the second input terminal of the second logic gates, and the output terminal of the first logic gates and the second logic gates is connected respectively to the input terminal of the first CPU and the input terminal of the 2nd CPU；First logic gates and the second logic gates output signal to dual processors respectively in response to the synchronizing signal from dual processors, so that dual processors determine whether synchronization according to the output signal respectively from two logic gates.Dual processors synchronization directly is completed using hardware semaphore, the synchronous efficiency of dual processors is improved, simplifies programming, and synchronization delay is small, and reliability is high.
Description
Technical field
This application involves the dual processors synchronous method and device in train control system field, more particularly to a kind of security system.
Background technology
Dual processors need to synchronize to ensure the synchronization of dual processors task in the security system of dual processors synchronous working.Base
In the soft method of synchronization of conventional communication mode, its design difficulty is higher, dependent on the mathematical algorithm of complete set, while can take
Certain process resource, influences the operational efficiency of system.In addition, being limited to the influence such as transmission rate and delay, reliability is relatively low,
And the problems such as needing the security of handle data communication.
The content of the invention
In view of this, the embodiment of the present application provides the dual processors synchronous method and device of a kind of security system, to solve
The soft Synchronization Design of dual processors is complicated in the prior art.The technical problem that treatment effeciency cannot be guaranteed.
According to the one side of the embodiment of the present application, there is provided a kind of dual processors synchronous method of security system, including：It is defeated
Go out synchronizing signal to two logic gates；Described two logic gates are received in response to the synchronizing signal of the dual processors
Export signal；Judge whether the output signal respectively from described two logic gates is consistent, in response to described two logics
The output signal of gate circuit is consistent, continues to execute internal processes；Differ in response to the output signal of described two logic gates
Cause, pause performs internal processes.
Preferably, the logic gates is NOR gate circuit.
Preferably, judge whether unanimously include respectively from the output signal of described two logic gates：Judge difference
Whether the output signal from described two NOR gate circuits is all 0.
Preferably, output synchronizing signal to two logic gates include：Output signal to CPU is used as synchronous after negating
Signal, exports to two logic gates.
According to the another aspect of the embodiment of the present application, there is provided a kind of dual processors sychronisation of security system, its feature exist
In, including the first logic gates and the second logic gates；The output terminal of first CPU is connected to the of the first logic gates
The first input end of one input terminal and the second logic gates, the output terminal of the 2nd CPU are connected to the of the first logic gates
The output terminal of second input terminal of two input terminals and the second logic gates, the first logic gates and the second logic gates point
The input terminal of the first CPU and the input terminal of the 2nd CPU are not connected to；
First logic gates and the second logic gates export respectively in response to the synchronizing signal from dual processors
Signal is to the dual processors, so that the dual processors judge to be according to respectively from the output signal of described two logic gates
No synchronization.
Preferably, the logic gates is NOR gate circuit.
Preferably, judge that the dual processors are same when the output signal for described two NOR gate circuits that CPU is received all is 0
Step.
According to the another aspect of the embodiment of the present application, there is provided a kind of dual processors sychronisation of security system, including storage
Device and dual processors；The memory is used to store one or more computer instruction, wherein, the one or more computer quilt
The dual processors are performed to realize the dual processors synchronous method of above-mentioned security system respectively.
The beneficial effect of the embodiment of the present application includes：Dual processors synchronization directly is completed using hardware semaphore, improves dual processors
Synchronous efficiency, simplify programming, and synchronization delay is small, and reliability is high.
Brief description of the drawings
By the description to the embodiment of the present application referring to the drawings, the above-mentioned and other purpose of the application, feature and
Advantage will be apparent from, in the accompanying drawings：
Fig. 1 is the principle block architecture diagram of the dual processors sychronisation of security system provided by the embodiments of the present application；
Fig. 2 is a kind of configuration diagram of the dual processors sychronisation of security system provided by the embodiments of the present application；
Fig. 3 is the flow chart of the dual processors synchronous method of security system provided by the embodiments of the present application.
Fig. 4 is the built-in system configuration diagram of the dual processors sychronisation of security system provided by the embodiments of the present application.
Embodiment
The application is described below based on embodiment, but the application is not restricted to these embodiments.Under
Text is detailed to describe some specific detail sections in the detailed description of the application.Do not have for a person skilled in the art
The description of these detail sections can also understand the application completely.In order to avoid obscuring the essence of the application, known method, mistake
The not narration in detail of journey, flow, element and circuit.
In addition, it should be understood by one skilled in the art that provided herein attached drawing be provided to explanation purpose, and
What attached drawing was not necessarily drawn to scale.
Unless the context clearly requires otherwise, otherwise entire disclosure is similar with the " comprising " in claims, "comprising" etc.
Word should be construed to the implication included rather than exclusive or exhaustive implication；That is, it is containing for " including but not limited to "
Justice.
In the description of the present application, it is to be understood that term " first ", " second " etc. are only used for description purpose, without
It is understood that to indicate or implying relative importance.In addition, in the description of the present application, unless otherwise indicated, the implication of " multiple "
It is two or more.
The dual processors synchronous method and device of security system provided by the embodiments of the present application, it is directly complete using hardware semaphore
It is synchronous into dual processors, the synchronous efficiency of dual processors is improved, simplifies programming, and synchronization delay is small, and reliability is high.
Fig. 1 is the principle configuration diagram of the dual processors sychronisation of security system provided by the embodiments of the present application, including the
One logic gates 11, the second logic gates 12.The output terminal of CPU1 is connected to the first input of the first logic gates 11
End and the first input end of the second logic gates 12.The output terminal of CPU2 is connected to the second input of the first logic gates 11
End and the second input terminal of the second logic gates 12.The output terminal of first logic gates 11 and the second logic gates 12 point
The input terminal of CPU1 and the input terminal of CPU2 are not connected to.
CPU1 and CPU2 exports synchronizing signal to the first logic gates 11, the second logic gates 12 respectively, as two
The input of a logic gates.First logic gates 11, the second logic gates 12 export logic in response to input signal
Judge signal, and the input terminal exported respectively to the input terminal of CPU1 and CPU2.CPU1 and CPU2 is by judging the first logic gate
Whether circuit 11 is consistent with the output signal of the second logic gates 12 to judge whether dual processors are synchronous.
Consistent with the output signal of the second logic gates 12 in response to the first logic gates 11, CPU1 or CPU2 continue
Perform internal processes；It is consistent with the output signal of the second logic gates 12 in response to the first logic gates 11, CPU1 or
CPU2 pauses perform internal processes, and the signal until determining two logic gates continues to execute internal processes when consistent.
In one embodiment, synchronizing signal is used as after the output signal to CPU1 and CPU2 negates, exports to two and patrols
Gate circuit is collected, so that two CPU can make dynamic synchronization.CPU exports synchronizing signal using one of pin, if do not negated,
Synchronizing signal state remains unchanged, and outputting and inputting for XOR gate does not change in each program circulating period, and only
Once be synchronously it is effective, judgement below with for the first time, will will all lose the meaning of real-time synchronization.
In one embodiment, as shown in Fig. 2, the first logic gates 11, the second logic gates 12 are XOR gate
Circuit.CPU1 and CPU2 exports synchronizing signal to the first NOR gate circuit 11, the second NOR gate circuit 12 respectively, is patrolled as two
Collect the input of gate circuit.First NOR gate circuit 11, the second NOR gate circuit 12 export logic judgment in response to input signal
Signal, and the input terminal exported respectively to the input terminal of CPU1 and CPU2.CPU1 and CPU2 is by judging the first NOR gate circuit
11 with whether the output signal of the second NOR gate circuit 12 consistent judges whether dual processors synchronous.Signal output truth table is as follows：
| CPU1 is exported | CPU2 is exported | XOR gate 1 exports | XOR gate 2 exports |
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 1 |
| 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | 0 |
Whether CPU1 and CPU2 judges the output signal of XOR gate 1 and XOR gate 2 all for 0.In response to XOR gate 1 and exclusive or
The output signal of door 2 all continues to execute internal processes for 0, CPU1 or CPU2, and the output in response to XOR gate 1 and XOR gate 2 is believed
Number all perform internal processes for 1, CPU1 or CPU2 pauses, when the output signal of XOR gate 1 and XOR gate 2 is all 0 followed by
It is continuous to perform internal processes.
Based on described above, the embodiment of the present application additionally provides a kind of dual processors synchronous method of security system, is suitable for
CPU1 and CPU2, as shown in figure 3, this method comprises the following steps.
S201, output synchronizing signal to two logic gates.
S202, receives output signal of two logic gates in response to the synchronizing signal of dual processors.
S203, judges whether the output signal respectively from two logic gates is consistent.In response to described two logics
The output signal of gate circuit is consistent, performs step S204；It is inconsistent in response to the output signal of described two logic gates, hold
Row step S205.
S204, continues to execute internal processes；
S205, pause perform internal processes.
In one embodiment, logic gates is NOR gate circuit,
S203 judges whether unanimously further comprise respectively from the output signal of described two logic gates：
Judge the output signal respectively from described two NOR gate circuits whether all as 0.
In one embodiment, S201 exports synchronizing signal to two logic gates and further comprises：Output to CPU
Signal is used as synchronizing signal after negating, and exports to two logic gates.
Below with reference to Fig. 4, it illustrates suitable for for realizing the dual processors sychronisation of the security system of the embodiment of the present application
Computer system 600 structure diagram.The dual processors sychronisation of security system shown in Fig. 4 is only an example, no
The function and use scope for tackling the embodiment of the present application bring any restrictions.
As shown in figure 4, computer system 600 includes central processing unit (CPU) 601, it can be read-only according to being stored in
Program in memory (ROM) 602 or be loaded into program in random access storage device (RAM) 603 from storage part 608 and
Perform various appropriate actions and processing.In RAM603, also it is stored with system 600 and operates required various programs and data.
CPU601, ROM602 and RAM603 are connected with each other by bus 604.Input/output (I/O) interface 605 is also connected to bus
604。
I/O interfaces 605 are connected to lower component：Importation 606 including keyboard, mouse etc.；Penetrated including such as cathode
The output par, c 607 of spool (CRT), liquid crystal display (LCD) etc. and loudspeaker etc.；Storage part 608 including hard disk etc.；
And the communications portion 609 of the network interface card including LAN card, modem etc..Communications portion 609 via such as because
The network of spy's net performs communication process.Driver 610 is also according to needing to be connected to I/O interfaces 606.Detachable media 611, such as
Disk, CD, magneto-optic disk, semiconductor memory etc., are installed on driver 610, in order to read from it as needed
Computer program be mounted into as needed storage part 608.
Especially, in accordance with an embodiment of the present disclosure, it may be implemented as computer above with reference to the process of flow chart description
Software program.For example, embodiment of the disclosure includes a kind of computer program product, it includes being carried on computer-readable medium
On computer program, the computer program include be used for execution flow chart shown in method program code.In such reality
Apply in example, which can be downloaded and installed by communications portion 609 from network, and/or from detachable media
611 are mounted.When the computer program is performed by central processing unit (CPU) 601, perform what is limited in the present processes
Above-mentioned function.It should be noted that computer-readable medium described herein can be computer-readable signal media or
Computer-readable recording medium either the two any combination.Computer-readable recording medium for example can be --- but
Be not limited to --- electricity, magnetic, optical, electromagnetic, system, device or the device of infrared ray or semiconductor, or it is any more than combination.
The more specifically example of computer-readable recording medium can include but is not limited to：Electrical connection with one or more conducting wires,
Portable computer diskette, hard disk, random access storage device (RAM), read-only storage (ROM), erasable type may be programmed read-only deposit
Reservoir (EPROM or flash memory), optical fiber, portable compact disc read-only storage (CD-ROM), light storage device, magnetic memory
Part or above-mentioned any appropriate combination.In this application, computer-readable recording medium can any be included or store
The tangible medium of program, the program can be commanded the either device use or in connection of execution system, device.And
In the application, computer-readable signal media can include believing in a base band or as the data that a carrier wave part is propagated
Number, wherein carrying computer-readable program code.The data-signal of this propagation can take various forms, including but not
It is limited to electromagnetic signal, optical signal or above-mentioned any appropriate combination.Computer-readable signal media can also be computer
Any computer-readable medium beyond readable storage medium storing program for executing, the computer-readable medium can send, propagate or transmit use
In by instruction execution system, device either device use or program in connection.Included on computer-readable medium
Program code any appropriate medium can be used to transmit, include but not limited to：Wirelessly, electric wire, optical cable, RF etc., Huo Zheshang
Any appropriate combination stated.
Flow chart and block diagram in attached drawing, it is illustrated that according to the system of the various embodiments of the application, methods and procedures product
Architectural framework in the cards, function and operation.At this point, each square frame in flow chart or block diagram can represent one
A part for module, program segment or code, a part for the module, program segment or code include one or more be used in fact
The executable instruction of logic function as defined in existing.It should also be noted that marked at some as in the realization replaced in square frame
Function can also be with different from the order marked in attached drawing generation.For example, two square frames succeedingly represented can essentially
Perform substantially in parallel, they can also be performed in the opposite order sometimes, this is depending on involved function.It is also noted that
It is the combination of each square frame and block diagram in block diagram and/or flow chart and/or the square frame in flow chart, can uses and perform rule
The dedicated hardware based systems of fixed functions or operations is realized, or can use the combination of specialized hardware and programmed instruction
To realize.
As on the other hand, present invention also provides a kind of non-volatile memory medium, which can
To be non-volatile memory medium included in device described in above-described embodiment；Can also be individualism, without supplying
Non-volatile memory medium in CTC system equipment.Above-mentioned non-volatile memory medium is stored with one or more program, when
When one or more program stored is performed by an equipment so that the dual processors sychronisation of the security system：Output
Synchronizing signal is to two logic gates；The output that two logic gates are received in response to the synchronizing signal of the dual processors is believed
Number；Judge whether the output signal respectively from two logic gates is consistent, the output in response to two logic gates is believed
It is number consistent, continue to execute internal processes；Inconsistent in response to the output signal of two logic gates, pause performs internal journey
Sequence.
It will be understood by those skilled in the art that embodiments herein can be provided as method, apparatus (equipment), therefore, this
Application can be using the form of the embodiment in terms of complete hardware embodiment, complete software embodiment or combination software and hardware.
The foregoing is merely the preferred embodiment of the application, the application is not limited to, for those skilled in the art
For, the application can have various modifications and changes.All any modifications made within spirit herein and principle, be equal
Replace, improve etc., it should be included within the protection domain of the application.
Claims (8)
- A kind of 1. dual processors synchronous method of security system, it is characterised in that including：Synchronizing signal is exported to two logic gates；Receive output signal of described two logic gates in response to the synchronizing signal of the dual processors；Judge whether the output signal respectively from described two logic gates is consistent, in response to described two logic gates Output signal it is consistent, continue to execute internal processes；Inconsistent in response to the output signal of described two logic gates, pause performs internal processes.
- 2. according to the method described in claim 1, it is characterized in that, the logic gates is NOR gate circuit.
- 3. according to the method described in claim 2, it is characterized in that, judge the output respectively from described two logic gates Whether signal unanimously includes：Judge the output signal respectively from described two NOR gate circuits whether all as 0.
- 4. according to the method described in claim 1, it is characterized in that, output synchronizing signal to two logic gates include：Output signal to CPU is used as synchronizing signal after negating, and exports to two logic gates.
- 5. the dual processors sychronisation of a kind of security system, it is characterised in that including the first logic gates and the second logic gate electricity Road；The output terminal of first CPU is connected to the first input end of the first logic gates and the first input of the second logic gates End, the output terminal of the 2nd CPU are connected to the second input terminal of the first logic gates and the second input of the second logic gates End, the output terminal of the first logic gates and the second logic gates are connected respectively to the input terminal and the 2nd CPU of the first CPU Input terminal；First logic gates and the second logic gates export signal respectively in response to the synchronizing signal from dual processors To the dual processors, so that the dual processors are according to same to determine whether respectively from the output signal of described two logic gates Step.
- 6. device according to claim 5, it is characterised in that the logic gates is NOR gate circuit.
- 7. device according to claim 6, it is characterised in that the output for described two NOR gate circuits that CPU is received Signal judges that the dual processors are synchronous when being all 0.
- 8. the dual processors sychronisation of a kind of security system, it is characterised in that including memory and dual processors；The memory is used for One or more computer instruction is stored, wherein, one or more computer is performed to realize respectively by the dual processors：Synchronizing signal is exported to two logic gates；Receive output signal of described two logic gates in response to the synchronizing signal of the dual processors；Judge whether the output signal respectively from described two logic gates is consistent, in response to described two logic gates Output signal it is consistent, continue to execute internal processes；Inconsistent in response to the output signal of described two logic gates, pause performs internal processes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711116457.9A CN107942781B (en) | 2017-11-13 | 2017-11-13 | double-CPU synchronization method and device for security system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711116457.9A CN107942781B (en) | 2017-11-13 | 2017-11-13 | double-CPU synchronization method and device for security system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107942781A true CN107942781A (en) | 2018-04-20 |
| CN107942781B CN107942781B (en) | 2020-05-22 |
Family
ID=61934908
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711116457.9A Active CN107942781B (en) | 2017-11-13 | 2017-11-13 | double-CPU synchronization method and device for security system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107942781B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201604665U (en) * | 2009-11-02 | 2010-10-13 | 北京全路通信信号研究设计院 | Communication interface equipment of train control center |
| CN102437898A (en) * | 2011-12-15 | 2012-05-02 | 北京和利时***工程有限公司 | System and method for highspeed rail to generate transponder massage in real time |
| CN102857366A (en) * | 2012-06-08 | 2013-01-02 | 北京和利时***工程有限公司 | Trackside electronic device for transparent transmission of information of high-speed railway responder |
| JP2014109793A (en) * | 2012-11-30 | 2014-06-12 | Toyota Motor Corp | Moving body and control method therefor |
-
2017
- 2017-11-13 CN CN201711116457.9A patent/CN107942781B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201604665U (en) * | 2009-11-02 | 2010-10-13 | 北京全路通信信号研究设计院 | Communication interface equipment of train control center |
| CN102437898A (en) * | 2011-12-15 | 2012-05-02 | 北京和利时***工程有限公司 | System and method for highspeed rail to generate transponder massage in real time |
| CN102857366A (en) * | 2012-06-08 | 2013-01-02 | 北京和利时***工程有限公司 | Trackside electronic device for transparent transmission of information of high-speed railway responder |
| JP2014109793A (en) * | 2012-11-30 | 2014-06-12 | Toyota Motor Corp | Moving body and control method therefor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107942781B (en) | 2020-05-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107103903B (en) | Acoustic model training method and device based on artificial intelligence and storage medium | |
| US20190012575A1 (en) | Method, apparatus and system for updating deep learning model | |
| US9947001B2 (en) | System and method for using multiple payment accounts using a single payment device | |
| TWI515668B (en) | Methods and systems for detection in a state machine | |
| US9111081B2 (en) | Remote direct memory access authentication of a device | |
| CN107679700A (en) | Business flow processing method, apparatus and server | |
| TW201347409A (en) | Boolean logic in a state machine lattice | |
| US20170052884A1 (en) | Generic test automation for restful web services applications | |
| CN110046116B (en) | Tensor filling method, device, equipment and storage medium | |
| CN109992498A (en) | Generation method and system, the computer system of test case | |
| CN109889875A (en) | Communication means, device, terminal device and computer-readable medium | |
| CN113791605B (en) | Test method, device, equipment and storage medium | |
| CN113034118B (en) | Business auditing method, system, readable storage medium and computer program product | |
| CN112631884A (en) | Pressure measurement method and device based on data synchronization, computer equipment and storage medium | |
| CN109634934A (en) | Exchange method, apparatus, computer equipment and the storage medium of finance data | |
| CN108491890A (en) | Image method and device | |
| US20170220442A1 (en) | Replicating test case data into a cache with non-naturally aligned data boundaries | |
| CN109522060A (en) | The restoring method and terminal device of business scenario | |
| CN106550005A (en) | Method and apparatus for processing the medium type in REST software architectures | |
| CN107942781A (en) | The dual processors synchronous method and device of security system | |
| CN111582649A (en) | Risk assessment method and device based on user APP unique hot coding and electronic equipment | |
| CN107633219A (en) | Integrated optical character identifying method and system | |
| CN109522174A (en) | Control adb enabled method, apparatus, terminal and storage medium | |
| CN107291628A (en) | The method and apparatus of accessing data storage devices | |
| CN114237705A (en) | Verification method, verification device, electronic equipment and computer-readable storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |