CN1905175A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN1905175A
CN1905175A CNA2006101100178A CN200610110017A CN1905175A CN 1905175 A CN1905175 A CN 1905175A CN A2006101100178 A CNA2006101100178 A CN A2006101100178A CN 200610110017 A CN200610110017 A CN 200610110017A CN 1905175 A CN1905175 A CN 1905175A
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Prior art keywords
semiconductor substrate
substrate
insulating properties
semiconductor device
back side
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CNA2006101100178A
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CN100438004C (zh
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铃木彰
三坂荣一
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Abstract

本发明提供一种确保高的成品率且可靠性高的半导体装置及其制造方法。在半导体基板(1)的表面形成凹部(5)，在绝缘性基板(6)(玻璃等)上形成与该凹部(5)对应的凸部(7)。然后，使凹部(5)与凸部(7)嵌合，经由粘接层(8)而将半导体基板(1)与绝缘性基板(7)接合。对半导体基板(1)的背面进行背部研磨，露出凸部(7)，然后进行形成通孔(10)、形成贯通电极(14)、形成导电端子(18)以及切割等工序。此时，半导体基板(1)的表面及侧面被绝缘性基板(6)覆盖(保护)。另外，凸部(7)具有规定的宽度，切割在凸部(7)的中点附近进行。

Description

半导体装置及其制造方法
技术领域
本发明涉及加工性优良且可靠性高的半导体装置及其制造方法。
背景技术
近年来，作为三维安装技术，CSP(Chip Size Package：芯片尺寸封装)正受到注目。CSP是指具有与半导体芯片的外形尺寸大致相同尺寸的外形尺寸的小型封装。
以往，作为CSP的一种，公知有BGA(Ball Grid Array：球栅阵列封装)型的半导体装置。该BGA型的半导体装置将由焊锡等金属部件构成的球状的导电端子格子状地在封装的一主面上配列多个，与搭载于封装的另一面上的半导体芯片电连接。
并且，将该BGA型半导体装置组装在电子设备中时，通过将各导电端子安装在印刷衬底上的配线图案上，从而将半导体芯片和搭载于印刷衬底上的外部电路电连接。
并且，这样的BGA型电子装置与具有向侧部突出的引脚的SOP(SmallOutline Package：小轮廓封装)和QFP(Quad Flat Package：四方平板封装)等其他的CSP型半导体装置相比，具有可设置多个导电端子且可小型化的优点，故可作为例如搭载于携带电话上的数码相机的图像传感器芯片等而广泛使用。
图10是现有的BGA型半导体装置的概略结构，图10(A)是该BGA型半导体装置的表面侧的立体图。另外，图10(B)是该BGA型背面侧的立体图。
该BGA型半导体装置101在第一及第二玻璃基板102、103之间经由环氧树脂层105a、105b而密封有半导体芯片104。在第二玻璃基板103的一主面上、即BGA型半导体装置101的背面上格子状地配置有多个导电端子106。该导电端子106经由第二配线109与半导体芯片104连接。在多个第二配线109上连接有分别从半导体芯片104的内部引出的铝配线，将各导电端子106和半导体芯片104电连接。
参照图11详细说明该BGA型半导体装置101的剖面结构。图11表示沿划线DL分割成各个芯片的BGA型半导体装置101的剖面图。
在形成于半导体芯片104的表面上的绝缘层108上设有第一配线107。该半导体芯片104的表面通过环氧树脂等树脂层105a而与第一玻璃基板102连接。另外，该半导体芯片104的背面通过环氧树脂等树脂层105b与第二玻璃基板103粘接。
另外，第一配线107的一端与第二配线109连接。该第二配线109从第一配线107的一端在第二玻璃基板103的表面上延伸。并且，在第二玻璃基板103上延伸的第二配线109上形成有球状的导电端子106。另外，在第二配线109的表面上形成有由抗焊料剂等构成的保护膜110。
上述技术记载于以下的专利文献1中。
专利文献1：特许公表2002-512436号公报
专利文献2：特开2003-309221号公报
但是，在上述现有的BGA型半导体装置中，尤其是其芯片端112上的加工特别困难，故存在半导体装置的可靠性恶化的问题。具体地说，例如在芯片端112未被保护膜110充分覆盖的情况下，具有水、药液等腐蚀物质侵入配线(第一配线107、第二配线109)的问题。
另外，由于切割工序中划线的稍微偏斜、及此时产生的冲击而同时发生保护膜110剥离，配线(第二配线109)露出，或形成于内部的配线(第一配线107)、焊盘电极等元件损伤的问题。另外，为了防止该问题的产生，在将划线与芯片端的距离扩大的情况下，会减小每片晶片的芯片数量，且成本增加。
另外，根据温度变化，在半导体芯片104和支承基板(例如第一玻璃基板102)的接点上温度循环(膨胀系数的不同)而产生歪曲，由该部分产生机械的损伤，乃至侵入腐蚀物质。
这样，在以往的结构中，由于半导体装置上产生的各种应力、冲击、温度变化而产生破损或变形等损伤，具有可靠性变差的问题。另外，这样的问题在所谓的贯通型的半导体装置(参照专利文献2)中也同样地产生。
发明内容
因此，本发明在芯片尺寸封装型的半导体装置及其制造方法中谋求可靠性的大幅度提高。
本发明是鉴于上述课题而研发的，其主要特征如下。即，本发明的半导体装置包括：半导体基板；在所述半导体基板的表面形成的焊盘电极；从所述半导体基板的背面贯通并到达所述焊盘电极的通孔；形成于所述通孔之中并与所述焊盘电极电连接的贯通电极；形成于所述半导体基板的背面并与所述贯通电极电连接的导电端子，由绝缘性基板覆盖所述半导体基板的表面及侧面。
另外，本发明的半导体装置的制造方法，其具有如下特征。即，本发明的半导体装置的制造方法包括有如下的工序：准备表面形成有焊盘电极的半导体基板，从所述半导体基板表面向背面的方向形成规定的凹部；在绝缘性基板上形成与所述凹部对应的凸部；然后，经由粘接层将所述半导体基板与所述绝缘性基板接合；形成从所述半导体基板的背面到达所述焊盘电极的通孔；在所述通孔中形成与所述焊盘电极电连接的贯通电极；在所述半导体基板的背面形成与所述贯通电极电连接的导电端子。
另外，将半导体基板和绝缘性基板接合的工序也可以利用阳极接合法。由此，可精度良好地将凹部和凸部接合，其结果可提高半导体装置的可靠性。
另外，本发明的半导体装置的制造方法，包括如下的工序：从所述半导体基板的表面向背面的方向形成规定的凹部；在绝缘性基板上形成与所述凹部对应的凸部；然后，在含所述凹部的所述半导体基板上或含所述凸部的所述绝缘性基板上形成粘接层；使所述凹部及所述凸部嵌合而将所述半导体基板和所述绝缘性基板接合；沿所述凸部上设有的划线进行切割，将所述半导体基板切断分离成多个半导体芯片。并且，不限于形成有贯通电极的半导体装置，还可制造在各种各样的半导体装置中，在制造工序及使用状态中对于外部环境(腐蚀物质的侵入、应力、冲击等)的变化具有良好的耐久性和可靠性的半导体装置。
在本发明的半导体装置及其制造方法中，从制造工序中途阶段，由强度高的绝缘性基板(玻璃等)覆盖(保护)半导体基板的表面及侧面。由此，提高对热处理、蚀刻、切割等制造工序或使用状态的外部环境的变化(腐蚀物质的侵入、应力、冲击等)的耐久性和稳定性。并且，根据本发明，由于将半导体基板和绝缘性基板粘合之后的加工容易，可确保很高的成品率。
另外，在绝缘性基板的凸部进行切割时，主要对绝缘性基板(玻璃等)进行切割即可，不需要如以往的切割工序那样对半导体层进行切割，故其控制容易。另外，由于即使划线多少偏斜也保护绝缘性基板，故对成品率的影响小。
结果，可得到在确保高的成品率的同时可靠性高的芯片尺寸封装型半导体装置。
附图说明
图1是用于说明本发明的半导体装置及其制造方法的剖面图；
图2是用于说明本发明的半导体装置及其制造方法的剖面图；
图3是用于说明本发明的半导体装置及其制造方法的剖面图；
图4(A)、(B)是用于说明本发明的半导体装置及其制造方法的剖面图；
图5(A)、(B)是用于说明本发明的半导体装置及其制造方法的剖面图；
图6(A)、(B)是用于说明本发明的半导体装置及其制造方法的剖面图；
图7是用于说明本发明的半导体装置及其制造方法的平面图；
图8是用于说明本发明的半导体装置及其制造方法的平面图；
图9是用于说明本发明的半导体装置及其制造方法的平面图；
图10(A)、(B)是说明现有的半导体装置的立体图；
图11是说明现有的半导体装置的剖面图。
符号说明
1：半导体基板；2：第一绝缘膜；3：焊盘电极；4：钝化膜；5：(半导体基板)的凹部；6：绝缘性基板；7：(绝缘性基板的)凸部；8：粘接层；9：抗蚀剂层；10：通孔；11：第二绝缘膜；12：抗蚀剂层；13：阻挡金属层；14：贯通电极；15：配线层；16：抗蚀剂层；17：保护膜；18：导电端子；20：半导体装置；101：半导体装置；102：第一玻璃基板；103：第二玻璃基板；104：半导体芯片；105a、105b：树脂层；106：导电端子；107：第一配线；108：绝缘层；109：第二配线；110：保护膜；DL：划线。
具体实施方式
以下参照附图详细说明本发明的实施方式。图1～图8分别是按制造工序顺序所示的剖面图。另外，图9是从背面方向看本发明的半导体装置的平面图，图8是沿图9的X-X线的剖面图。另外，在半导体基板上适当形成有MOS晶体管，多个配线、将配线间连接的插塞等元件及由氧化硅膜构成的元件分离，但其图示省略。另外，由于通过晶片工序进行以下工序，故多个半导体装置20同时形成，而为了方便，说明形成有三个半导体装置的工序。
首先，如图1所示，在由硅(Si)等构成的半导体基板1的表面上将第一绝缘膜2(例如由热氧化法或CVD法等构成的氧化硅膜)形成为例如2μm的膜厚。然后，通过溅射法或镀敷法、其他成膜方法形成构成为焊盘电极3的铝(Al)或铜(Cu)等金属层，之后，使用未图示的掩模对该金属层进行蚀刻，在绝缘膜2上将焊盘电极3形成为例如1μm的膜厚。焊盘电极3为与半导体基板1上的未图示的电子器件连接的外部连接用电极。
然后，覆盖焊盘电极3，将钝化膜4(例如由等离子CVD法构成的氮化硅膜(SiN膜))形成为例如2μm的膜厚。之后，从半导体基板1的表面向背面的方向形成规定的凹部5。凹部5是与后述的绝缘性基板6粘合时必要的接合部位。该凹部5通过蚀刻或激光束照射等方法而形成。在此，凹部5的高度例如为200μm左右，宽度为40μm左右，但不限于此。通过以上的工序，进行形成有规定的凹部5的半导体基板1的形成。
另一方面，如图1所示，准备由玻璃、塑料、陶瓷、石英等构成的绝缘性基板6，形成与在半导体基板1上形成的凹部5对应的凸部7。凸部7是如上所述在与被构图了的半导体基板1粘合时必要的接合部位。该凸部7与凹部5同样，通过蚀刻或激光束照射等方法形成。通过以上的工序，形成形成有规定的凸部7的绝缘性基板6。
另外，在图面上，凹部5及凸部7为平直形状，但也可以形成为锥形。
其次，在含凸部7的侧壁的绝缘性基板6的表面(或者含凹部5的内壁的半导体1的表面)上使用旋涂法涂敷例如由环氧树脂构成的粘接剂。然后，如图2所示，经由该粘接剂(粘接层8)将半导体基板1的表面与绝缘性基板6接合。此时，凹部5和对应的凸部7嵌合。
另外，作为将半导体基板1和绝缘性基板6接合的方法，也可以使用阳极接合法(Anodic bonding)。此时，在半导体基板1与绝缘性基板6之间产生大的静电引力(粘接层8)，通过在界面化学接合，将二者接合。根据该方法，由于以固相进行接合，故可进行高精度的接合，并且仅在必要部分上进行加热，因此具有可变形小地进行接合等的优点。另外，也可以将粘接剂和阳极接合法并用。
然后，以粘接有该绝缘性基板6的状态，如图3所示，进行半导体基板1的背面蚀刻、所谓的背部研磨(BG)。该背部研磨一直进行到至少绝缘性基板6的凸部7从半导体基板1的背面露出，从而使得以后的工序容易，在制造可靠性高的半导体装置上是理想的。这是由于，本实施方式中没有在绝缘性基板6的凸部7上残留半导体基板1的必要性。另外，将半导体基板1减薄的同时，只要切割绝缘性基板6就能分离成一个个，切割也容易进行。因此，在本实施方式中，通过该背部研磨将凹部5消除。
另外，在以后的工序中，由于绝缘性基板6具有作为半导体基板1的强力的支承体的作用，故可谋求工序操作时的强度对策、污染对策。
然后，在半导体基板1的背面上有选择地形成抗蚀剂层9。有选择是指，在半导体基板1的背面中，仅在与焊盘电极3对应的位置上具有开口部而形成。之后，以该抗蚀剂层9为掩模，最好通过干式蚀刻法选择地蚀刻半导体基板1及第一绝缘膜2。作为干式蚀刻的蚀刻气体，可使用公知的CHF3等。通过该蚀刻，如图4(A)所示，焊盘电极3露出，形成从与该焊盘电极3对应处的半导体基板1的背面贯通至焊盘电极3的表面的通孔10。
去除抗蚀剂层9之后，如图4(B)所示，在含有通孔10内的半导体基板1的整个背面，将第二绝缘膜11(例如由等离子CVD法形成的氮化硅膜或氧化硅膜)形成为例如1μm的膜厚。
如图5(A)所示，在除通孔10之外的第二绝缘膜11上有选择地形成抗蚀剂层12。然后，以该抗蚀剂层12为掩膜，蚀刻去除通孔10底部的第二绝缘膜11(在残存有第一绝缘膜2的情况下也包括该第二绝缘膜)。该蚀刻例如为各向异性离子蚀刻为好，但也可以是其他的蚀刻。通过该蚀刻，如图5(B)所示，可使形成于半导体基板1背面上及通孔10的侧壁上的第二绝缘膜11残存，并同时将该底部的第二绝缘膜11去除而使焊盘电极3露出。之后，将抗蚀剂层12去除。另外，将图4(A)工序中的第一绝缘膜2的蚀刻去除工序省略，而在本工序的第二绝缘膜11的蚀刻去除工序中，将第一绝缘膜2及第二绝缘膜11一同蚀刻去除。
接着，如图6(A)所示，在含通孔10的半导体基板1的背面的第二绝缘膜11及焊盘电极3上形成阻挡金属层13。另外，在阻挡金属层13上形成未图示的籽晶层。在此，上述阻挡金属层13例如由钛钨层(TiW)层、氮化钛(TiN)或氮化钽(TaN)层等的金属构成。上述未图示的籽晶层是用于镀敷形成后述的贯通电极14及配线层15的电极，例如由铜(Cu)等金属构成。阻挡金属层13例如通过溅射法、CVD法、PVD法、无电解镀敷法及其他成膜方法形成。
然后，在含通孔10的阻挡金属层13及未图示的籽晶层上，例如通过无电解镀敷法形成由铜(Cu)构成的贯通电极14以及与该贯通电极14连续连接的配线层15。贯通电极14及配线层15经由阻挡金属层13以及未图示的籽晶层与在通孔10的底部露出的焊盘电极3电连接。另外，所述贯通电极14及配线层15也可以是由溅射法等形成铝(Al)的部件。
然后，如图6(B)所示，在半导体基板1的背面的配线层15上有选择地形成用于将配线层15构图成规定图案的抗蚀剂层16。该抗蚀剂层16与残存的配线层15(配线)的图案对应形成。
之后，以抗蚀剂层16为掩模，蚀刻去除不需要的配线层15部分以及未图示的籽晶层。接着，以配线层15为掩模，蚀刻去除阻挡金属层13。通过该蚀刻，将半导体基板1的背面的配线层15构图为规定的配线图案。然后去除抗蚀剂层16。
如图7所示，在半导体基板1背面上，将其覆盖，形成例如由抗焊料剂之类的抗蚀剂材料构成的保护膜17。在保护膜17中配线层15的规定位置(导电端子形成区域)设有开口部。并且，在由该开口部露出的配线层15上使用网印法形成例如由焊锡等金属构成的球状导电端子18。
通过以上的工序，分别完成由层积的各层构成的BGA型半导体装置20。并且，由于以上的工序通过晶片工序进行，故在一片晶片上同时形成多个半导体装置20。因此，通过沿多个半导体装置20的边界的划线DL进行切割，如图8所示，分离成一个个的半导体装置20。在此，划线DL设定在半导体装置20的边界、即绝缘性基板6的凸部7上。此时，绝缘性基板6缓和并保护向半导体装置20的冲击。因此以往成为问题的切割工序中引起的机械损伤(半导体装货子20的各层的剥离或断裂)减轻。
另外，使划线DL在凸部7的中点附近，保护半导体装置20不受切割工序引起的机械损伤，同时在提高成品率方面是理想的。
另外，在本实施方式的切割中只要主要将绝缘性基板6(例如玻璃)切割即可，由于不切割半导体层(半导体基板1)，故其控制容易。
图9是从背面方向看到的本实施方式的切割后的半导体装置20的平面图，图8是沿图9的X-X线的剖面图。另外，在图9中为了方便而省略了保护膜17的图示。
这样，在本发明的半导体装置20中，其表面及侧面被绝缘性基板6覆盖，背面被保护膜17覆盖。因此，在制造工序时以及使用状态中，对外部环境变化(腐蚀物质的侵入、应力、冲击等)的耐久性、可靠性比以往的半导体装置大幅度提高。
另外，在本实施方式中，对适用于具有球状的导电端子的BGA型的半导体装置的情况为例进行了说明，但本发明也可以适用于LGA(Land GridArray：面栅阵列)型的半导体装置中。

Claims (9)

1.一种半导体装置，其特征在于，包括：半导体基板；在所述半导体基板的表面形成的焊盘电极；从所述半导体基板的背面贯通并到达所述焊盘电极的通孔；形成于所述通孔之中并与所述焊盘电极电连接的贯通电极；形成于所述半导体基板的背面并与所述贯通电极电连接的导电端子，
由绝缘性基板覆盖所述半导体基板的表面及侧面。
2.如权利要求1所述的半导体装置，其特征在于，在所述绝缘性基板与所述半导体基板之间具有粘接层。
3.如权利要求2所述的半导体装置，其特征在于，所述粘接层由粘接剂构成。
4.如权利要求1～3中任一项所述的半导体装置，其特征在于，所述绝缘性基板是玻璃、塑料、陶瓷或石英中的任一个。
5.一种半导体装置的制造方法，其特征在于，包括如下的工序：
准备表面形成有焊盘电极的半导体基板，从所述半导体基板表面向背面的方向形成规定的凹部；
在绝缘性基板上形成与所述凹部对应的凸部；
然后，经由粘接层将所述半导体基板与所述绝缘性基板接合；
形成从所述半导体基板的背面到达所述焊盘电极的通孔；
在所述通孔中形成与所述焊盘电极电连接的贯通电极；
在所述半导体基板的背面形成与所述贯通电极电连接的导电端子。
6.如权利要求5所述的半导体装置的制造方法，其特征在于，经由粘接层将所述半导体基板和所述绝缘性基板接合的工序利用阳极接合法。
7.如权利要求5或6所述的半导体装置的制造方法，其特征在于，在形成所述导电端子的工序之后，沿所述凸部上设有的划线进行切割工序。
8.如权利要求5～7任一项所述的半导体装置的制造方法，其特征在于，在经由粘接层将所述半导体基板和所述绝缘性基板接合的工序之后，进行将所述半导体基板的背面平坦化，直至至少使所述绝缘性基板的凸部露出的工序。
9.一种半导体装置的制造方法，其特征在于，包括如下的工序：
从所述半导体基板的表面向背面的方向形成规定的凹部；
在绝缘性基板上形成与所述凹部对应的凸部；
然后，在含所述凹部的所述半导体基板上或含所述凸部的所述绝缘性基板上形成粘接层；
使所述凹部及所述凸部嵌合而将所述半导体基板和所述绝缘性基板接合；
沿所述凸部上设有的划线进行切割，将所述半导体基板切断分离成多个半导体芯片。
CNB2006101100178A 2005-07-28 2006-07-28 半导体装置及其制造方法 Expired - Fee Related CN100438004C (zh)

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