CN102969305B - 用于半导体结构的管芯对管芯间隙控制及其方法 - Google Patents

用于半导体结构的管芯对管芯间隙控制及其方法 Download PDF

Info

Publication number
CN102969305B
CN102969305B CN201210187476.1A CN201210187476A CN102969305B CN 102969305 B CN102969305 B CN 102969305B CN 201210187476 A CN201210187476 A CN 201210187476A CN 102969305 B CN102969305 B CN 102969305B
Authority
CN
China
Prior art keywords
tube core
substrate
distance
edge
tube
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201210187476.1A
Other languages
English (en)
Other versions
CN102969305A (zh
Inventor
林俊成
卢思维
施应庆
王英达
郭立中
李隆华
郑心圃
余振华
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN102969305A publication Critical patent/CN102969305A/zh
Application granted granted Critical
Publication of CN102969305B publication Critical patent/CN102969305B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/03452—Chemical vapour deposition [CVD], e.g. laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/05611—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05639—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05684—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

一个实施例是一种包括了衬底、第一管芯、以及第二管芯的结构。该衬底具有第一表面和与第一表面相对的第二表面。该衬底具有从第一表面向第二表面延伸的衬底通孔。第一管芯与衬底相接合，并且第一管芯与衬底的第一表面相连接。第二管芯与衬底相接合，并且第二管芯与衬底的第一表面相连接。第一管芯的第一边缘和第二管芯的第一边缘之间具有第一距离，并且该第一距离在与衬底的第一表面平行的方向上。第一距离等于或小于200微米。本发明还提供了一种用于半导体结构的管芯对管芯间隙控制及其方法。

Description

用于半导体结构的管芯对管芯间隙控制及其方法
技术领域
本发明涉及半导体领域，更具体地，本发明涉及一种用于半导体结构的管芯对管芯间隙控制及其方法。
背景技术
自从集成电路（IC）发展以来，由于各种电子封装（即，晶体管、二极管、电阻器、电容器等）的集成密度持续提高，半导体工业经历了持续的迅速发展。就绝大部分而言，集成密度的这些发展源于最小封装尺寸的再三减小，这使得在给定的面积中可以集成更多的部件。
实际上，这些集成度的提高基本上都是二维的（2D），使得集成封装所占用的面积基本上都位于半导体晶圆的表面上。密度的增大和集成电路面积的相应减小通常超过了将集成电路芯片直接接合在衬底上的能力。
利用附加维度的不同的封装技术已被用于实现各种目的。一种封装件是中介层上一个芯片或多个芯片。中介层已被用于将芯片的球接触区域再分配到更大的中介层面积中。另一种发展是在有源管芯上堆叠管芯。这也使得封装件能够包括多个芯片并且减少了封装的足迹（footprint）。
在处理过程中，这些封装件中的中介层或底部有源管芯大体上包括衬底通孔（TSV，也被称为“半导体通孔”或“硅通孔”），并且在将中介层或底部管芯从晶圆中单分（singulate）出来之前，通常要将其他管芯连接在中介层或底部有源管芯。在管芯连接步骤之后，经常进一步处理包括中介层或底部有源管芯的晶圆，该处理通常包括各种热工艺。在该热工艺过程中，底部填充的热膨胀系数（CTE）或收缩可能导致晶圆翘曲。该翘曲可能会对TSV或封装件的其他部件（诸如，底部填充材料或凸块）施加应力。该应力可能导致TSV中产生裂缝、在凸块中产生裂缝或底部填充材料的分层。
发明内容
根据本发明的一个方面，提供了一种结构，包括：衬底，具有第一表面和与所述第一表面相对的第二表面，所述衬底具有从所述第一表面向所述第二表面延伸的衬底通孔；第一管芯，与所述衬底相接合，所述第一管芯与所述衬底的所述第一表面相连接；以及第二管芯，与所述衬底相接合，所述第二管芯与所述衬底的所述第一表面相连接，所述第一管芯的第一边缘和所述第二管芯的第一边缘之间具有第一距离，所述第一距离在与所述衬底的所述第一表面平行的方向上，所述第一距离等于或小于200微米。
在该结构中，进一步包括：第三管芯，与所述衬底相接合，所述第三管芯与所述衬底的所述第一表面相连接，所述第二管芯的第二边缘和所述第三管芯的第一边缘之间具有第二距离，所述第二距离在与所述衬底的所述第一表面平行的方向上，所述第一距离和所述第二距离的总和等于或小于250微米。
在该结构中，所述第一距离和所述第二距离均等于或小于125微米。
在该结构中，进一步包括：第四管芯，与所述衬底相接合，所述第四管芯与所述衬底的第一表面相连接，所述第三管芯的第二边缘和所述第四管芯的第一边缘之间具有第三距离，所述第三距离在与所述衬底的所述第一表面平行的方向上，所述第一距离、所述第二距离、和所述第三距离的总和等于或小于150微米。
在该结构中，所述第一距离、所述第二距离、和所述第三距离均等于或小于50微米。
在该结构中，进一步包括：底部填充材料，所述底部填充材料位于所述衬底和所述第一管芯以及所述衬底和所述第二管芯之间，所述底部填充材料位于所述第一管芯和所述第二管芯之间。
在该结构中，所述衬底是中介层衬底。
在该结构中，所述衬底是有源管芯衬底。
根据本发明的另一方面，提供了一种结构，包括：衬底，具有第一表面和与所述第一表面相对的第二表面，所述衬底具有从所述第一表面向所述第二表面延伸的衬底通孔；第一管芯，与所述衬底相接合，所述第一管芯与所述衬底的所述第一表面相连接；第二管芯，与所述衬底相接合，所述第二管芯与所述衬底的所述第一表面相连接，所述第一管芯的第一边缘和所述第二管芯的第一边缘之间具有第一距离，所述第一管芯的第一边缘和所述第二管芯的第一边缘是第一邻近管芯边缘，所述第一距离等于或大于380微米；以及底部填充材料，位于所述第一管芯的第一边缘和所述第二管芯的第二边缘之间。
在该结构中，所述第一距离小于600微米。
在该结构中，进一步包括：第三管芯，与所述衬底相接合，所述第三管芯与所述衬底的所述第一表面相连接，所述第二管芯的第二边缘和所述第三管芯的第一边缘之间具有第二距离，所述第二管芯的第二边缘和所述第三管芯的第一边缘是第二邻近管芯边缘，所述第二距离大于380微米。
在该结构中，所述底部填充材料位于所述第二管芯的第二边缘和所述第三管芯的第一边缘之间。
在该结构中，进一步包括：第四管芯，与所述衬底相接合，所述第四管芯与所述衬底的所述第一表面相连接，所述第三管芯的第二边缘和所述第四管芯的第一边缘之间具有第三距离，所述第三管芯的第二边缘和所述第四管芯的第一边缘是第三邻近管芯边缘，所述第三距离大于380微米。
在该结构中，所述底部填充材料位于所述第三管芯的第二边缘和所述第四管芯的第一边缘之间。
在该结构中，所述衬底是中介层衬底、有源管芯衬底、或其组合。
根据本发明的又一方面，提供了一种方法，包括：将至少两个管芯与衬底的第一表面相接合，所述衬底具有在其中延伸的衬底通孔，所述至少两个管芯在所述至少两个管芯中的邻近管芯之间具有平均间隔，所述平均间隔位于与所述衬底的所述第一表面平行的方向上，所述平均间隔是200微米或更小；以及在接合所述至少两个管芯之后，对所述衬底的第二表面进行处理，所述第二表面与所述第一表面相对。
在该方法中，所述处理包括穿过所述衬底的所述第二表面暴露出所述衬底通孔。
在该方法中，进一步包括：将底部填充材料分布在所述衬底和所述至少两个管芯中的每一个之间；以及固化所述底部填充材料，所述底部填充材料位于所述至少两个管芯中的邻近管芯之间。
在该方法中，所述至少两个管芯包括三个管芯，所述平均间隔为125微米或更小。
在该方法中，所述至少两个管芯包括四个管芯，所述平均间隔是50微米或更小。
附图说明
为了更全面地理解实施例及其优势，现将结合附图所进行的描述作为参考，其中：
图1A和图1B分别是根据实施例的四管芯两个半维度的集成电路（2.5DIC）结构的截面图和布局图；
图2是描绘出晶圆翘曲与带有图1A和图1B中的结构的管芯对管芯间隔的关联的图表；
图3A和图3B分别是根据另一个实施例的三管芯2.5DIC结构的截面图和布局图；
图4A和图4B分别是根据又一个实施例的两管芯2.5DIC结构的截面图和布局图；
图5是示出了根据实施例将平均间隙距离作为结构上的管芯数量的函数的图表；
图6是根据实施例的从晶圆中单分出来的管芯；
图7是根据实施例的带有图6所示的管芯的两管芯2.5DIC结构的截面图；
图8A和图8B是根据实施例的结构图像的一部分；
图9A至图9H是根据实施例的形成结构的方法。
具体实施方式
下面，详细讨论本发明各实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的概念。所讨论的具体实施例仅仅示出了制造和使用本发明的具体方式，而不用于限制本发明的范围。
将结合具体语境，即，具有连接至无源中介层的管芯的两个半维度的集成电路（2.5IC）结构来描述实施例。其他实施例也可以被应用于具有叠加的有源管芯的三维IC（3DIC）、具有与有源中介层连接的管芯的2.5DIC等。
图1A和图1B分别示出的是在根据实施例的处理过程中四管芯2.5DIC结构的截面图和布局图。结构10包括带有分别通过第一连接件26、第二连接件28、第三连接件30以及第四连接件32连接至无源中介层12的第一管芯18、第二管芯20、第三管芯22以及第四管芯24。连接件26、28、30以及32可以是导电凸块（诸如，微凸块）并且可以将相应的管芯18、20、22以及24与无源中介层12电连接和机械连接。无源中介层12包括在衬底13中的衬底通孔（TVS，在本领域中也被称为“半导体通孔”或“硅通孔”）14以及在衬底13的正面上的再分配层（RDL）。各个凸块接合焊盘位于RDL 16（未示出）上并且与相应的连接件26、28、30和32相连接。各个凸块接合焊盘与穿过RDL 16的相应的TSV 14电连接。底部填充材料34包围着连接件26、28、30和32并且位于其间，并且位于中介层12和管芯18、20、22和24之一之间。底部填充材料34也位于邻接的管芯之间，诸如，位于第一管芯18和第二管芯20之间，位于第二管芯20和第三管芯22之间以及位于第三管芯22和第四管芯24之间。
值得注意的是，为了实现3DIC结构，另一个实施例使用了有源管芯，该有源管芯包括TSV以及代替中介层12的有源器件。另外，中介层12可以具有位于衬底13中的器件，使得该中介层12可以被称为有源中介层。
中介层12上的管芯之间存在三个间隙。第一间隙位于第一管芯18和第二管芯20之间并且具有第一距离40。第二间隙位于第二管芯20和第三管芯22之间并且具有第二距离42。第三间隙位于第三管芯22和第四管芯24之间并且具有第三距离44。
这三个间隙具有用于控制结构10的翘曲的距离值。该值可以被描述成邻近的管芯之间的间隙的平均距离。该平均距离可以被确定为管芯数量的函数，并且该平均距离可以控制结构10的临界的翘曲值。如下面更详细地论述，更具体地可以大体上通过图5中的图表来体现该平均距离。应该注意，间隙的距离不必彼此相等，然而这些距离也可以是相等的。这些距离可以具有不同的值，但在实施例中，所有这些距离的总和等于或小于平均距离乘以间隙数。
在公开的实施例中，在包括衬底13共计12英寸的晶圆中假设出偏斜（deflection）为600微米的翘曲值，这是因为，在该偏斜下可能发生底部填充的明显分层、凸块裂缝和/或TSV裂缝并且在该偏斜下，在衬底13的背面处理过程中工艺会受到不利影响。第一管芯18、第二管芯20、第三管芯22以及第四管芯24每个都具有大约为770微米的厚度（例如，在与中介层12的正面垂直的方向上）。中介层12具有用于位于中介层12的正面上的第一管芯18、第二管芯20、第三管芯22以及第四管芯24的组合的管芯连接区域，该连接面积大约为680平方微米。在这些条件下，衬底10中的三个间隙的平均距离为10至50微米或更小，例如，间隙的每个距离可以是50微米或更小。因此，这三个间隙的距离总数为150微米或更小，并且这三个间隙的距离可以被分配成相等的或不等的。如图2所示，只要平均的管芯对管芯间隔（图1A和图1B中的距离40、42和44）保持等于或小于50微米，那么翘曲（例如，在结构10的处理过程中晶圆的偏斜）就保持不大于600微米。
对于具有四个以上管芯的结构而言，假设所有其他条件都如前述那样，那么平均间隔在50微米或更小时就达到了饱和（saturate）。因此，对于带有四个间隙的五管芯结构而言，间隙距离的总和为200微米或更小。如上所述，间隙距离可以是相等的或不等的。
图3A和图3B分别示出了根据另一个实施例的三管芯2.5DIC结构70的截面图和布局图。结构70与图1A和1B中的结构10类似。结构70包括分别通过第一连接件26、第二连接件28以及第三连接件30与中介层12连接的第一管芯18、第二管芯20以及第三管芯22。在这个三管芯结构70中，在相应的邻近的管芯之间存在两个间隙。位于第一管芯18和第二管芯20之间的间隙具有第一距离72，位于第二管芯20和第三管芯22之间的间隙具有第二距离74。
如上所述，间隙具有用于控制包括衬底13的晶圆的翘曲的距离值，并且该值可以被描述成基于晶圆的数量的平均距离。假设维度与之前根据图1A和图1B中的结构10所论述的维度相同，在中介层上的管芯区域不同的情况下，由于所存在的管芯较少，所以用于结构70中的管芯之间的间隙的平均距离大约为125微米或更小，例如，每个间隙距离可以等于或小于125微米。
图4A和图4B分别示出了根据另一个实施例的两管芯2.5DIC结构80的截面图和布局图。结构80与图1A和图1B的结构10类似。结构80包括分别通过第一连接件26和第二连接件28与中介层12连接的第一管芯18和第二管芯20。在该两管芯结构80中，管芯之间存在一个间隙。该位于第一管芯18和第二管芯20之间的间隙具有第一距离82。
如上所述，该间隙具有用于控制包括衬底13的晶圆的翘曲的距离值，并且该值可以被描述成基于晶圆数量的平均距离。假设维度与之前根据图1A和图1B中的结构10所论述的维度相同，在中介层上的管芯区域不同的情况下，结构80中的管芯之间的间隙的距离大约为200微米或更小。
图5示出了带有各种数量的管芯结构的用于控制结构的翘曲的平均间隙距离。如前所述，带有四个或更多管芯的结构的平均间隙距离具有等于50微米或更小的管芯间平均间隙距离。对于具有四个管芯或更多管芯的结构而言，该平均间隙距离在大约50微米或更小时饱和。带有三个管芯的结构的平均间隙距离具有125微米或更小的管芯间平均间隙距离。带有两个管芯的结构的间隙距离具有200微米或更小的间隙距离。如上所述，平均间隙距离可以小于这些确定值，并且由此，结构中的邻近管芯之间的间隙可以均小于其相应的结构的确定值。
图6示出了实施例的其他部件。图6示出了从经过处理的晶圆中单分出来的管芯90。每个管芯90都包括被密封环94围绕的有源区域92。在实施例中，锯片（saw blade）宽度减小，从而在单分出来的管芯90之间产生较窄的切口宽度96。在相应的密封环94和管芯边缘之间，管芯90可以具有管芯晶圆的过量的衬底材料，诸如，具有距离98或距离100。例如，距离98和距离100均可以等于或大于15微米。
通过使用较窄的锯片或设计较宽的划片槽，可以将实施例集成到现有的工艺中。例如，不需要为了得到在密封环94和管芯边缘之间带有过量衬底材料的管芯而对晶圆的处理过程进行更改。另外，不需要为了实现在此所公开的间隙距离而对位于将与管芯90连接的中介层12上的连接件的足迹（或在此情况下可以是有源管芯）进行更改。过量的材料可以使得管芯具有更大的面积，由此减小了邻近的管芯之间的距离。
图7示出了两管芯2.5DIC结构110的截面图。结构110与图4A的结构80类似。结构80的第一管芯18被图7的结构110中的管芯90所替代。管芯90利用连接件112与中介层12的正面相连接，该连接件具有小于管芯90的面积的足迹。沿着管芯90的外部区域的过量材料具有距离98，该距离减小了管芯90和第二管芯20之间的间隙距离，从而实现了根据图4A所公开的距离。应该注意到，实施例想要将管芯90的特征用于结构中的所有管芯、一些管芯或不用于任何管芯以及用于具有任意数量管芯的结构。
重新参考图2，可以通过使管芯之间具有更大的平均距离来控制衬底的翘曲，诸如，在600微米以下的偏斜。在这些实施例中，管芯对管芯的间隔可以大于大约380微米，诸如，在大约380微米至大约600微米之间。该管芯对管芯间隔可以是包括了任意数量的管芯的结构的平均间隙距离。
另外，在这些实施例中，底部填充材料桥接了邻近的管芯之间的间隙。图8A和图8B是在具有不同间隙距离的邻近的管芯之间桥接的带有底部填充材料间隙实例的图像的一部分。具有图8A和图8B所示的间隙的结构除了具有在大约380微米和600微米之间的平均间隙距离以外，可以与图1A、1B、3A、3B、4A以及4B所示的结构类似。在图8A中，该结构包括与衬底101连接的第一管芯102和第二管芯103。底部填充材料104位于第一管芯102和第二管芯103之间，桥接了间隙距离105。该实施例中的间隙距离105大约为400微米，诸如，397微米。在图8B中，与图8A中的结构类似的结构具有大约为500微米（诸如，497微米）的间隙距离107。底部填充材料106位于第一管芯102和第二管芯103之间，桥接了间隙距离107。
图9A至图9H示出了根据实施例的形成结构（诸如，图4的两管芯结构80或图8A或图8B的结构）的方法。应该理解的是，提供该顺序是为了说明目的，但可以使用其他顺序。另外，本领域的普通技术人员能够轻易地理解为了形成在此公开的其他结构，甚至是在其他实施例中所预期的结构而对该方法所做的更改。
首先参考图9A，示出了被加工成晶圆的一部分的衬底13带有穿过衬底13的正面而形成的TSV 14。衬底13可以具有，例如，在衬底13的正面中形成的有源器件，并且由此可以是3DIC的管芯。衬底13在衬底13中可以没有有源源器件，并且由此可以是2.5DIC的无源中介层。在其他实施例中，衬底13可以具有位于衬底13中的有源器件并且可以是2.5DIC结构的有源中介层。
衬底13通常包括与衬底类似的，被用于形成将与中介层连接的管芯的材料，诸如，硅。然而衬底13可以由其他材料形成，可以相信，由于硅衬底和通常被用于管芯的硅之间的热膨胀系数（CTE）的不匹配低于其与由不同材料所形成的衬底之间的热膨胀系数不匹配，所以使用用于中介层或管芯的硅衬底可以减小应力。
通过例如，通过蚀刻、碾磨、激光技术、其组合等等在衬底13中形成凹部来形成TSV 14。诸如，通过化学汽相沉积（CVD）、原子层沉积（ALD）、物理汽相沉积（PVD）、热氧化、其组合等等将薄阻挡层共形地沉积在衬底13的正面上方以及开口中。该阻挡层可以包含氮化物或氮氧化物，诸如，氮化钛、氮氧化钛、氮化钽、氮氧化钽、氮化钨、其组合等等。将导电材料沉积在薄阻挡层上方以及开口中。可以通过电化学电镀（ECP）工艺、CVD、ALD、PVD、其组合等等形成该导电材料。导电材料的实例是铜、钨、铝、银、金、其组合等等。通过例如化学机械抛光（CMP）将过量的导电材料和阻挡层从衬底13的正面去除。因此，TSV 14包括导电材料和位于导电材料和衬底13之间的薄阻挡层。
在图9B中，正面处理继续形成RDL 16。RDL 16可以包括任意数量的金属化层、金属间介电（IMD）层、通孔、以及钝化层或其组合。图9B中所描述的RDL 16包括三层金属化层，诸如，IMD层中的第一金属化层（M1）120、第二金属化层（M2）122、以及第三金属化层（M3）124。通孔形成在IMD层中的金属化层之间。通过沉积IMD层，使用例如可接受的光刻技术蚀刻出IMD层中的层的金属化图案，沉积用于IMD层中的金属化的导电材料并且通过例如CMP去除任意过量的导电材料来形成这些金属化层。尤其当穿过IMD直至下面的金属化层形成通孔时，该光刻工艺可以包括单镶嵌工艺或双镶嵌工艺。
该IMD层可以是氧化物电介质，诸如，硼磷硅酸盐玻璃（BPSG）或其他电介质材料。该金属化层的导电材料可以是，例如，铜、镍、铝、铜铝、钨、钛、其组合等等。该金属化层可以包括位于导电材料和IMD材料之间的阻挡层，诸如，氮化钛、氮化钽等或其组合，并且可以在IMD层之间形成其他介电层，诸如，由例如氮化硅形成的蚀刻停止层。
在图9B中的顶部金属化层（第三金属化层124）形成之后，在这些金属化层上方形成一层或多层钝化层。该钝化层可以是聚酰亚胺、BPSG、氮化硅、其组合等等，并且可以使用旋涂技术、CVD、ALD、PVD、其组合等等形成该钝化层。为了在顶部金属化层上形成凸块接合焊盘，穿过钝化层形成了开口126，从而暴露出图9B中的顶部金属化层（第三金属化层124）。可以使用例如可接受的光刻技术和蚀刻技术来形成开口126。
参考图9C，穿过顶部金属化层上的开口126形成凸块接合焊盘128，并且在该凸块接合焊盘128上形成了导电凸块130。导电凸块130大体上与第一连接件26以及第二连接件28相对应。可以通过在开口126中沉积导电材料并且将该导电材料图案化成凸块接合焊盘128来形成凸块接合焊盘128。该导电材料可以包括铜、银、锡、钛、钨、其组合等等，并且通过PVD、CVD、ALD、其组合等等进行沉积。可以通过可接受的光刻技术和蚀刻技术来图案化凸块接合焊盘128。导电凸块130通过ECP等等形成在凸块接合焊盘128上，并且可以包含铜、锡、镍、其组合等等。
在图9D中，通过导电凸块130连接第一管芯18和第二管芯20。如根据图4A和图4B或图8A和图9B所描述的那样，第一管芯18和第二管芯20具有位于其间的相应的间隙，每个间隙具有位于第一管芯18和第二管芯20之间的距离82。底部填充材料34被分布在围绕着凸块130的位置上，并且位于管芯18、管芯20和中介层12或有源管芯之间。底部填充材料34也位于相应的第一管芯18和第二管芯20之间的间隙中。
可以根据可接受的半导体处理技术和器件要求处理管芯18和20。在实施例中，根据图6处理管芯18和管芯20之一或两者时，过量的晶圆衬底材料位于管芯边缘和密封环之间。管芯18和20可以是公知的使用拾取和放置（pick-and-place）工具连接的优良管芯，并且可以在分布底部填充材料34之前将导电凸块130回流。该底部填充材料34可以是使用可接受的分布或涂布设备进行分布的液态的环氧树脂、可变形的凝胶、硅橡胶、干膜、其组合等等。
在图9E中，例如，在将底部填充材料34固化之后，通过应用模塑料134和使用压缩模塑法来封装管芯18和20。如果模塑料134在管芯18和20的顶面上方，那么可以（例如，通过CMP）打磨模塑料134，从而暴露出管芯18和20的表面。
衬底13的背面处理以图9F中所描绘的作为开始。在背面处理过程中，图9E的晶圆上芯片（CoW）与载体衬底136相接合。可以使用黏合剂将载体衬底136与管芯18和20和/或模塑料134相接合。在后续的处理步骤中，载体衬底136通常提供临时的机械支撑和结构支撑。由此降低或防止了对中介层或管芯的损害。载体衬底136可以包括，例如，玻璃、氧化硅、氧化铝、其组合等等。该黏合剂可以是任意适当的黏合剂，诸如，紫外线（UV）胶，该紫外线胶在暴露在UV光线下时失去其黏性。
在图9F中，通过薄化衬底13来使TSV 14从衬底13的背面突出出来。可以使用蚀刻工艺和/或平坦化工艺（诸如，CMP工艺）来执行该薄化工艺。例如，最初可以执行平坦化工艺（诸如，CMP）来初步暴露出TSV 14的阻挡层。然后，可以在阻挡层材料和衬底13之间实施具有高蚀刻率选择性的一个或多个湿式蚀刻工艺，从而使得TSV 14从衬底13的背面突出出来。该蚀刻工艺也可以是，例如，干式蚀刻工艺。图9F中示出了，一层或多层介电层（诸如，介电层138和140）沉积在衬底13的背面上方。介电层138和140可以是，例如，氧化硅、氮化硅、氮氧化硅、其组合等等。然后，（例如，通过CMP）对该背面进行平坦化，使得TSV 14暴露在背面上。
图9G示出了钝化层142、球接合焊盘144以及导电球146的形成。钝化层142形成在介电层138和140上方的背面上，并且可以是通过旋涂技术、CVD、ALD、其组合等等所形成的，例如，聚酰亚胺、BPSG、聚苯并恶唑（PBO）、其组合等等。为了形成球接合焊盘144，穿过钝化层142形成了开口以便暴露出，例如，TSV 14。可以使用例如可接受的光刻技术和蚀刻技术来形成该开口。可以通过在开口中沉积导电材料（诸如，金属，例如，铬、铜铬合金、铜、金、钛、钨钛、镍、其组合或类似的金属的一层或多层）并且将该导电材料图案化成球接合焊盘144来形成球接合焊盘144。可以通过ECP、印刷等等来沉积该导电材料，并且可以通过可接受的光刻技术和蚀刻技术来进行图案化。导电球146通过ECP、印刷等等形成在球接合焊盘144上，并且可以包含铜、锡、共晶焊料、无铅焊料、镍、其组合等等。
应该注意，图9G示出了球接合焊盘144直接与TSV 14连接，然而，可以在衬底13的背面上形成一个或多个金属化层和IMD层来电连接球接合焊盘144和TSV 14。金属化层背面可以由任意导电材料（诸如，铜、铜合金、铝、银、金、其组合等等）形成，并且通过任意适当的技术（诸如，ECP、无电镀、其他沉积方法，诸如，溅射、印刷、CVD、PVD、其组合等等）形成。
然后，如图9H所示，利用与框架（frame）148邻近的导电球146将该组件与框架148接合，并且去除载体衬底136。然后，诸如，沿着切分线150将该组件切分成带有中介层和任意数量管芯的独立封装，诸如，图4A、图8A或图8B中所示的结构80。
实施例可以具有多种优点。在管芯接合工艺之后的处理过程中，可以通过控制管芯对管芯间隔来控制晶圆翘曲。这可以减小能够降低结构中的压力的管芯翘曲，从而减少TSV和/或凸块裂缝和/或底部填充分层。因此，实施例可以提供更大的工艺窗和更高的产量。同样，由于减小了由翘曲所造成的风险，因此可以更简单地进行晶圆处理。另外，在实施例中，管芯之间的电线可以更短，从而提供了更低的电阻和电容。
一个实施例是包括了衬底、第一管芯、以及第二管芯的结构。该衬底具有第一表面和与第一表面相反的第二表面。该衬底具有从第一表面向第二表面延伸的衬底通孔。第一管芯与衬底相接合，并且第一管芯与衬底的第一表面相连接。第二管芯与衬底相接合，并且第二管芯与衬底的第一表面相连接。第一管芯的第一边缘和第二管芯的第一边缘之间具有第一距离，并且该第一距离在与衬底的第一表面平行的方向上。第一距离等于或小于200微米。
另一个实施例是包括了衬底和至少两个管芯的结构。该衬底具有从衬底的第一表面延伸出的衬底通孔。至少两个管芯均与衬底的第一表面相连接，并且该至少两个管芯在至少两个管芯中的邻近的管芯之间具有平均距离。该平均距离在与第一表面平行的方向上，并且该平均距离等于或小于200微米。
另一个实施例是一种结构。该结构包括衬底、第一管芯、第二管芯、以及底部填充材料。该衬底具有第一表面和与第一表面相对的第二表面，并且该衬底具有从第一表面向第二表面延伸的衬底通孔。第一管芯与衬底相接合，并且第一管芯与衬底的第一表面相连接。第二管芯与衬底相接合，并且第二管芯与衬底的第一表面相连接。第一管芯的第一边缘和第二管芯的第一边缘之间具有第一距离，并且第一管芯的第一边缘和第二管芯的第一边缘是第一邻近管芯边缘。第一距离等于或大于380微米。该底部填充材料位于第一管芯的第一边缘和第二管芯的第二边缘之间。
又一个实施例是一种方法，该方法包括：将至少两个管芯与衬底的第一表面相接合。该衬底具有从第一表面延伸出的衬底通孔。该至少两个管芯在至少两个管芯中的邻近管芯之间具有平均间隔，并且该平均间隔在与衬底的第一表面平行的方向上。该平均间隔是200微米或更小。该方法进一步包括：在接合了至少两个管芯之后，对衬底的第二表面进行处理，该第二表面与第一表面相对。
尽管已经详细地描述了本发明及其优势，但应该理解，可以在不背离所附权利要求限定的本发明主旨和范围的情况下，做各种不同的改变，替换和更改。而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解，通过本发明，现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造，材料组分、装置、方法或步骤根据本发明可以被使用。因此，所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。

Claims (18)

1.一种半导体结构，包括：
衬底，具有第一表面和与所述第一表面相对的第二表面，所述衬底具有从所述第一表面向所述第二表面延伸的衬底通孔；
第一管芯，与所述衬底相接合，所述第一管芯与所述衬底的所述第一表面相连接；以及
第二管芯，与所述衬底相接合，所述第二管芯与所述衬底的所述第一表面相连接，所述第一管芯的第一边缘和所述第二管芯的第一边缘之间具有第一距离，所述第一距离在与所述衬底的所述第一表面平行的方向上，所述第一距离等于或小于200微米；
第三管芯，与所述衬底相接合，所述第三管芯与所述衬底的所述第一表面相连接，所述第二管芯的第二边缘和所述第三管芯的第一边缘之间具有第二距离，所述第二距离在与所述衬底的所述第一表面平行的方向上，所述第一距离和所述第二距离的总和等于或小于250微米，
其中，所述第一管芯、所述第二管芯以及所述第三管芯呈直线布置。
2.根据权利要求1所述的半导体结构，其中，所述第一距离和所述第二距离均等于或小于125微米。
3.根据权利要求1所述的半导体结构，进一步包括：第四管芯，与所述衬底相接合，所述第四管芯与所述衬底的第一表面相连接，所述第三管芯的第二边缘和所述第四管芯的第一边缘之间具有第三距离，所述第三距离在与所述衬底的所述第一表面平行的方向上，所述第一距离、所述第二距离、和所述第三距离的总和等于或小于150微米。
4.根据权利要求3所述的半导体结构，其中，所述第一距离、所述第二距离、和所述第三距离均等于或小于50微米。
5.根据权利要求1所述的半导体结构，进一步包括：底部填充材料，所述底部填充材料位于所述衬底和所述第一管芯以及所述衬底和所述第二管芯之间，所述底部填充材料位于所述第一管芯和所述第二管芯之间。
6.根据权利要求1所述的半导体结构，其中，所述衬底是中介层衬底。
7.根据权利要求1所述的半导体结构，其中，所述衬底是有源管芯衬底。
8.一种半导体结构，包括：
衬底，具有第一表面和与所述第一表面相对的第二表面，所述衬底具有从所述第一表面向所述第二表面延伸的衬底通孔；
第一管芯，与所述衬底相接合，所述第一管芯与所述衬底的所述第一表面相连接；
第二管芯，与所述衬底相接合，所述第二管芯与所述衬底的所述第一表面相连接，所述第一管芯的第一边缘和所述第二管芯的第一边缘之间具有第一距离，所述第一管芯的第一边缘和所述第二管芯的第一边缘是第一邻近管芯边缘，所述第一距离等于或大于380微米；以及
底部填充材料，位于所述第一管芯的第一边缘和所述第二管芯的第二边缘之间；以及
第三管芯，与所述衬底相接合，所述第三管芯与所述衬底的所述第一表面相连接，所述第二管芯的第二边缘和所述第三管芯的第一边缘之间具有第二距离，所述第二管芯的第二边缘和所述第三管芯的第一边缘是第二邻近管芯边缘，所述第二距离大于380微米，
其中，所述第一管芯、所述第二管芯以及所述第三管芯呈直线布置。
9.根据权利要求8所述的半导体结构，其中，所述第一距离小于600微米。
10.根据权利要求8所述的半导体结构，其中，所述底部填充材料位于所述第二管芯的第二边缘和所述第三管芯的第一边缘之间。
11.根据权利要求8所述的半导体结构，进一步包括：第四管芯，与所述衬底相接合，所述第四管芯与所述衬底的所述第一表面相连接，所述第三管芯的第二边缘和所述第四管芯的第一边缘之间具有第三距离，所述第三管芯的第二边缘和所述第四管芯的第一边缘是第三邻近管芯边缘，所述第三距离大于380微米。
12.根据权利要求11所述的半导体结构，其中，所述底部填充材料位于所述第三管芯的第二边缘和所述第四管芯的第一边缘之间。
13.根据权利要求8所述的半导体结构，其中，所述衬底是中介层衬底、有源管芯衬底、或其组合。
14.一种形成半导体结构的方法，包括：
将至少两个管芯与衬底的第一表面相接合，所述衬底具有在其中延伸的衬底通孔，所述至少两个管芯在所述至少两个管芯中的邻近管芯之间具有平均间隔，所述平均间隔位于与所述衬底的所述第一表面平行的方向上，所述平均间隔是200微米或更小；以及
在接合所述至少两个管芯之后，对所述衬底的第二表面进行处理，所述第二表面与所述第一表面相对，
其中，所述至少两个管芯包括至少三个管芯，所述至少三个管芯呈直线布置。
15.根据权利要求14所述的方法，其中，所述处理包括穿过所述衬底的所述第二表面暴露出所述衬底通孔。
16.根据权利要求14所述的方法，进一步包括：
将底部填充材料分布在所述衬底和所述至少两个管芯中的每一个之间；以及
固化所述底部填充材料，所述底部填充材料位于所述至少两个管芯中的邻近管芯之间。
17.根据权利要求14所述的方法，其中，所述至少两个管芯包括三个管芯，所述平均间隔为125微米或更小。
18.根据权利要求14所述的方法，其中，所述至少两个管芯包括四个管芯，所述平均间隔是50微米或更小。
CN201210187476.1A 2011-08-30 2012-06-07 用于半导体结构的管芯对管芯间隙控制及其方法 Active CN102969305B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/221,447 2011-08-30
US13/221,447 US8963334B2 (en) 2011-08-30 2011-08-30 Die-to-die gap control for semiconductor structure and method

Publications (2)

Publication Number Publication Date
CN102969305A CN102969305A (zh) 2013-03-13
CN102969305B true CN102969305B (zh) 2015-10-07

Family

ID=47665328

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210187476.1A Active CN102969305B (zh) 2011-08-30 2012-06-07 用于半导体结构的管芯对管芯间隙控制及其方法

Country Status (5)

Country Link
US (2) US8963334B2 (zh)
KR (1) KR101420855B1 (zh)
CN (1) CN102969305B (zh)
DE (1) DE102012100796B4 (zh)
TW (1) TWI528505B (zh)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8659144B1 (en) * 2011-12-15 2014-02-25 Marvell International Ltd. Power and ground planes in package substrate
US8933551B2 (en) * 2013-03-08 2015-01-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3D-packages and methods for forming the same
US10192810B2 (en) 2013-06-28 2019-01-29 Intel Corporation Underfill material flow control for reduced die-to-die spacing in semiconductor packages
JP6424610B2 (ja) * 2014-04-23 2018-11-21 ソニー株式会社 半導体装置、および製造方法
CN105023877B (zh) 2014-04-28 2019-12-24 联华电子股份有限公司 半导体晶片、封装结构与其制作方法
US9842825B2 (en) 2014-09-05 2017-12-12 Taiwan Semiconductor Manufacturing Company, Ltd. Substrateless integrated circuit packages and methods of forming same
US9455243B1 (en) 2015-05-25 2016-09-27 Inotera Memories, Inc. Silicon interposer and fabrication method thereof
US10957672B2 (en) * 2017-11-13 2021-03-23 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
US10796976B2 (en) * 2018-10-31 2020-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of forming the same
US20200168527A1 (en) * 2018-11-28 2020-05-28 Taiwan Semiconductor Manfacturing Co., Ltd. Soic chip architecture
CN111725185A (zh) * 2019-03-04 2020-09-29 苏州多感科技有限公司 图像传感器及其制备方法、图像识别方法、电子设备
US11114360B1 (en) 2019-09-24 2021-09-07 Xilinx, Inc. Multi-die device structures and methods
US11205639B2 (en) * 2020-02-21 2021-12-21 Xilinx, Inc. Integrated circuit device with stacked dies having mirrored circuitry
US11482497B2 (en) * 2021-01-14 2022-10-25 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure including a first die and a second die and a bridge die and method of forming the package structure
US11973040B2 (en) * 2021-04-23 2024-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. Interposer with warpage-relief trenches

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1921085A (zh) * 2005-06-24 2007-02-28 米辑电子股份有限公司 线路组件结构制造方法及其结构
JP4128945B2 (ja) * 2003-12-04 2008-07-30 松下電器産業株式会社 半導体装置
CN102017141A (zh) * 2008-04-29 2011-04-13 奥斯兰姆奥普托半导体有限责任公司 可表面安装的发光二极管模块以及用于制造可表面安装的发光二极管模块的方法

Family Cites Families (62)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4695870A (en) * 1986-03-27 1987-09-22 Hughes Aircraft Company Inverted chip carrier
US4811082A (en) 1986-11-12 1989-03-07 International Business Machines Corporation High performance integrated circuit packaging structure
US4990462A (en) 1989-04-12 1991-02-05 Advanced Micro Devices, Inc. Method for coplanar integration of semiconductor ic devices
US5075253A (en) 1989-04-12 1991-12-24 Advanced Micro Devices, Inc. Method of coplanar integration of semiconductor IC devices
US5380681A (en) 1994-03-21 1995-01-10 United Microelectronics Corporation Three-dimensional multichip package and methods of fabricating
US5510273A (en) * 1995-04-03 1996-04-23 Xerox Corporation Process of mounting semiconductor chips in a full-width-array image
US6002177A (en) 1995-12-27 1999-12-14 International Business Machines Corporation High density integrated circuit packaging with chip stacking and via interconnections
US6087199A (en) * 1998-02-04 2000-07-11 International Business Machines Corporation Method for fabricating a very dense chip package
US6213376B1 (en) 1998-06-17 2001-04-10 International Business Machines Corp. Stacked chip process carrier
US6281042B1 (en) 1998-08-31 2001-08-28 Micron Technology, Inc. Structure and method for a high performance electronic packaging assembly
US6271059B1 (en) 1999-01-04 2001-08-07 International Business Machines Corporation Chip interconnection structure using stub terminals
US6461895B1 (en) 1999-01-05 2002-10-08 Intel Corporation Process for making active interposer for high performance packaging applications
US6229216B1 (en) 1999-01-11 2001-05-08 Intel Corporation Silicon interposer and multi-chip-module (MCM) with through substrate vias
US6243272B1 (en) 1999-06-18 2001-06-05 Intel Corporation Method and apparatus for interconnecting multiple devices on a circuit board
US6355501B1 (en) 2000-09-21 2002-03-12 International Business Machines Corporation Three-dimensional chip stacking assembly
KR100364635B1 (ko) 2001-02-09 2002-12-16 삼성전자 주식회사 칩-레벨에 형성된 칩 선택용 패드를 포함하는 칩-레벨3차원 멀티-칩 패키지 및 그 제조 방법
KR100394808B1 (ko) 2001-07-19 2003-08-14 삼성전자주식회사 웨이퍼 레벨 적층 칩 패키지 및 그 제조 방법
KR100435813B1 (ko) 2001-12-06 2004-06-12 삼성전자주식회사 금속 바를 이용하는 멀티 칩 패키지와 그 제조 방법
DE10200399B4 (de) 2002-01-08 2008-03-27 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Erzeugung einer dreidimensional integrierten Halbleitervorrichtung und dreidimensional integrierte Halbleitervorrichtung
US6661085B2 (en) 2002-02-06 2003-12-09 Intel Corporation Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack
US6887769B2 (en) 2002-02-06 2005-05-03 Intel Corporation Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
US6975016B2 (en) 2002-02-06 2005-12-13 Intel Corporation Wafer bonding using a flexible bladder press and thinned wafers for three-dimensional (3D) wafer-to-wafer vertical stack integration, and application thereof
US6762076B2 (en) 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
US6600222B1 (en) 2002-07-17 2003-07-29 Intel Corporation Stacked microelectronic packages
US6790748B2 (en) 2002-12-19 2004-09-14 Intel Corporation Thinning techniques for wafer-to-wafer vertical stacks
US6908565B2 (en) 2002-12-24 2005-06-21 Intel Corporation Etch thinning techniques for wafer-to-wafer vertical stacks
TW578282B (en) * 2002-12-30 2004-03-01 Advanced Semiconductor Eng Thermal- enhance MCM package
US6924551B2 (en) 2003-05-28 2005-08-02 Intel Corporation Through silicon via, folded flex microelectronic package
US6946384B2 (en) 2003-06-06 2005-09-20 Intel Corporation Stacked device underfill and a method of fabrication
US7320928B2 (en) 2003-06-20 2008-01-22 Intel Corporation Method of forming a stacked device filler
KR100537892B1 (ko) 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
US7345350B2 (en) 2003-09-23 2008-03-18 Micron Technology, Inc. Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias
KR100621992B1 (ko) 2003-11-19 2006-09-13 삼성전자주식회사 이종 소자들의 웨이퍼 레벨 적층 구조와 방법 및 이를이용한 시스템-인-패키지
TWI236747B (en) * 2004-03-12 2005-07-21 Advanced Semiconductor Eng Manufacturing process and structure for a flip-chip package
KR100570514B1 (ko) 2004-06-18 2006-04-13 삼성전자주식회사 웨이퍼 레벨 칩 스택 패키지 제조 방법
KR100618837B1 (ko) 2004-06-22 2006-09-01 삼성전자주식회사 웨이퍼 레벨 패키지를 위한 얇은 웨이퍼들의 스택을형성하는 방법
US7307005B2 (en) 2004-06-30 2007-12-11 Intel Corporation Wafer bonding with highly compliant plate having filler material enclosed hollow core
US7087538B2 (en) 2004-08-16 2006-08-08 Intel Corporation Method to fill the gap between coupled wafers
US7317256B2 (en) 2005-06-01 2008-01-08 Intel Corporation Electronic packaging including die with through silicon via
US7557597B2 (en) 2005-06-03 2009-07-07 International Business Machines Corporation Stacked chip security
US7402515B2 (en) 2005-06-28 2008-07-22 Intel Corporation Method of forming through-silicon vias with stress buffer collars and resulting devices
US7432592B2 (en) 2005-10-13 2008-10-07 Intel Corporation Integrated micro-channels for 3D through silicon architectures
US7528494B2 (en) 2005-11-03 2009-05-05 International Business Machines Corporation Accessible chip stack and process of manufacturing thereof
US7410884B2 (en) 2005-11-21 2008-08-12 Intel Corporation 3D integrated circuits using thick metal for backside connections and offset bumps
US7402442B2 (en) 2005-12-21 2008-07-22 International Business Machines Corporation Physically highly secure multi-chip assembly
US7279795B2 (en) 2005-12-29 2007-10-09 Intel Corporation Stacked die semiconductor package
US20080002460A1 (en) * 2006-03-01 2008-01-03 Tessera, Inc. Structure and method of making lidded chips
TWI331391B (en) * 2007-03-20 2010-10-01 Siliconware Precision Industries Co Ltd Stackable semiconductor device and fabrication method thereof
US7576435B2 (en) 2007-04-27 2009-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Low-cost and ultra-fine integrated circuit packaging technique
KR101213175B1 (ko) 2007-08-20 2012-12-18 삼성전자주식회사 로직 칩에 층층이 쌓인 메모리장치들을 구비하는반도체패키지
US8222079B2 (en) * 2007-09-28 2012-07-17 International Business Machines Corporation Semiconductor device and method of making semiconductor device
US9660153B2 (en) * 2007-11-14 2017-05-23 Cree, Inc. Gap engineering for flip-chip mounted horizontal LEDs
US7915080B2 (en) * 2008-12-19 2011-03-29 Texas Instruments Incorporated Bonding IC die to TSV wafers
TWI455263B (zh) * 2009-02-16 2014-10-01 Ind Tech Res Inst 晶片封裝結構及晶片封裝方法
US8689437B2 (en) * 2009-06-24 2014-04-08 International Business Machines Corporation Method for forming integrated circuit assembly
JP5532744B2 (ja) * 2009-08-20 2014-06-25 富士通株式会社 マルチチップモジュール及びマルチチップモジュールの製造方法
JP5635247B2 (ja) * 2009-08-20 2014-12-03 富士通株式会社 マルチチップモジュール
US10276486B2 (en) * 2010-03-02 2019-04-30 General Electric Company Stress resistant micro-via structure for flexible circuits
US8218334B2 (en) * 2010-03-09 2012-07-10 Oracle America, Inc. Multi-chip module with multi-level interposer
US8313982B2 (en) * 2010-09-20 2012-11-20 Texas Instruments Incorporated Stacked die assemblies including TSV die
US9412708B2 (en) * 2011-01-19 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Enhanced ESD protection of integrated circuit in 3DIC package
US8779553B2 (en) * 2011-06-16 2014-07-15 Xilinx, Inc. Stress-aware design for integrated circuits comprising a stress inducing structure and keep out zone

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4128945B2 (ja) * 2003-12-04 2008-07-30 松下電器産業株式会社 半導体装置
CN1921085A (zh) * 2005-06-24 2007-02-28 米辑电子股份有限公司 线路组件结构制造方法及其结构
CN102017141A (zh) * 2008-04-29 2011-04-13 奥斯兰姆奥普托半导体有限责任公司 可表面安装的发光二极管模块以及用于制造可表面安装的发光二极管模块的方法

Also Published As

Publication number Publication date
US20150125994A1 (en) 2015-05-07
KR20130024695A (ko) 2013-03-08
TW201310586A (zh) 2013-03-01
US20130049216A1 (en) 2013-02-28
KR101420855B1 (ko) 2014-07-18
TWI528505B (zh) 2016-04-01
US8963334B2 (en) 2015-02-24
US10157879B2 (en) 2018-12-18
DE102012100796B4 (de) 2020-03-12
CN102969305A (zh) 2013-03-13
DE102012100796A1 (de) 2013-02-28

Similar Documents

Publication Publication Date Title
CN102969305B (zh) 用于半导体结构的管芯对管芯间隙控制及其方法
US20240021544A1 (en) Seal ring for hybrid-bond
US10879140B2 (en) System and method for bonding package lid
CN109937476B (zh) 晶片级封装和方法
US20200126938A1 (en) 3D Packages and Methods for Forming the Same
CN111883481B (zh) 3d封装件结构及其形成方法
US9991190B2 (en) Packaging with interposer frame
KR101570272B1 (ko) 상호접속 구조물 및 이의 제조 방법
CN108074828A (zh) 封装结构及其形成方法
TWI575664B (zh) 封裝結構及其形成方法
TW201810565A (zh) 封裝、半導體元件及封裝的形成方法
US20130154091A1 (en) Semiconductor device packaging using encapsulated conductive balls for package-on-package back side coupling
CN105374693A (zh) 半导体封装件及其形成方法
KR101508841B1 (ko) 패키지 온 패키지 구조물 및 이의 형성 방법
WO2014209404A1 (en) Interconnect structure comprising fine pitch backside metal redistribution lines combined with vias
EP3154078A2 (en) Fan-out wafer level package structure
US10796930B2 (en) Semiconductor device with decreased warpage and method of fabricating the same
US9548283B2 (en) Package redistribution layer structure and method of forming same
CN105225967A (zh) 封装半导体器件的方法和封装的半导体器件
TWI544555B (zh) 半導體封裝結構及其製造方法
US20210257335A1 (en) Semiconductor package and method of manufacturing the same
TW201642428A (zh) 矽中介層與其製作方法
US8988893B2 (en) Method for electrical connection between elements of a three-dimensional integrated structure and corresponding device
TWI773400B (zh) 半導體元件及其製造方法
CN113097201B (zh) 半导体封装结构、方法、器件和电子产品

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant