CN1893045A - 半导体装置制造用基板、半导体装置的制造方法 - Google Patents
半导体装置制造用基板、半导体装置的制造方法 Download PDFInfo
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- CN1893045A CN1893045A CNA2006101011403A CN200610101140A CN1893045A CN 1893045 A CN1893045 A CN 1893045A CN A2006101011403 A CNA2006101011403 A CN A2006101011403A CN 200610101140 A CN200610101140 A CN 200610101140A CN 1893045 A CN1893045 A CN 1893045A
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Abstract
半导体装置制造用基板,具备:晶片;多个半导体元件,其形成在所述晶片上;凸块,其配置在所述半导体元件的各个周边部;对准标记,其配置在所述半导体元件的所述各个周边部;以及粘接层,其形成在所述半导体元件上。所述粘接层的厚度为在未配置有所述凸块的所述半导体元件的各个中央部的厚度比在所述半导体元件的所述各个周边部的厚度要厚。
Description
技术领域
本发明涉及半导体装置制造用基板、以及使用该半导体装置制造用基板的半导体装置的制造方法。
背景技术
以往,通常的使用各向异性导电薄膜或者非导电性薄膜等的粘接薄膜的倒装片安装方法为,向基板侧供给粘接薄膜,在其上对附着凸块的IC进行加热加压胶接(bonding)而连接的方法。
然而,提出了从最近的高密度安装要求出发,尽量减少粘接薄膜的突出量,从在IC附近也搭载其他部件、或者减小安装区域的期望出发,向晶片侧预先供给粘接薄膜,对其进行切割,用与IC相同大小的粘接薄膜来安装的方法(例如,特开2001-237268号公报)。
根据这样的方法,在基板与IC的对准情况下,IC侧隔着粘接薄膜而检测对准标记。然而,在这种情况下,产生下面的问题。
通常,考虑形成在IC侧的凸块的高度、以及形成在基板侧的布线的厚度(IC与基板之间间隙),而确定粘接薄膜的厚度。例如,在安装在玻璃基板上的COG(Chip on Glass)中,由于玻璃基板侧的布线厚度为埃级别的厚度,因此几乎不需要考虑,只需考虑凸块高度量而确定粘接薄膜的厚度即可。另一方面,在COB(Chip on Borad)中,有必要将粘接薄膜的厚度增大布线的厚度(数十μm)的量。在这种情况下,会产生对准时的倒装片接合性的摄像识别性因粘接薄膜的增厚量而相应地下降的问题。
发明内容
本发明,其目的在于提供一种能够实现简便且可靠地制造半导体装置的半导体装置制造用基板、以及使用该半导体装置制造用基板的半导体装置的制造方法。
本发明的半导体装置制造用基板,具备:晶片;多个半导体元件,其形成在上述晶片上;凸块,其配置在上述半导体元件的各个周边部;对准标记,其配置在上述半导体元件的上述各个周边部;以及粘接层,其形成在上述半导体元件上,并且其厚度为在未配置有上述凸块的上述半导体元件的各个中央部的厚度比在上述半导体元件的上述各个周边部的厚度要厚。
根据这样的半导体装置制造用基板,在形成在晶片上的粘接材料层之中,位于未配置有凸块的半导体元件中央部的粘接材料层,比配置有凸块的半导体元件周边部的粘接材料层更厚,而粘接材料层成为在中央部中突出的形状,因此将包括半导体元件的基板安装在例如具有规定的布线图案的布线基板上时,通过将该突出部分与布线基板相对而进行安装,从而在该突出部分中能够实现可靠的粘接。另一方面,由于作为凸块的形成区域的周边部的粘接材料层的膜厚相对于中央部较薄,因此难以产生配置在该周边部的对准标记的检测性(目视性)因粘接材料层的介入而导致下降的不良情况。其结果,根据本发明的半导体装置制造用基板,对于如上上述的布线基板能够满足在安装半导体元件时的连接可靠性、以及在对准时的标记检测性(目视性)。特别,当布线基板的布线厚度较厚的情况下,在将考虑半导体元件的目视性的薄膜均匀地形成的粘接材料层中,在布线基板与半导体元件之间产生未填充粘接材料层的区域(间隙),因密接性下降而导致粘接可靠性下降。然而,如本发明,将中央部相对地作成厚膜(即凸形状)时,能够彻底填充这样的间隙而提高密接性,进而能够得到连接可靠性。
在上述的半导体装置制造用基板中,上述粘接层能够具有:第一粘接层以及第二粘接层,上述第一粘接层以均匀的厚度形成在上述半导体层上,上述第二粘接层形成在上述第一粘接层上的上述半导体元件的上述中央部。这样将粘接材料层作成层叠型的情况下,能够简便地形成具有上述的薄膜厚关系的粘接材料层。具体而言,能够采用:在形成第一粘接材料层之后选择性地进行层压第二粘接材料层的方法、以及在形成第一粘接材料层之后由光刻法选择形成第二粘接材料层的方法。
还有,在上述半导体装置制造用基板中,在上述第一粘接材料层以及上述第二粘接材料层之中,能够仅使上述第一粘接材料层具有导电粒子。由此通过仅在第一粘接材料层含有导电粒子,能使半导体元件与布线基板之间绝缘,且能够实现凸块与布线之间的可靠的电连接。
本发明的半导体装置的制造方法,具有:在晶片上形成多个半导体元件的工序,所述多个半导体元件在各个周边部配置有凸块和对准标记;在上述半导体元件上形成粘接层的工序,其中,上述粘接层的膜厚为在未配置有上述凸块的上述半导体元件的各个中央部的厚度比在上述半导体元件的上述各个周边部的膜厚要厚;切断上述晶片,取得对应于上述半导体元件的多个单片半导体元件的工序;将上述各个单片半导体元件经由上述粘接层安装在具有规定图案的布线的布线基板上。使用这样的半导体装置制造用基板的半导体元件的安装,其可靠性非常高,并且连接稳定性良好。
还有,在上述切断工序中,能够在上述半导体元件的周边部进行切断。在切断工序中,通过对晶片与粘接材料同时进行切割,以使半导体元件与粘接材料层的大小相同(即形成为粘接材料层覆盖半导体元件的整个表面),由于可以将其他电子部件搭载在半导体元件周围,从而能够实现高密度安装。
还有,在上述安装工序中,在使形成在所述单个半导体元件上的粘接材料层中的所述膜厚的部分(突出部分)、与在上述布线基板未形成有上述布线的部分相对的状态下,能够将单片半导体元件安装在布线基板上。在这种情况下,在周边部连接凸块与布线基板的布线,并且在突出部分中半导体元件与布线基板可靠地密接而不会形成间隙,从而能够确保连接稳定性。
附图说明
图1是本实施方式的半导体装置制造用基板的俯视示意图。
图2是图1的A-A’剖面示意图。
图3A以及3B是表示半导体装置制造用基板的一制造工序例的剖面示意图。
图4是表示半导体装置制造用基板的切断工序的一例的剖面示意图。
图5是表示安装工序的一例的剖面示意图。
图6是表示使用图1的半导体装置制造用基板而制造的半导体装置的一例的剖面示意图。
图7是用于表示图6的半导体装置的效果的说明图。
图8是表示安装工序的一变形例的剖面示意图。
图9是表示半导体装置制造用基板的一变形例的剖面示意图。
具体实施方式
下面,参照附图说明本发明的实施方式。还有,在下面用于说明的各个附图中,为了可识别各个部件,而适当地改变各个部件的比例尺。
图1是表示本发明的半导体装置制造用基板的一实施方式的俯视示意图,图2是图1的A-A’剖面示意图。图1以及图2所示的半导体装置制造用基板50,将具备多个半导体元件5的晶片1作为基材而构成。还有,在此晶片1使用硅而构成。
在晶片1的表面上形成有凸块3。具体而言凸块3配置在各个半导体元件5的周边部,各个半导体元件5被形成为***(peripheral)形状。在包括凸块3的晶片1上形成有粘接材料层2。粘接材料层2具有以片状的均匀薄膜厚形成在晶片1的整个面上的第一粘接材料层2a、以及以规定图案形成在第一粘接材料层2a上的岛状的第二粘接材料层2b。
在此,粘接材料层2由通过加热加压可粘接的热硬化型粘接材料构成。在本实施方式中对于第一粘接材料层2a与第二粘接材料层2b采用不同种类的粘接材料。作为这样的热硬化型粘接材料,例如可以使用将环氧树脂、丙烯酸树脂等作为主要材料的粘接材料等。例如能将第一粘接材料层2a由环氧树脂构成,能将第二粘接材料层2b由丙烯酸树脂构成。若通过第二粘接材料层2b存在,而粘接材料层2形成为突出形状,则对材质没有特别的限制,而在第一粘接材料层2a与第二粘接材料层2b中可以使用相同种类的粘接材料。
第二粘接材料层2b,配置在各个半导体元件5中没有形成凸块3的区域,即配置在各个半导体元件5的中心侧区域。由此通过第二粘接材料层2b选择形成在半导体元件5的中心侧(中央部),从而粘接材料层2,在没有配置有凸块3的中心侧比在各个半导体5中配置有凸块3的周边部形成得较厚。即,在各个半导体元件5中,粘接材料层2在半导体元件5的周边部以薄薄膜(例如20μm)形成,而在半导体元件5的中心侧中以厚薄膜(例如30μm)形成。结果粘接材料层2被构成为在半导体元件5的中心侧包括突出部分的形状。
还有,在第一粘接材料层2a以及第二粘接材料层2b之中,只有在第一粘接材料层2a含有导电粒子6。在将半导体装置制造用基板50粘接在布线基板等的情况下,通过含有这样的导电粒子6,可使该布线与凸块3电连接。
还有,凸块3,在此采用通过电镀形成的金凸块,但也可以采用形成镍后镀金的凸块。
接着,参照图3A以及图3B说明制造半导体装置制造用基板50的方法。
首先,如图3A所示,在晶片1上以规定图案形成凸块3,并且形成多个相同的构成的半导体元件5。晶片1由硅半导体结晶构成。在此,使用通过电镀形成的金凸块,然而也可以采用球状凸块(ball bumps)。
接着,在晶片1上形成粘接材料层2(图3B)。在此,由以下方法形成粘接材料层2以使其具有凸状图案。
即,在晶片1的整个面上层压(laminate)由环氧树脂构成的薄膜树脂而形成第一粘接材料层2a。接着,将由丙稀酸树脂构成的粘接薄膜排列在规定母材上以使其形成在各个半导体元件5上,使用其而一并层压。
还有,在通过这样的层压而形成粘接材料层2的情况下,在第一粘接材料层2a与第二粘接材料层2b中可以使用相同材质的粘接材料。例如将分别由环氧树脂构成的薄膜树脂以片状形成在晶片的整个面上之后,在其上能够按照规定图案形成单片薄膜树脂。在层压时,优选在减压状态下进行。通过在减压状态下进行,能够防止在晶片1与粘接材料层2之间混入气泡的不良反应的发生。
还有,在晶片1的整个面上以片状形成第一粘接材料层2a之后,以由感光性树脂构成的片状的第二粘接材料层2b覆盖该第一粘接材料层2a的整个面,可通过曝光对其进行图案形成以使粘接材料层2突出形状化。在这种情况下,第一粘接材料层2a有必要采用在第二粘接材料层2b的曝光时具有耐光性的材料。还有,第一粘接材料层2a以及第二粘接材料层2b有必要分别采用不同的粘接材料。
还有,例如如图9所示,在用单一的材料形成粘接材料层2的情况下,由使用光刻法的掩模蚀刻(mask etching)能得到突出形状。具体而言,在晶片1的整个面上以片状形成粘接材料之后,掩模各个半导体元件5的中央部(即想要形成突出形状的部分),蚀刻粘接材料,从而能够形成图9所示构成的粘接材料层2。
接着,参照图4以及图5,说明使用上述半导体装置制造用基板50的半导体装置的制造方法。
首先,如图4所示,对上述半导体装置制造用基板50进行切割。具体而言,使用金刚石刀具30,沿着半导体元件5的界线(切断线)45一并切断晶片1以及粘接材料层2。通过进行切割能得到如图5所示的单片半导体元件15。还有,界线45并不是在实际中画的线,而是指通过基于对准标记40(参照图1)的对位而确定的虚拟切断线。
还有,在单片半导体元件15上,形成粘接材料层2以覆盖包括凸块3的晶片1。在粘接材料层2中,第二粘接材料层2b形成在第一粘接材料层2a上。其结果,粘接材料层2,如上所述在具有凸块3的周边部形成为薄膜,而在中心部形成为厚膜。
接着,如图5所示,在具有以规定的图案形成的布线11的布线基板10上,安装单片半导体元件15。在此,经由上述粘接材料层2粘接布线基板10与单片半导体元件15。
具体而言,对准布线基板10与单片半导体元件15之后,在将布线基板10中没有形成布线11的区域(布线非形成区域)12,与粘接材料层2的突出部分(即第二粘接材料层2b)相对的状态下,粘接布线基板10与单片半导体元件15。参照图1所示的对准标记40进行对准。通过在相互接触的状态下对基板10与元件15进行加热,并通过熔融粘接材料层2,从而进行粘接。
通过这样的安装方法,制造安装有如图6所示的半导体元件15的半导体装置100。该半导体装置100,其凸块3与布线11之间的电连接良好,并且其基板10与半导体元件15之间的密接性也良好。
当形成在布线基板10上的布线11较厚的情况下,如图7所示,若形成考虑对准标记40(参照图1)的检测性(目视性)的厚度均匀的粘接材料层22,则存在在布线基板10与粘接材料层22之间形成未填充粘接材料层22的区域(间隙)的可能性。由此,在半导体元件15与布线基板10之间形成间隙的安装中,存在由该间隙导致密接性下降,连接可靠性降低的情况。然而,根据由上述方法制造的半导体装置100(参照图6),通过第二粘接材料层2b的突出形状,不会在半导体元件15与布线基板10之间形成间隙,能够可靠地进行粘接。
如上所述在布线11较厚的情况下,例如也能够采用如图8所示的方法,来制造兼备电连接性与基板-元件之间连接性的半导体元件15。即,在布线基板10的未形成有布线11的区域12配置粘接材料层2d(粘接材料层2d比布线11更厚)。还有,在半导体元件15形成均匀厚度的粘接材料层2a,并且使粘接材料层2d与粘接材料层2a相对而进行粘接。即使是这样的安装方法,在区域12中也不会形成间隙,能够防止在基板-元件之间形成间隙的不良情况的发生。
以上,对本发明的优选实施例进行说明,然而本发明并不限定于这些实施例。在不脱离本发明的要点的范围内,可以进行结构的添加、省略、置换、以及其他修改。本发明并不限定于所述的说明,而仅被附加的权利要求书的范围所限定。
Claims (4)
1、一种半导体装置制造用基板,具备:
晶片;
多个半导体元件,其形成在所述晶片上;
凸块,其配置在所述半导体元件的各个周边部;
对准标记,其配置在所述半导体元件的所述各个周边部;以及
粘接层,其形成在所述半导体元件上,并且其厚度为在未配置有所述凸块的所述半导体元件的各个中央部的厚度比在所述半导体元件的所述各个周边部的厚度要厚。
2、根据权利要求1所述的半导体装置制造用基板,其特征在于,
所述粘接层,具有第一粘接层以及第二粘接层,所述第一粘接层以均匀的厚度形成在所述半导体层上,所述第二粘接层形成在所述第一粘接层上的所述半导体元件的所述中央部。
3、根据权利要求2所述的半导体装置制造用基板,其特征在于,
在所述第一粘接层以及所述第二粘接层之中,只有所述第一粘接层具有导电粒子。
4、一种半导体装置的制造方法,包括:
在晶片上形成多个半导体元件的工序,所述多个半导体元件在各个周边部配置有凸块和对准标记;
在所述半导体元件上形成粘接层的工序,所述粘接层的膜厚为在未配置有所述凸块的所述半导体元件的各个中央部的厚度比在所述半导体元件的所述各个周边部的厚度要厚;
切断所述晶片,并得到与所述半导体元件相对应的多个单片半导体元件的工序;以及
在具有规定图案的布线的布线基板上经由所述粘接层安装所述各个单片半导体元件的工序。
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CNB2006101011403A Expired - Fee Related CN100433318C (zh) | 2005-07-07 | 2006-07-03 | 半导体装置制造用基板、半导体装置的制造方法 |
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US (1) | US20070007666A1 (zh) |
JP (1) | JP4123251B2 (zh) |
KR (1) | KR100816346B1 (zh) |
CN (1) | CN100433318C (zh) |
TW (1) | TWI303464B (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103094220A (zh) * | 2011-10-28 | 2013-05-08 | 株式会社东芝 | 存储装置、半导体装置及其制造方法 |
CN107154455A (zh) * | 2016-03-04 | 2017-09-12 | 日东电工(上海松江)有限公司 | 密封光半导体元件的制造方法 |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201011830A (en) * | 2008-09-03 | 2010-03-16 | United Test Ct Inc | Self-adhesive semiconductor wafer |
JP4702424B2 (ja) * | 2008-10-08 | 2011-06-15 | カシオ計算機株式会社 | 液晶表示素子 |
KR101212029B1 (ko) * | 2011-12-20 | 2012-12-13 | 한국기초과학지원연구원 | 화합물 결합단백질 검출 방법 |
Family Cites Families (15)
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JPS6130059A (ja) * | 1984-07-20 | 1986-02-12 | Nec Corp | 半導体装置の製造方法 |
US4769523A (en) * | 1985-03-08 | 1988-09-06 | Nippon Kogaku K.K. | Laser processing apparatus |
JP2547895B2 (ja) * | 1990-03-20 | 1996-10-23 | シャープ株式会社 | 半導体装置の実装方法 |
DE69618458T2 (de) * | 1995-05-22 | 2002-11-07 | Hitachi Chemical Co., Ltd. | Halbleiterteil mit einem zu einem verdrahtungsträger elektrisch verbundenem chip |
EP0952762B1 (en) * | 1996-12-19 | 2011-10-12 | Ibiden Co, Ltd. | Printed wiring board and method for manufacturing the same |
US5962921A (en) * | 1997-03-31 | 1999-10-05 | Micron Technology, Inc. | Interconnect having recessed contact members with penetrating blades for testing semiconductor dice and packages with contact bumps |
US6260264B1 (en) * | 1997-12-08 | 2001-07-17 | 3M Innovative Properties Company | Methods for making z-axis electrical connections |
CN1242602A (zh) * | 1998-07-16 | 2000-01-26 | 日东电工株式会社 | 晶片规模封装结构及其内使用的电路板 |
JP3660175B2 (ja) * | 1998-11-25 | 2005-06-15 | セイコーエプソン株式会社 | 実装構造体及び液晶装置の製造方法 |
JP2001237268A (ja) * | 2000-02-22 | 2001-08-31 | Nec Corp | 半導体素子の実装方法及び製造装置 |
US6569753B1 (en) * | 2000-06-08 | 2003-05-27 | Micron Technology, Inc. | Collar positionable about a periphery of a contact pad and around a conductive structure secured to the contact pads, semiconductor device components including same, and methods for fabricating same |
JP3478281B2 (ja) * | 2001-06-07 | 2003-12-15 | ソニー株式会社 | Icカード |
US6791660B1 (en) * | 2002-02-12 | 2004-09-14 | Seiko Epson Corporation | Method for manufacturing electrooptical device and apparatus for manufacturing the same, electrooptical device and electronic appliances |
JP3847260B2 (ja) * | 2003-01-28 | 2006-11-22 | 京セラ株式会社 | Icウエハを用いたフリップチップ型icの製造方法 |
TWI333249B (en) * | 2004-08-24 | 2010-11-11 | Himax Tech Inc | Sensor package |
-
2005
- 2005-07-07 JP JP2005198494A patent/JP4123251B2/ja not_active Expired - Fee Related
-
2006
- 2006-06-21 TW TW095122209A patent/TWI303464B/zh not_active IP Right Cessation
- 2006-06-29 US US11/478,488 patent/US20070007666A1/en not_active Abandoned
- 2006-07-03 CN CNB2006101011403A patent/CN100433318C/zh not_active Expired - Fee Related
- 2006-07-04 KR KR1020060062470A patent/KR100816346B1/ko not_active IP Right Cessation
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103094220A (zh) * | 2011-10-28 | 2013-05-08 | 株式会社东芝 | 存储装置、半导体装置及其制造方法 |
CN107154455A (zh) * | 2016-03-04 | 2017-09-12 | 日东电工(上海松江)有限公司 | 密封光半导体元件的制造方法 |
CN107154455B (zh) * | 2016-03-04 | 2020-03-10 | 日东电工(上海松江)有限公司 | 密封光半导体元件的制造方法 |
Also Published As
Publication number | Publication date |
---|---|
KR100816346B1 (ko) | 2008-03-24 |
JP2007019221A (ja) | 2007-01-25 |
CN100433318C (zh) | 2008-11-12 |
KR20070006569A (ko) | 2007-01-11 |
TWI303464B (en) | 2008-11-21 |
US20070007666A1 (en) | 2007-01-11 |
TW200707605A (en) | 2007-02-16 |
JP4123251B2 (ja) | 2008-07-23 |
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