CN1842070B - 具有多级的定时恢复电路 - Google Patents
具有多级的定时恢复电路 Download PDFInfo
- Publication number
- CN1842070B CN1842070B CN2006100568528A CN200610056852A CN1842070B CN 1842070 B CN1842070 B CN 1842070B CN 2006100568528 A CN2006100568528 A CN 2006100568528A CN 200610056852 A CN200610056852 A CN 200610056852A CN 1842070 B CN1842070 B CN 1842070B
- Authority
- CN
- China
- Prior art keywords
- signal
- circuit
- data
- clock signal
- extraction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000011084 recovery Methods 0.000 title claims abstract description 40
- 230000004044 response Effects 0.000 claims abstract description 33
- 238000000605 extraction Methods 0.000 claims description 127
- 239000000284 extract Substances 0.000 claims description 23
- 238000005070 sampling Methods 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 14
- 230000010355 oscillation Effects 0.000 claims description 6
- 238000001514 detection method Methods 0.000 claims description 5
- 230000001360 synchronised effect Effects 0.000 claims description 3
- 101100328957 Caenorhabditis elegans clk-1 gene Proteins 0.000 description 25
- 101100113692 Caenorhabditis elegans clk-2 gene Proteins 0.000 description 22
- 238000012545 processing Methods 0.000 description 21
- 230000000694 effects Effects 0.000 description 16
- 238000001914 filtration Methods 0.000 description 10
- 102100040856 Dual specificity protein kinase CLK3 Human genes 0.000 description 6
- 101000749304 Homo sapiens Dual specificity protein kinase CLK3 Proteins 0.000 description 6
- 102100040844 Dual specificity protein kinase CLK2 Human genes 0.000 description 5
- 101000749291 Homo sapiens Dual specificity protein kinase CLK2 Proteins 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 238000004891 communication Methods 0.000 description 4
- 230000001186 cumulative effect Effects 0.000 description 3
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- 230000009467 reduction Effects 0.000 description 3
- 238000013459 approach Methods 0.000 description 2
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 240000005373 Panax quinquefolius Species 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
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Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
- H04L7/002—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation
- H04L7/0029—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation interpolation of received data signal
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
- H04L7/0012—Synchronisation information channels, e.g. clock distribution lines by comparing receiver clock with transmitter clock
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
Claims (9)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005-093004 | 2005-03-28 | ||
JP2005093004A JP4213132B2 (ja) | 2005-03-28 | 2005-03-28 | タイミングリカバリ回路及び間引きクロック生成方法 |
JP2005093004 | 2005-03-28 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1842070A CN1842070A (zh) | 2006-10-04 |
CN1842070B true CN1842070B (zh) | 2010-04-14 |
Family
ID=37030914
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2006100568528A Expired - Fee Related CN1842070B (zh) | 2005-03-28 | 2006-03-09 | 具有多级的定时恢复电路 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7173994B2 (zh) |
JP (1) | JP4213132B2 (zh) |
CN (1) | CN1842070B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20210126766A1 (en) * | 2018-07-10 | 2021-04-29 | Socionext Inc. | Phase synchronization circuit, transmission and reception circuit, and integrated circuit |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5108407B2 (ja) | 2007-07-25 | 2012-12-26 | 富士通セミコンダクター株式会社 | シンボルタイミングリカバリ回路 |
CN101286797B (zh) * | 2008-05-19 | 2011-12-28 | 中兴通讯股份有限公司 | 基于obsai协议的定时信号传递方法及*** |
JP5560778B2 (ja) * | 2010-03-05 | 2014-07-30 | 日本電気株式会社 | クロック乗せ換え回路、及びクロック乗せ換え方法 |
US8897656B2 (en) * | 2010-07-08 | 2014-11-25 | Em Photonics, Inc. | Synchronizing phases of multiple opitcal channels |
US9088328B2 (en) | 2011-05-16 | 2015-07-21 | Intel Mobile Communications GmbH | Receiver of a mobile communication device |
US8826062B2 (en) | 2011-05-23 | 2014-09-02 | Intel Mobile Communications GmbH | Apparatus for synchronizing a data handover between a first clock domain and a second clock domain through phase synchronization |
WO2014181573A1 (ja) * | 2013-05-10 | 2014-11-13 | 三菱電機株式会社 | 信号処理装置 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1126331A (zh) * | 1994-09-30 | 1996-07-10 | 美国电报电话公司 | 精定时恢复电路 |
CN1189729A (zh) * | 1996-09-30 | 1998-08-05 | 大宇电子株式会社 | 数字解调器的符号定时恢复电路 |
US6765445B2 (en) * | 2000-07-10 | 2004-07-20 | Silicon Laboratories, Inc. | Digitally-synthesized loop filter circuit particularly useful for a phase locked loop |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4896334A (en) * | 1988-10-24 | 1990-01-23 | Northern Telecom Limited | Method and apparatus for timing recovery |
US6819514B1 (en) * | 1996-04-30 | 2004-11-16 | Cirrus Logic, Inc. | Adaptive equalization and interpolated timing recovery in a sampled amplitude read channel for magnetic recording |
DE69837656T2 (de) * | 1998-06-30 | 2007-12-27 | Lucent Technologies Inc. | Trägerfolgesystem unter Anwendung eines Fehleroffsetfrequenzsignals |
US6363129B1 (en) * | 1998-11-09 | 2002-03-26 | Broadcom Corporation | Timing recovery system for a multi-pair gigabit transceiver |
JP3573627B2 (ja) | 1998-09-28 | 2004-10-06 | 富士通株式会社 | マルチレートシンボルタイミングリカバリ回路 |
US6414990B1 (en) * | 1998-09-29 | 2002-07-02 | Conexant Systems, Inc. | Timing recovery for a high speed digital data communication system based on adaptive equalizer impulse response characteristics |
KR100287867B1 (ko) * | 1998-12-31 | 2001-05-02 | 구자홍 | 디지털 텔레비전의 타이밍 복원 장치 |
JP4366808B2 (ja) * | 2000-01-31 | 2009-11-18 | ソニー株式会社 | タイミングエラー検出回路および復調回路とその方法 |
US6901126B1 (en) * | 2000-06-30 | 2005-05-31 | Texas Instruments Incorporated | Time division multiplex data recovery system using close loop phase and delay locked loop |
US6985549B1 (en) * | 2000-10-20 | 2006-01-10 | Ati Research, Inc. | Blind cost criterion timing recovery |
US6636120B2 (en) * | 2000-11-24 | 2003-10-21 | Texas Instruments Incorporated | Decimated digital phase-locked loop for high-speed implementation |
-
2005
- 2005-03-28 JP JP2005093004A patent/JP4213132B2/ja not_active Expired - Fee Related
-
2006
- 2006-02-21 US US11/357,031 patent/US7173994B2/en active Active
- 2006-03-09 CN CN2006100568528A patent/CN1842070B/zh not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1126331A (zh) * | 1994-09-30 | 1996-07-10 | 美国电报电话公司 | 精定时恢复电路 |
CN1189729A (zh) * | 1996-09-30 | 1998-08-05 | 大宇电子株式会社 | 数字解调器的符号定时恢复电路 |
US6765445B2 (en) * | 2000-07-10 | 2004-07-20 | Silicon Laboratories, Inc. | Digitally-synthesized loop filter circuit particularly useful for a phase locked loop |
Non-Patent Citations (1)
Title |
---|
JP特开平7-147562A 1995.06.06 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20210126766A1 (en) * | 2018-07-10 | 2021-04-29 | Socionext Inc. | Phase synchronization circuit, transmission and reception circuit, and integrated circuit |
Also Published As
Publication number | Publication date |
---|---|
CN1842070A (zh) | 2006-10-04 |
JP2006279332A (ja) | 2006-10-12 |
JP4213132B2 (ja) | 2009-01-21 |
US20060214825A1 (en) | 2006-09-28 |
US7173994B2 (en) | 2007-02-06 |
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C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
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ASS | Succession or assignment of patent right |
Owner name: FUJITSU MICROELECTRONICS CO., LTD. Free format text: FORMER OWNER: FUJITSU LIMITED Effective date: 20081024 |
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Effective date of registration: 20081024 Address after: Tokyo, Japan, Japan Applicant after: Fujitsu Microelectronics Ltd. Address before: Kanagawa Applicant before: Fujitsu Ltd. |
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C14 | Grant of patent or utility model | ||
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C56 | Change in the name or address of the patentee |
Owner name: FUJITSU SEMICONDUCTORS CO., LTD Free format text: FORMER NAME: FUJITSU MICROELECTRON CO., LTD. |
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CP03 | Change of name, title or address |
Address after: Kanagawa Patentee after: Fujitsu Semiconductor Co., Ltd. Address before: Tokyo, Japan, Japan Patentee before: Fujitsu Microelectronics Ltd. |
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ASS | Succession or assignment of patent right |
Owner name: SUOSI FUTURE CO., LTD. Free format text: FORMER OWNER: FUJITSU SEMICONDUCTOR CO., LTD. Effective date: 20150513 |
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C41 | Transfer of patent application or patent right or utility model | ||
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Effective date of registration: 20150513 Address after: Kanagawa Patentee after: Co., Ltd. Suo Si future Address before: Kanagawa Patentee before: Fujitsu Semiconductor Co., Ltd. |
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CF01 | Termination of patent right due to non-payment of annual fee | ||
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