CN1795552A - 制造一种多层互连结构的方法 - Google Patents
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Abstract
一种采用空气作为低k介电体成分在多层互连结构中形成层间介电层的方法,其与金属镶嵌工艺兼容而无需引入另外工艺步骤。所述金属镶嵌工艺导电部件特性是在所述互连结构各层的牺牲型芯材料(22、30)中通过标准光刻和蚀刻工艺形成的。所述各层中的导电部件(28’、32’、34’)被型芯材料包围。在形成互连结构的所有层之后,对所述型芯材料提供一通道(62)。通过所述通道导入一各向同性蚀刻剂,其选择性地蚀刻和去除型芯材料。互连结构中先前由型芯材料占据的空间由空气填充,所述空气充当低k介电体。
Description
技术领域
本发明涉及制造集成电路芯片,更具体而言涉及一种制造集成电路芯片的多层(multi-level)互连结构的工艺。
背景技术
在制造集成电路(IC)芯片中,有源器件尺寸的减小改善了电路的性能并且提升了封装在半导体衬底上的有源器件的复杂度和性能。只有有效地互连有源器件,才能充分实现有源器件密度进步的好处。随着有源器件密度增加和特征尺寸减小,IC芯片电路的性能和功能最终受互连结构信号传输效力和效率的限制。
已经通过更有效地在有源器件之间布置金属线,开发了与有源器件密度提升匹配的多层互连结构。在某些IC设计中,可能需要5个或更多的单独的金属线层以适应所述有源器件密度。多层互连结构在多层中布置金属线,其中各个单极的金属线形成于层间介电体中。所述层间介电体使所述互连结构中各层中的金属线相互电绝缘并且使相邻层中的金属线电绝缘。
在用于制造多层互连结构的后端(back-end-of-line)(BEOL)工艺过程中,通常采用金属镶嵌工艺。在金属镶嵌工艺中,在层间介电体中蚀刻沟槽和通孔,并且用诸如铜(Cu)或铜基合金的金属填充,以制成金属线和在不同层的金属线之间的垂直导电路径。铜比其它考虑用来制造多层互连结构的候选金属,例如铝,具有优越的电迁移阻抗和更低的电阻率。常规的减蚀刻(subtractive etching)方法不能用于形成铜金属线,因为铜难于蚀刻。因此,对于制造铜金属线,金属镶嵌工艺特别具有针对性。
在一种双金属镶嵌工艺中,层间介电层同形地被一层金属覆盖,所述金属同时填充所述沟槽和通孔。通过诸如化学机械抛光(CMP)的工艺从层间介电体中去除多余的过量金属。在沟槽中留下的金属基本在相对于所述衬底的水平方向延伸以界定金属线,并且留在通孔内的金属提供相邻层金属线之间的接触。一种单金属镶嵌工艺在不同的层间介电层中形成沟槽和通孔,并且分别用不同的金属沉积层填充。
随着有源器件密度增加和特征尺寸减小,减小了所述多层互连结构的各层中相邻的依节距(on-pitch)金属线之间和相邻层的金属线之间的线到线的间距。线到线间距的减小增加了线到线的电容,这减慢了由金属线承载的信号的速度,结果产生传播延迟。
可以通过减小层间介电体的介电常数来减小线到线的电容。为此,多层互连结构的一种趋势是由一种介电体形成所述层间介电体,所述介电体的特性在于其相对介电常数小于氧化硅或氟化硅玻璃的介电常数。通常,这样的低k介电体的特性在于其介电常数小于4,氧化硅的介电常数为4。候选的低k材料包括:旋涂低k膜,比如可以从Dow Chemical Co.(Midland,MI)商业获得的SILK;以及化学气相沉积低k膜,比如有机硅化物。由低k介电体提供的线到线电容减小允许相邻金属线设置得更近,并且减少了多层互连结构中的层数。低k介电体的效果是用来对给定的导线密度改善IC芯片的性能。
金属镶嵌工艺对形成层间介电层的材料的性质有严格要求,因此对所述计划用作层间介电体的候选低k介电体有严格要求。所述要求的主体限制了将低k介电体集成于用来制造多层互连结构的金属镶嵌工艺中。具体地,低k介电体必须与金属镶嵌工艺的清洗、蚀刻、CMP和热处理特性兼容。所述低k介电体必须具有足够的机械强度和化学稳定性以经受所有的工艺步骤。
在金属镶嵌工艺中,由常规低k介电体形成的层间介电层由一层蚀刻阻挡层(etch stop layer)覆盖,所述蚀刻阻挡层用来保护免受光致抗蚀剂剥离工艺的影响。所述蚀刻阻挡层还用作CMP工艺的硬掩膜,在均厚沉积填充了通孔和沟槽之后,所述CMP工艺去除覆盖层间介电体的多余金属。如果省略了蚀刻阻挡层,常规的低k介电体软,且在通过CMP工艺抛光时易于形成底切(undercutting)。因为许多低k介电体是亲水的,所述蚀刻阻挡层还保护层间介电体免受在CMP工艺期间引入的潮气的影响,并且保护层间介电体免受强烈的后CMP清洗的侵蚀。
尽管蚀刻阻挡层消除了这些不利影响,但是它们的存在增加了金属镶嵌工艺的复杂度。具体地,需要一种特定的沉积来制成每层蚀刻阻挡层。另一个缺点是所述最常用的蚀刻阻挡层材料氮化硅具有相当高的介电常数,其范围在大约6至大约8之间。因此,蚀刻阻挡层的存在增加了层间介电体的有效介电常数和电容。
用来形成多层互连结构的一种极低k的介电体是空气,它具有大约为1的介电常数。通过引入一种牺牲或可去除材料作为临时层间介电体,并且在所述多层互连结构的各层完成后去除所述牺牲材料,可以有助于工艺期间的机械强度。先前由所述牺牲材料占据的空间是填充空气的孔。
一种常规的形成空气介电体的方法采用非晶碳作为牺牲材料。通过提供一个穿过互连结构延伸的通道,并且在一种氧化环境中加热,以将所述非晶碳转化为从所述通道逸出的含碳气体并而去除非晶碳。但是,在去除非晶碳之前,在各个互连层的金属线上方施加两个氮化硅覆层。各个保护层需要一种独立的光刻图案和蚀刻步骤,从而增加了制造成本并且为了保证所述两个覆层之间的覆盖公差,可能增加所述IC芯片的尺寸。去除非晶碳被认为会恶化形成金属线的材料,这使采用一种附着增强阻挡层(adhesion promotionbarrier layer)完全密封所述金属线成为必须。另外,在后面的层形成之前,从互连结构的各层中去除所述牺牲非晶碳显著增加了制造多层互连结构的复杂性。
另一种形成空气介电体的常规方法使用可流动的氧化或氢硅酸盐玻璃作为牺牲材料。在所述互连结构所有层形成后,通过一种湿化学蚀刻去除所述牺牲材料。所述互连结构通过一种金属镶嵌通孔和减蚀刻金属线工艺形成,而非采用单或双金属镶嵌工艺。减蚀刻工艺形成金属线,并且在互连结构的不同层中界定将来用于去除牺牲材料的通道。
又一种常规的形成空气介电体的方法依靠氮化硅作为牺牲材料。所述金属线通过一种减蚀刻工艺形成,并且涂上一层100nm至200nm的氧化硅作为用于将来去除牺牲材料的保护层。在所述互连结构的不同层形成之后,通过一种对于氮化物对氧化物具有高蚀刻选择性的化学蚀刻剂,例如磷酸,去除所述牺牲材料。所述保护层必须相对较厚,因为磷酸以一种慢但可测量的速率蚀刻氧化硅。随着金属线被布置得越来越密以匹配有源器件密度的增加,避免蚀刻金属线所需的保护层厚度建议与上相邻金属线之间的间距可比。结果,随着依节距金属线之间的间隙减小,这种常规方法变得不能用于提供空气介电体。
因此,需要的正是一种在多层互连结构中形成采用空气作为低k介电材料成分的层间介电层的方法,其可以与金属镶嵌工艺集成而不增加工艺步骤,并且与金属镶嵌工艺中通过化学机械抛光去除材料兼容。
发明内容
根据本发明,现在提供了一种制造多层互连结构的方法,所述方法包括:将型芯材料施加到一衬底;去除部分的所述型芯材料以形成沟槽;去除部分的所述型芯材料以形成通孔;所述沟槽在下面的通孔上敞开;用导电材料填充通孔和沟槽以制成多个部件(feature),在相邻部件之间设置有型芯材料;形成至少一层,所述层覆盖所述部件和型芯材料;界定至少一层通道,所述通道引导所述型芯材料穿过所述层;并且通过将各向同性蚀刻剂引入所述通道从而去除所述型芯材料,所述各向同性蚀刻剂选择性地蚀刻所述型芯材料,以在相邻的部件之间留下空气孔。
所述型芯材料可以选自非晶硅、非晶锗和非晶硅锗。在一个实例中,所述型芯材料为非晶硅且各向同性的蚀刻剂包含氢氧化钾。在另一个实例中,所述型芯材料为非晶锗且各向同性的蚀刻剂包含过氧化氢。去除部分的型芯材料以形成沟槽可以通过单一光刻和蚀刻操作进行。类似地,去除部分的型芯材料以形成通孔也可以通过单一光刻和蚀刻操作进行。所述多层互连结构可以没有覆盖型芯材料的保护层。所述导电材料可以是铜。所述各向同性的蚀刻剂能够选择性地对铜去除型芯材料。所述各向同性的蚀刻剂能够选择性地对钛、氮化钛、钽、氮化钽、氧化硅、氮化硅和铝去除型芯材料。用导电材料填充所述通孔和沟槽还包括通过一种导电材料的单一沉积从而将所述导电材料引入所述通孔和沟槽。
从另一个方面来看本发明,现在提供了一种制造多层互连结构的方法,所述方法包括:在一衬底上形成型芯材料的第一层;去除部分的所述型芯材料的第一层以形成第一沟槽,去除部分的所述型芯材料的第一层以形成第一通孔,所述第一沟槽在下面的第一通孔上敞开;用导电材料填充所述第一通孔和所述第一沟槽以制成多个部件,所述部件具有水平方向分隔相邻第一部件的型芯材料;形成位于第一部件上面的型芯材料的第二层;去除部分的所述型芯材料的第二层以形成第二沟槽,去除部分的所述型芯材料的第二层以形成第二通孔,所述第二沟槽在下面的第二通孔上敞开;用导电材料填充所述第二通孔和所述第二沟槽以制成多个部件,所述部件具有水平方向分隔相邻所述第二部件的型芯材料;所述分隔第二部件的型芯材料与所述分隔第一部件的型芯材料边界相同;形成位于第二部件上面的型芯材料的至少一层;界定至少一通道,所述通道将所述型芯材料引导穿过所述层;通过将各向同性蚀刻剂引入所述通道以去除所述型芯材料,所述各向同性蚀刻剂选择性地蚀刻所述型芯材料,以在相邻的第一部件和相邻的第二部件之间留下空气孔。
从又一个方面来看本发明,现在提供了一种制造多层互连结构的方法,所述方法包括:将型芯材料施加到一衬底;所述型芯材料选自非晶硅、非晶锗和非晶硅锗;去除部分的所述型芯材料部分以形成沟槽;去除部分的所述型芯材料以形成通孔;所述沟槽在下面的通孔上敞开;同时用导电材料填充所述通孔和所述沟槽以制成多个部件,所述部件具有设置在相邻部件之间的型芯材料;形成至少一层,所述层覆盖所述部件和所述型芯材料;界定至少一通道,所述通道将所述型芯材料引导穿过所述层;通过将各向同性蚀刻剂引入所述通道以去除所述型芯材料,所述各向同性蚀刻剂选择性地蚀刻所述型芯材料,以在相邻的部件之间留下空气孔。
从又一个方面来看本发明,现在提供了一种通过所述工艺制造的多层互连结构,所述工艺包括:将型芯材料施加到一衬底;去除部分的所述型芯材料以形成沟槽;去除部分的所述型芯材料以形成通孔;所述沟槽在下面的通孔上敞开;用导电材料填充所述通孔和所述沟槽以制成多个部件,所述部件具有设置在相邻部件之间的型芯材料;形成至少一层,所述层覆盖所述部件和所述型芯材料;界定至少一通道,所述通道将所述型芯材料引导穿过所述层;通过将各向同性蚀刻剂引入所述通道以去除所述型芯材料,所述各向同性蚀刻剂选择性地蚀刻所述型芯材料,以在相邻的部件之间留下空气孔。
本发明的优选实施例涉及一种制造多层互连结构的方法。将型芯材料施加到衬底并且去除部分的所述型芯材料以形成沟槽和通孔,其中沟槽可能在下面的通孔上敞开。然后用导电材料填充所述通孔和沟槽,优选地同时通过单一沉积以制成多个部件。所述型芯材料设置在相邻部件之间,并且形成至少一层,所述层覆盖所述部件和型芯材料。界定一个或更多通道,将所述型芯材料引导通过所述层,并且将各向同性蚀刻剂引入各个通道。所述各向同性蚀刻剂选择性地蚀刻所述型芯材料,以在相邻部件之间留下气孔。在本发明的某些实施例中,型芯材料选自非晶硅、非晶锗和非晶硅锗。在本发明的其它实施例中,可能在型芯材料的单独的层中形成其它填充的通孔和沟槽层,型芯材料在形成覆盖层之前施加,并在之后通过各向同性蚀刻剂去除。
根据本发明的原理,采用型芯材料作为牺牲层间层,其在留下充空气空间的工艺之后可被去除,克服了在金属镶嵌工艺中集成低k介电体所遇到的困难。具体地,所述型芯材料不需要在CMP工艺中用于保护和结构强度的蚀刻阻挡层或其它覆层。所述型芯材料在化学上抵抗光致抗蚀剂剥离期间使用的蚀刻剂,并且具有结构刚度,以应对在CMP工艺期间施加的机械压力。从多层互连结构中消除这样的蚀刻阻挡层降低了互连结构的有效介电常数。
所述型芯材料完全与单或双金属镶嵌工艺兼容,因为所述通孔和沟槽可以通过标准光刻和蚀刻技术形成于型芯材料中。结果,不需要另外的工艺步骤以将本发明的原理结合到金属镶嵌工艺中。此外,所述型芯材料足够坚固,这样就不需要形成比如支撑柱的结构加强体的另外的工艺步骤。这样的结构加强体也可能增加有效介电常数。实施本发明的原理对金属镶嵌工艺几乎不增加额外的成本,并且不需要另外的光刻步骤,否则所述另外的光刻步骤还可能增加芯片尺寸,以解决实现图案对准所需的掩膜覆盖公差问题。
所述型芯材料选择性地对于填充多层互连结构的通孔和沟槽的铜金属和常规的衬垫(liners)是可去除的,所述互连结构用没有蚀刻阻挡层的金属镶嵌工艺形成。所述型芯材料还对互连结构中暴露的其他材料是可去除的,所述材料包括但不仅限于氧化硅、氮化硅和铝。因此,去除型芯材料以留下填充空气的层间介电层不损伤或劣化在互连结构中存在的留下的金属或其他材料。
所述型芯材料的介电特性与本发明无关,也与成品IC芯片无关,因为在IC芯片制造完成之前,所述型芯材料被从后端(back-end-of-line)(BEOL)去除。
附图说明
结合于并且构成本说明书的一部分的附图示出了本发明的实施例,并且与前面给出的一般描述和下面给出的所述实施例的详细描述一起,用来解释本发明的原理。
图1-19是根据本发明的原理的金属镶嵌工艺方法的一实施例的各种阶段的部分的衬底的截面视图。
具体实施方式
本发明涉及制造一种用于集成电路的多层互连结构,其在金属的单独的层之间具有作为层间介电体的空气。根据本发明的原理,在制造所述互连结构期间,一种牺牲型芯材料代替层间介电体,并且在制造之后,去除这种型芯材料,用空气填充所述空的空间。作为该创造性方法的结果,能够容易地、高性价比地采用金属镶嵌工艺的工艺方法和设备特性来制造高质量的多层互连结构。
参照图1,部分的衬底10包括诸如场效应晶体管(FET’s)的栅极导体12和浅沟槽隔离(STI)结构14。衬底10可以是任何合适的半导体衬底材料,包括但不仅限于硅和砷化镓,在其上或在其中,可以通过前端(front-end-of-line)(FEOL)工艺形成有源器件。由一种相对高电阻率的材料,例如硼磷硅酸盐玻璃(BPSG),构成的一绝缘层设置在衬底10上作为金属前(pre-metal)介电体。绝缘层16暴露的表面被抛平并且通过化学机械抛光(CMP)工艺或任何其它合适的平面化技术平面化。通常,CMP工艺涉及一种抛光或机械磨制操作,其由引入到抛光垫和衬底10之间的一种浆料在化学上得到帮助。
通过一种标准光刻和蚀刻工艺在绝缘层16内形成接触开口,通过填充接触开口的均厚沉积导入了一种导电材料,如钨,且通过使用任何合适的平面化技术,如CMP工艺,去除多余的过量的导电材料向下到达绝缘层16,从而提供触点18。然后在抛光过的表面上形成蚀刻阻挡层20,其典型厚度为约10nm至约50nm。所述蚀刻阻挡层20可以由任何数量的不同材料构成,如氮化硅或氧化硅,其通过常规的物理气相沉积或化学气相沉积技术沉积。
参照图2,在蚀刻阻挡层20上沉积型芯层22。如将要在下面讨论的,所述型芯层22代表通过以后的工艺步骤被去除的材料。通常,型芯层22具有范围在大约100nm至大约1000nm之间的厚度。所述型芯层22可以通过任何常规沉积技术沉积,包括但不仅限于化学气相沉积和物理气相沉积,其与沉积形成层22的材料兼容。
参照图3,在型芯层22中界定了多个沟槽24,其在垂直方向延伸到蚀刻阻挡层20的水平面。能够采用单一常规光刻和蚀刻操作形成沟槽24,其中将一抗蚀层(未显示)施加到型芯层22,将其曝光来显露沟槽24的隐性图案特性,并且将其显影来将隐性的图案转变为在沟槽24的位置的型芯层22上界定掩膜区和非掩膜区的最终图案,并且通过任何合适的蚀刻工艺,如各向异性蚀刻(如等离子体蚀刻或反应离子蚀刻),在非掩膜区去除部分的型芯层22,其产生了向下到蚀刻阻挡层20的侧壁以界定沟槽24。在形成沟槽24之后剥离图案化的抗蚀剂。
将这里使用的所述术语“水平”界定为与衬底10的常规平面或表面平行的一平面,不考虑取向。所述术语“垂直”指示与刚界定的“水平”垂直的方向。相对于水平平面界定术语,诸如“上”、“上方”、“下”、“侧”(如在“侧壁”中)、“高”、“低”、“上面”和“下面”。
在界定了沟槽24之后,型芯层22暴露的表面可以选择性地被通过例如低温等离子体氧化生成的薄氧化层26覆盖。典型的氧化层26可以是氧化硅,其厚度为大约10nm至大约50nm。
参照图4,通过比如等离子体或反应离子蚀刻的蚀刻去除由界定沟槽24暴露的蚀刻阻挡层20区域,以允许建立同触点18的电接触。所述型芯层22水平表面上的氧化层26区,如果存在,也通过湿或干蚀刻去除。然后在沟槽24的水平和垂直表面上施加增强附着的阻挡衬垫27(adhesion-promotingbarrier liner)。典型的适用于衬垫27的材料包括:钛、氮化钛、钽、氮化钽、其它难熔金属、金属氮化物及其化合物。可以在衬垫27上方施加一籽层(未图示),以促进此后诸如铜或铜合金的导电金属的电沉积。
接着,通过合适的沉积技术,例如通过无电镀或电镀技术,在衬底10上同形地均厚沉积比如铜或铜合金的金属导电层28。作为选择,可以通过物理气相沉积或化学气相沉积来沉积导电层28。在导电层28均厚沉积之后,金属填充沟槽24并且覆盖型芯层22图案的残留物。如果需要,可以热处理衬底10以在随后的工艺步骤之前退火导电层28的金属。具体地,退火的铜增加了晶粒尺寸以改善电迁移的可靠性并改善与衬垫27的结合。
参照图5,通过任何合适的平面化技术,例如CMP工艺,去除导电层28的多余的金属、型芯层22上存在的衬垫27以及型芯层22上存在的任何氧化层部分,停止在沟槽24的水平面上以提供平面化的表面。填充沟槽24的来源于导电层28的嵌入的金属界定由所述型芯层22包围的导电部件28。所述型芯层22充当CMP工艺的抛光阻挡层。所述合成结构界定了多层互连结构的通常由附图标记29表示的第一层。
参照图6,在平面化的表面上沉积另一型芯层。所述型芯层30的典型厚度在大约100nm至1500nm之间,优选为1000nm。所述型芯层30可以通过任何常规的沉积技术沉积,包括但不仅限于化学气相沉积和物理气相沉积,与沉积形成层30的材料兼容。
参照图7,采用单一常规光刻和蚀刻操作在型芯层30中界定多个通孔32。具体地,将一蚀刻阻挡层(未图示)施加到型芯材料30,将其曝光以显露通孔32的隐性图案特性,且将其显影以将隐性的图案转变为在通孔32的位置的型芯层22上界定掩膜区和非掩膜区的最终图案,并且随后通过任何合适的蚀刻工艺,如各向异性蚀刻(如等离子蚀刻或反应离子蚀刻),将其蚀刻,其产生垂直的通孔侧壁32,在非掩膜区中从型芯层30去除材料并且形成通孔32。通孔32垂直延伸穿过型芯层30向下到导电线28’,用于建立电互连。在界定通孔32之后,将图案化的抗蚀剂剥离。
参照图8,采用单一常规光刻和蚀刻操作在型芯层30内提供多个沟槽34。具体地,将一抗蚀层(未显示)施加到型芯层30,将其曝光来显露沟槽34的隐性图案特性,并且将其显影来将隐性的图案转变为在沟槽24的位置的型芯层30上界定掩膜区和非掩膜区的最终图案,并且通过任何合适的蚀刻工艺,如各向异性蚀刻(如等离子体蚀刻或反应离子蚀刻),其产生了基本垂直沟槽侧壁,在非掩膜区去除部分的型芯层30且形成了沟槽34。在界定沟槽34之后,将图案化的抗蚀剂剥离。形成沟槽34与通孔32对准,以便通常具有一种覆盖关系。型芯层30暴露的水平和垂直表面可以选择性地由一薄氧化层36覆盖,氧化层36可以是通过例如低温等离子体氧化生成的氧化硅。
或者,通孔32可以在沟槽34形成之后而不是在沟槽34形成之前形成,其不偏离本发明的精神和范围。用两者任一顺序进行金属镶嵌工艺的能力是在半导体器件制造领域中的一般技术人员所熟知的。
参照图9,对通孔32和沟槽34的所述水平和垂直表面施加一增强附着的阻挡衬垫39。适用于衬垫39的典型材料包括钛、氮化钛、钽、氮化钽、其它难熔金属及上述物质的化合物。在所述衬垫39上方可以施加一籽层(未图示)以促进以后比如铜或铜合金的导电材料的沉积,如果其通过电镀沉积。接着,在型芯材料30上方均厚沉积一比如铜或铜合金的金属的导电层38。所述导电层38的金属填充通孔32和沟槽34并且覆盖型芯层30图案的残留物。如果需要,可以对所述衬底10进行热处理以在随后的工艺步骤之前对导电层38的金属退火。具体地,退火的铜增加了晶粒尺寸,以改善电迁移的可靠性和促进与衬垫39的结合。
参照图10,采用任何合适的平面化技术,如CMP工艺,去除在沟槽34水平面之上凸出的导电层38中多余的金属、部分的衬垫39和所述型芯层30上的任何氧化层36的部分,以提供平面化的表面。所述型芯层30作为抛光阻挡层。在沟槽34内的嵌入金属界定由型芯层30的材料包围的导电线34’,且通孔32内的嵌入金属界定导电栓32’。
所述合成结构界定多层互连结构的通常用附图标记40表示的第二层。填充通孔32的所述导电栓32’和填充沟槽34的导电线34’互连有源器件和所述互连结构的其它层中的其它类似的导电线。具体地,每个导电栓32’在其下端与导电部件28’之一电接触,并且在其上端与导线34’之一电接触。
参照图11,将图6-10的顺序重复来制造多层互连结构的附加的层。例如,将通常用附图标记42表示的第三互连层加到图11的结构。第三互连层42包括:包围导电栓44的型芯层50,所述导电栓44由型芯层50中金属填充的通孔46界定;导电线48,其由型芯层50中金属填充的沟槽49界定;用于所述导电栓44和导电线48的衬垫51;和可选的氧化层53。
虽然图11示出多层互连结构具有三个独立的层29、40、42,但本发明并不仅限于此,因为按照IC芯片设计和有源器件的密度的要求可以将类似于层40和42的其它层附加到多层互连结构。本发明考虑所述发明原理的混合集成,即在多层互连结构的上层引入作为层间介电体的空气,且在垂直低于去除型芯材料的层的下层,依靠常规的低k介电材料,如旋涂低k膜或化学气相沉积低k膜作为层间介电体。
所述型芯层22、30和50由任何能够通过各向同性蚀刻工艺对于在所述完成的多层互连结构中的其它材料选择性地被去除的材料形成,所述各向同性蚀刻工艺比如湿蚀刻工艺或气态化学蚀刻工艺。具体地,各向同性蚀刻工艺应该对于金属镶嵌工艺的填充通孔和沟槽的金属、设置在型芯层和金属之间的衬垫和暴露于蚀刻工艺的多层互连结构的其他任何材料是选择性的,其包括但不仅限于氧化硅和氮化硅。具体而言,形成型芯层22、30和50的材料对于填充通孔和沟槽的金属和衬垫是选择性可去除的,使得不需要保护阻挡层。
形成型芯层22、30和50的材料还应该具有足够的硬度,以作为用于沉积在被构图的型芯层22、30和50上金属的CMP工艺的抛光阻挡层,以采用金属填充通孔和沟槽以形成导电栓和导电线。具体而言,对于抛光,形成型芯层22、30和50的材料应当与金属镶嵌结构中填充所述通孔和沟槽的金属一样硬,优选为更硬。
构成型芯层22、30和50的材料还应不受到在CMP工艺中使用的浆料的溶解、侵蚀或其它不利影响,或受到跟在所述CMP之后的清洗工艺使用的试剂的影响,CMP工艺平面化填充通孔和沟槽的导电材料。例如,用于抛光铜的常规CMP工艺可以使用一种浆料,所述浆料包括或者过氧化氢和氧化铝、氢氧化胺和氧化铝、或者硝酸和氧化铝,对于所述浆料,形成型芯层22、30和50的材料应当有抵抗力,如果在多层互连结构中使用了优选的铜金属化。
用于型芯层22、30和50的优选候选材料是非晶硅、非晶锗和非晶硅锗。非晶硅在一种包括氢氧化钾溶液的各向同性蚀刻剂中是可蚀刻的,所述蚀刻剂对铜、铜衬垫和在所述衬底上暴露的比如氧化硅、氮化硅和钛的其它普通材料选择性地蚀刻型芯层22、30和50。常规上通过使用例如硅烷(SiH4)的产硅前体(silicon-yielding precursor)作为反应物气体的热化学气相沉积(CVD),通过使用产硅前体作为反应物气体的低压化学气相沉积(LPCVD),通过用产硅前体作为反应物气体的等离子体增强化学气相沉积(PECVD),或通过物理气相沉积(PVD)的技术来生产非晶硅。可以通过使用一种比如锗烷(GeH4)的产锗前体作为反应物气体的类似的CVD方法或通过PVD技术来形成非晶锗,所述非晶锗在包含过氧化氢的溶液中是各向同性可蚀刻的。可以通过使用比如锗烷和硅烷的反应物气体混合物的CVD工艺沉积或通过使用一种合适成分材料的靶的PVD来沉积非晶硅锗。
参照图12和13,在多层互连结构最上层42的平面化的表面上沉积了绝缘层52,其由例如氧化硅、氮化硅或这两种材料的化合物构成。采用常规的光刻和刻蚀技术在绝缘层52中形成多个通孔54。具体而言,将抗蚀层(未图示)施加到所述绝缘层52,将其曝光以显露通孔54的隐性的图案特性,将其显影以将隐性的图案转换为在所述通孔54的位置的绝缘层52上界定掩膜区和非掩膜区的最终的图案,且随后通过任何合适的蚀刻工艺将其蚀刻,所述蚀刻工艺比如各向异性蚀刻(例如等离子体蚀刻或反应离子蚀刻),其产生带锥度的通孔侧壁,以在非掩膜区中从绝缘层52去除材料并且形成通孔54。通孔54垂直延伸到导电线48的水平面。
参照图14和15,在绝缘层52上均厚沉积了导电层56。导电层56由诸如铝或铝基合金的具有相对较高导电率的金属形成。填充通孔54的金属界定导电栓54’。采用常规的减光刻和刻蚀技术构图导电层56以形成导电线58。所述导电线58覆盖导电栓54’,使得通孔54保持填充金属。
参照图16和17,通过沉积由比如氧化硅或氮化硅的一种或多种介电材料构成的绝缘层60从而钝化导电线58。通过常规的光刻和刻蚀技术,在绝缘层52和绝缘层60中界定至少一个,优选为多个通道62。具体而言,将抗蚀层(未图示)施加到绝缘层60,将其曝光以显露通道62的隐性的图案特征,将其显影以将隐性的图案转换为在所述通道62的位置的绝缘层60上界定掩膜区和非掩膜区的最终的图案,且随后通过例如各向异性蚀刻(例如等离子体蚀刻或反应离子蚀刻的任何合适的蚀刻工艺蚀刻,其产生基本垂直的通孔侧壁,以在非掩膜区中从绝缘层52去除材料并且形成通道62。各个通道62位于导电栓54’和导电线58之间。通道62穿过绝缘层52和绝缘层60延伸,但不穿过原来与导电层56相关的金属。通道62向衬底10延伸,以界定畅通无阻的分离的液体通道,其允许流体进入型芯层22、30和50。
将一种通常用附图标记61表示的各向同性蚀刻剂引入通道62,用来去除型芯层22、30和50。可以将各向同性蚀刻剂61通过湿化学工艺或气态化学工艺引入。典型地,将各向同性蚀刻剂61施加到整个衬底10上方,例如通过将衬底10浸没在一包含各向同性蚀刻剂61的液体化学浴中。各向同性蚀刻剂61蚀刻形成型芯层22、30和50的材料,优选在所有方向以同样的速率蚀刻。保持衬底10的浸没直到去除型芯层22、30和50。
参照图18,各向同性蚀刻剂61(图17)的化学反应溶解并且去除形成型芯层22、30和50的材料,而且没有显著改变形成阻挡层20、氧化层26和36、衬垫27、39和51、导电层28、38和56、绝缘层52和绝缘层60的材料。被蚀刻的型芯材料的副产品由各向同性蚀刻剂为媒介扩散通过通道62逸出所述互连结构。空气孔63界定一体积空间,其在前被型芯层22、30和50的材料占据而现在被具有大约为1的介电常数的空气填充。空气孔63将导电部件28’、导电栓32’、导电线34’、导电栓44和导电线48从相互之间电隔离。空气介电体提供了一有效降低线到线电容的低k层间介电体。
参照图19,在多层互连结构的上部沉积一种密封剂64。密封剂64具有填充和密封通道62的部分66。在未硬化状态,密封剂64的粘度应该足够高,使得部分66填充通道62但不进入空气孔63。将密封剂64暴露到用作衬垫(未图示)的敞开区,然后将其硬化成结构上稳定的形式。一种示范性的密封剂64是具有几个微米的厚度的聚酰亚胺。
这样,虽然已通过描述各种的实施例来示出本发明,并且这些实施例已被相当详细地描述,申请人的目的不是限制或用任何方法将权利要求项限制在这样细节的范围。对于本领域的技术人员容易想象另外的利用和修改。这样,本发明在其更广领域因而不仅限于具体细节、代表性设备和方法以及显示和描述的示出的实例。因此,在不改变申请人的总体的发明构思的精神或范围的情况下可以从这样的细节作出改变。
Claims (39)
1.一种制造多层互联结构的方法,包括:
将型芯材料施加到衬底;
去除部分的所述型芯材料以形成沟槽;
去除部分的所述型芯材料以形成通孔,所述沟槽在所述下面的通孔上开口;
用导电材料填充所述通孔和沟槽以制成多个部件,所述部件在相邻部件之间具有设置的介电体;
在所述部件和型芯材料上面形成至少一层;
界定至少一通道,所述通道将型芯材料引导穿过所述层;并且
通过将各向同性的蚀刻剂导入所述通道从而去除所述型芯材料,所述各向同性的蚀刻剂选择性地蚀刻所述型芯材料,在相邻部件之间留下气孔。
2.如权利要求1所述的方法,其中所述型芯材料选自非晶硅、非晶锗和非晶硅锗。
3.如权利要求2所述的方法,其中所述型芯材料是非晶硅,所述各向同性的蚀刻剂包含氢氧化钾。
4.如权利要求2所述的方法,其中所述型芯材料是非晶锗,所述各向同性的蚀刻剂包含过氧化氢。
5.如权利要求1所述的方法,其中去除部分的所述型芯部分以形成沟槽是通过单一光刻和蚀刻操作进行的。
6.如权利要求1所述的方法,其中去除部分的所述型芯部分以形成通孔是通过单一光刻和蚀刻操作进行的。
7.如权利要求1所述的方法,其中所述多层互联结构没有覆盖所述型芯材料的保护层。
8.如权利要求1所述的方法,其中所述导电材料是铜。
9.如权利要求8所述的方法,其中所述各向同性蚀刻剂能够选择性地对铜去除所述型芯材料。
10.如权利要求9的方法,其中所述各向同性蚀刻剂能够选择性地对钛、氮化钛、钽、氮化钽、氧化硅、氮化硅和铝去除所述型芯材料。
11.如权利要求1所述的方法,其中用所述导电材料填充所述通孔和沟槽还包括通过所述导电材料的单一沉积从而将所述导电材料导入所述通孔和沟槽。
12.一种制造多层互连结构的方法,包括:
在衬底上形成型芯材料的第一层;
去除部分的所述型芯材料的第一层以形成第一沟槽;
去除部分的所述型芯材料的第一层以形成第一通孔,所述第一沟槽在所述下面的第一通孔上开口;
用导电材料填充所述第一通孔和第一沟槽以制成多个第一部件,所述部件具有在水平方向分隔相邻第一部件的型芯材料;
在所述第一部件上方形成所述型芯材料的第二层;
去除部分的所述型芯材料的第二层以形成第二沟槽;
去除部分的所述型芯材料的第二层以形成第二通孔,所述第二沟槽在下面的第二通孔上开口;
用导电材料填充所述第二通孔和第二沟槽以制成多个第二部件,所述部件具有在水平方向分隔相邻第二部件的型芯材料;分隔所述第二部件的所述型芯材料与分隔所述第一部件的所述型芯材料具有相同的边界。
在所述第二部件上形成至少一层;
界定至少一通道,所述通道将所述型芯材料引导穿过所述层;且
通过将各向同性蚀刻剂引入所述通道中从而去除所述型芯材料,所述各向同性蚀刻剂选择性地蚀刻所述型芯材料,以在相邻的第一部件之间和相邻的第二部件之间留下空气孔。
13.如权利要求12所述的方法,其中所述型芯材料选自非晶硅、非晶锗和非晶硅锗。
14.如权利要求12所述的方法,其中所述型芯材料是非晶硅,所述各向同性蚀刻剂包含氢氧化钾。
15.如权利要求12所述的方法,其中所述型芯材料是非晶锗,所述各向同性蚀刻剂包含过氧化氢。
16.如权利要求12所述的方法,其中去除所述型芯材料以形成第一沟槽是通过单一光刻和蚀刻操作进行的。
17.如权利要求12所述的方法,其中去除所述型芯材料以形成第一通孔是通过单一光刻和蚀刻操作进行的。
18.如权利要求12的方法,其中去除所述型芯材料以形成第二沟槽是通过单一光刻和蚀刻操作进行的。
19.如权利要求12所述的方法,其中去除所述型芯材料以形成第二通孔是通过一种单光刻和蚀刻操作进行的。
20.如权利要求12所述的方法,其中分隔所述第二部件的所述型芯材料和分隔所述第一部件的所述型芯材料之间的界面没有保护层。
21.如权利要求12所述的方法,其中所述导电材料是铜。
22.如权利要求21所述的方法,其中所述各向同性蚀刻剂能够选择性地对铜去除所述型芯材料。
23.如权利要求22所述的方法,其中各向同性蚀刻剂能够选择性地对钛、氮化钛、钽、氮化钽、氧化硅、氮化硅和铝去除所述型芯材料。
24.一种制造多层互连结构的方法,包括:
将型芯材料施加到衬底,所述型芯材料选自非晶硅、非晶锗和非晶硅锗;
去除部分的所述型芯材料以形成沟槽;
去除部分的所述型芯材料以形成通孔;所述沟槽在所述下面的通孔上开口:
同时用导电材料填充所述通孔和所述沟槽以制成多个部件,所述部分具有设置在相邻部件之间的所述型芯材料;
在所述部件和型芯材料上方形成至少一层;
界定至少一通道,所述通道将所述型芯材料引导穿过所述层;和
通过将所述各向同性蚀刻剂引入所述通道内以去除所述型芯材料,所述各向同性蚀刻剂选择性地蚀刻所述型芯材料,以在相邻部件之间留下空气孔。
25.如权利要求所述24的方法,其中所述型芯材料是非晶硅,所述各向同性蚀刻剂包含氢氧化钾。
26.如权利要求所述24的方法,其中所述型芯材料是非晶锗,所述各向同性蚀刻剂包含过氧化氢。
27.如权利要求所述24的方法,其中去除所述型芯材料以形成沟槽是通过单一光刻和蚀刻操作进行的。
28.如权利要求所述24的方法,其中去除所述型芯材料以形成通孔是通过单一光刻和蚀刻操作进行的。
29.如权利要求所述24的方法,其中多层互连结构没有覆盖所述型芯材料的保护层。
30.如权利要求所述24的方法,其中所述导电材料是铜。
31.如权利要求所述30的方法,其中所述各向同性蚀刻剂能够选择性地对铜去除所述型芯材料。
32.如权利要求所述31的方法,其中所述各向同性蚀刻剂能够选择性地对钛、氮化钛、钽、氮化钽、氧化硅、氮化硅和铝去除所述型芯材料。
33.一种多层互连结构,由所述工艺制造,所述工艺包括:
将型芯材料施加到衬底;
去除部分的所述型芯材料以形成沟槽;
去除部分的所述型芯材料以形成通孔;所述沟槽在所述下面的通孔上开口;
用导电材料填充所述通孔和所述沟槽以制成多个部件,所述部件具有设置在相邻部件之间的所述型芯材料;
在所述部件和型芯材料上方形成至少一层;
界定至少一通道,所述通道将所述型芯材料引导穿过所述层;和
通过将所述各向同性蚀刻剂引入所述通道内以去除所述型芯材料,所述各向同性蚀刻剂选择性地蚀刻所述型芯材料,以在相邻部件之间留下空气孔。
34.如权利要求所述33的多层互连结构,其中所述导电材料是铜。
35.如权利要求所述34的多层互连结构,其中所述各向同性蚀刻剂能够选择性地对铜去除型芯材料。
36.如权利要求所述35的多层互连结构,其中所述各向同性蚀刻剂能够选择性地对钛、氮化钛、钽、氮化钽、氧化硅、氮化硅和铝去除所述型芯材料。
37.如权利要求所述33的多层互连结构,其中所述型芯材料选自非晶硅、非晶锗和非晶硅锗。
38.如权利要求所述37的多层互连结构,其中所述型芯材料选自非晶硅、非晶锗和非晶硅锗。
39.如权利要求所述37的多层互连结构,其中所述型芯材料是非晶硅,所述各向同性蚀刻剂包含氢氧化钾。
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- 2004-05-04 EP EP04731043A patent/EP1625617A1/en not_active Withdrawn
- 2004-05-04 CN CNA2004800141131A patent/CN1795552A/zh active Pending
- 2004-05-04 WO PCT/GB2004/001933 patent/WO2004105121A1/en active Application Filing
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CN105762083A (zh) * | 2007-12-31 | 2016-07-13 | 英特尔公司 | 为细线和空间封装应用形成高密度金属布线的方法及由此形成的结构 |
CN105762083B (zh) * | 2007-12-31 | 2020-01-14 | 英特尔公司 | 为细线和空间封装应用形成高密度金属布线的方法及由此形成的结构 |
CN102543852A (zh) * | 2011-12-27 | 2012-07-04 | 格科微电子(上海)有限公司 | 金属互连结构及其制作方法 |
CN102543852B (zh) * | 2011-12-27 | 2014-07-16 | 格科微电子(上海)有限公司 | 金属互连结构及其制作方法 |
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US6713835B1 (en) | 2004-03-30 |
TW200509263A (en) | 2005-03-01 |
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TWI284944B (en) | 2007-08-01 |
KR20060015515A (ko) | 2006-02-17 |
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