CN105762083A - 为细线和空间封装应用形成高密度金属布线的方法及由此形成的结构 - Google Patents
为细线和空间封装应用形成高密度金属布线的方法及由此形成的结构 Download PDFInfo
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Abstract
描述形成微电子装置结构的方法。那些方法可包括:形成通过积聚结构与设置在积聚结构上的光敏材料的至少一个开口,其中积聚结构包括封装衬底的一部分;用含金属纳米胶填充至少一个开口;以及烧结含金属纳米胶,以在至少一个开口中形成整体性质金属结构。
Description
发明背景
微电子封装设计正朝愈加更细线路发展,以便满足更大功能性和更高速度的要求。这种趋势对高密度印刷电路板(PCB)和封装衬底提出增加的要求。使用现有布线技术来扩展常规封装积聚(buildup)工艺(process)以满足更细线路尺寸在封装制造中产生了瓶颈。
附图说明
虽然本说明书以具体指出并明确主张被认为是本发明的权利要求书来结束,但是通过结合附图阅读以下对本发明的描述,本发明的优点可更易于确定,附图中:
图1a-1h表示根据本发明实施例的结构。
图2a-2b表示根据本发明实施例的结构。
图3a-3c表示根据本发明实施例的结构。
图4a-4c表示根据本发明实施例的结构。
图5表示根据本发明实施例的***。
具体实施方式
在以下具体实施方式中,以附图为参照,附图以说明方式示出可实施本发明的具体实施例。充分详细地描述这些实施例,使本领域技术人员能够实施本发明。要理解,本发明的各个实施例虽然不同,但不一定相互排斥。例如,在不脱离本发明精神和范围的情况下,本文中结合一个实施例所述的具体功能、结构或特性可在其它实施例中实现。另外要理解,在不脱离本发明精神和范围的情况下,可修改每个所公开实施例中各个要素的位置或布置。因此,以下详细描述不是限制性的,本发明的范围仅由适当解释的随附权利要求书以及授权给权利要求书的全部等效范围定义。附图中,同样的标号在若干视图中表示相同或相似的功能性。
描述形成微电子结构的方法。那些方法可包括:形成通过积聚结构以及设置在积聚结构上的光敏材料的至少一个开口,其中积聚结构包括封装衬底的一部分;用含金属纳米胶填充该至少一个开口;以及烧结含金属纳米胶,以在该至少一个开口中形成整体性质金属结构。
例如,本发明的方法实现供封装应用中使用的细线/空间布线的制造。
例如,图1a-1h示出形成微电子结构的方法、例如用于形成封装结构的部分的方法的实施例。图1a示出封装结构100一部分的截面(在一个实施例中,封装衬底可包括有机衬底)。封装衬底100可例如包括诸如光致抗蚀剂材料的光敏材料102、积聚材料104(例如聚合物材料)和核心材料106。可使用其它聚合物材料来代替光致抗蚀剂,只要可通过适当的化学制品/工艺将它从积聚材料104中选择性地去除。封装衬底100还可包括至少一个通孔结构108和至少一个线结构110,它在一些实施例中可包括例如封装衬底100中导电通孔和导电布线的导电互连结构。
至少一个开口112a、112b可在光敏材料102和积聚材料104中/通过光敏材料102和积聚材料104形成。在一个实施例中,至少一个开口112a可包括可使触点111暴露于至少一个通孔结构108的通孔触点开口,并且至少一个开口112b可包括可包含到至少一个线结构110的触点113的细导电线开口。在一些实施例中,至少一个开口112a、112b可通过利用激光消融工艺和例如纳米压印工艺的压印工艺中至少之一来形成。
在一个实施例中,纳米压印工具314可用于形成通过光敏材料302和积聚材料304一部分的至少一个开口312a(图3a-3b)。然后,可利用激光消融工艺316来通过光敏材料302和积聚材料304形成到至少一个线结构310的至少一个开口312b,其中可暴露到至少一个线结构310的触点313(图3c)。在形成至少一个开口312b的激光消融工艺316期间,通过去除积聚材料304的剩余部分以使到至少一个通孔结构308的触点311暴露,也可完成/形成至少一个开口312a。
根据具体应用,光敏材料302和/或积聚材料304的厚度可改变。例如,如果难以同时制作通过光敏材料302和积聚材料304的压印,则可仅对光敏材料302执行纳米压印,之后跟随积聚材料304的激光消融。
在另一实施例中,第一激光消融工艺416a可用于形成通过光敏材料402和积聚材料404一部分的至少一个开口412a的一部分(图4a-4b)。然后,可利用第二激光消融工艺416b形成通过光敏材料402和积聚材料404二者的至少一个开口412b,其中可暴露到至少一个线结构410的触点413(图4c)。在形成至少一个开口412b的第二激光消融工艺416b期间,通过去除积聚材料404的剩余部分以使到至少一个通孔结构408的触点411暴露,也可完成/形成至少一个开口412a。
在形成至少一个开口112a、112b(又参见图1c)之后,可用含金属纳米胶118填充至少一个开口112a、112b。在一个实施例中,可通过利用挤压技术和/或丝网印刷(screenprinting)技术,用含金属纳米胶118填充至少一个开口112a、112b。在一些实施例中,含金属纳米胶118可包括可包含纳米大小金属粒子的金属纳米胶。
在一个实施例中,含金属纳米胶118可包括银、金、锡和铜纳米粒子中至少之一。在一些实施例中,任何类型的含金属纳米胶可用于填充至少一个开口112a、112b,其可包括产生纳米大小粒子的能力。例如,碳纳米管(CNT)和金属纳米胶混合胶也可用于产生金属和CNT合成结构、例如导线(wire)结构,其中在执行后续烧结工艺之后具有改进的电气性质和机械性质,本文将要进行描述。
在一个实施例中,金属纳米粒子可覆盖有分散剂、反应速率控制试剂以及例如溶剂的某些添加剂以控制粘度。在一些实施例中,可利用例如模版印刷(stencilprinting)和/或喷墨印刷的方法来分配溶剂。在一个实施例中,分散剂可包括链烷酸或胺化合物,并且可用于减小纳米金属粒子的表面张力能量。在一些实施例中,反应速率控制试剂在室温下会是稳定的而不会遇到活化,并且例如可包括胺化合物。
在一个实施例中,含金属纳米胶118的纳米大小金属粒子可包括可经过后续烧结工艺的金属。在一个实施例中,纳米大小金属粒子可覆盖有分散剂,使得它们包括精细分布而在含金属纳米胶118中没有实质凝聚。在一个实施例中,含金属纳米胶118可包括可包含大约5nm的平均直径的铜纳米粒子。纳米大小金属粒子的直径可根据具体应用而改变,但在一些实施例中,可包括大约10nm或以下。
含金属纳米胶118可经过烧结工艺120。例如烧结温度和时间条件的具体烧结工艺条件120可根据纳米胶材料的具体类型进行控制。在一个实施例中,在升高但低于烧结温度的温度下,反应速率控制试剂通过升温而变成活化,并可开始与含金属纳米胶118中的分散剂起反应,且可从纳米金属粒子去除分散剂。
这可引起相互凝聚的纳米金属粒子,并且也会在纳米金属粒子之间发生互扩散增长,以减小其表面张力能量。随着温度增加到烧结温度,纳米大小金属粒子可从纳米大小粒子119转换,以便形成整体性质金属结构122(图1d,示出在经过烧结工艺120之后未经转换的含金属纳米胶(a)和经转换的含金属纳米胶(b)的一部分)。在一个实施例中,含金属纳米胶的烧结温度可包括比整体性质金属结构的熔融温度更低的温度。在一个实施例中,整体性质金属结构122包括很少到没有的有机材料和很少到没有的纳米大小金属粒子。
因此,含金属纳米胶118中基于有机物的(organicbased)材料(分散剂、反应控制试剂、添加剂)可在烧结工艺120期间去除,以便形成整体性质金属结构122。为了有效去除基于有机物的材料,可利用各种烧结工艺。在一个实施例中,可采用空气诱导烧结工艺,其中可应用大约100摄氏度至大约280摄氏度之间的烧结温度来烧结含银和/或金的纳米胶118。
空气中存在的氧可扩散到纳米胶118中,并且可易于与待蒸发的有机物起反应,由此形成整体性质金属结构122。在铜和/或锡纳米胶的情况下,可控制金属纳米粒子的氧化。在一个实施例中,可使用还原环境条件(例如Ar-5%H2混合气体、N2甲酸汽相混合气体等)。环境压力也可以是要控制以及控制烧结工艺时间和温度以增强烧结质量的关键烧结因素中之一。在一个实施例中,烧结时间可包括大约60分钟或以下。
在一个实施例中,当含金属纳米胶118转换成整体性质金属结构122(图1e)时,可发生容积变化124。在一些实施例中,整体性质金属结构122在转换时可遭受容积的减小。可从积聚材料104去除光敏材料102(图1f),并且根据特定应用(图1g),附加积聚材料104a可形成在积聚材料104上,以便形成封装结构123。
在一个实施例中,整体性质金属结构122可包括导电结构,例如微电子封装应用中的导电导线(图1h)。在一个实施例中,相邻整体性质金属结构122a、122b、122c可包括线宽126和相邻整体性质金属结构之间、例如整体性质金属结构122a与122b之间的线间距128。在一个实施例中,线宽126可包括大约10微米或以下,并且线间距可包括大约10微米或以下。
因此,实现制造小于大约10/10微米的细线/空间金属导线的能力。也实现具有高纵横比的金属导线的制造。在高密度封装衬底和/或母板的常规积聚工艺中,小于大约10/10微米的细线/空间导电布线因为在导线图案化期间通过化学蚀刻方法的电镀金属(特别是铜)的均匀直接制造中由于蚀刻副作用遇到的困难而面临关键难题。本发明的各个实施例基于使用含金属纳米胶的镶嵌技术对细线/空间应用、例如在高密度封装衬底或母板制造中允许金属导线的制造,而无需已沉积金属的化学机械抛光(CMP)和直接图案蚀刻。
在另一实施例中,衬底200(例如与图1c的衬底100相似)可包括光敏材料202、积聚材料204和含金属胶218。在衬底200中填充可提供到衬底200中导电结构的连接的开口之前,(例如但不限于通孔结构和线结构),疏水材料209可应用到光敏材料202的顶表面。疏水材料209可阻止含金属纳米胶218在含金属纳米胶218被填充到开口(未示出)、例如图1b的至少一个开口112中之后仍然残留在光敏材料202表面。
在一个实施例中,含金属纳米胶218在被挤压到开口中之后可仍然残留在光敏材料202顶表面。光敏材料202顶表面上的含金属纳米胶218则可易于去除(图2b),同时含金属纳米胶218残留在填充开口、例如在线腔和过孔中,并且发生表面张力的减小。
本发明的实施例提供许多优点。实现以取得高纵横比的能力交付小于大约10/10微米的细线/空间金属导线。描述与常规积聚工艺相比通过使用含金属纳米胶的简单工艺。根据本发明实施例,通过使用允许所制造金属导线的高纵横比的沟槽形成技术、例如镶嵌技术,可预期显著的质量提高。通过消除处理期间的CMP步骤,以及通过消除对化学蚀刻、电镀、籽晶溅射和电镀工艺的需要,可实现成本降低。
图5是示出能够与用于制造微电子结构、例如图1g中封装结构123的方法配合操作的***500的简图。要理解,当前实施例仅仅是其中可使用本发明中封装结构的许多可能***中之一。
在***500中,封装结构524可通过I/O总线508在通信上耦合到印刷电路板(PCB)518。封装结构524的通信耦合可通过物理部件、例如通过使用将封装结构524安装到PCB518的封装和/或插座连接(例如通过使用芯片封装、内插器和/或连接盘栅格阵列插座)来建立。封装结构524还可通过各种无线部件(例如没有使用到PCB的物理连接)在通信上耦合到PCB518,如本领域众所周知一样。
***500可包括例如处理器的计算装置502以及通过处理器总线505在通信上相互耦合的高速缓冲存储器504。处理器总线505和I/O总线508可通过主桥506进行桥接。通信上耦合到I/O总线508并且还耦合到封装结构524的可以是主存储器512。主存储器512的示例可包括但不限于静态随机存取存储器(SRAM)和/或动态随机存取存储器(DRAM)和/或某些其它状态保存介质。***500还可包括图形协处理器513,但是,将图形协处理器513结合到***500中对***500的操作不是必需的。耦合到I/O总线508的还可以是例如显示装置514、大容量存储装置520以及键盘和指点装置522。
这些要素执行其在本领域中众所周知的常规功能。具体来说,大容量存储装置520可用于为根据本发明实施例形成封装结构的方法的可执行指令提供长期存储,而主存储器512可用于在由计算装置502的执行期间短期存储根据本发明实施例形成封装结构的方法的可执行指令。另外,指令可存储在或者以其它方式关联通信上与***耦合的机器可访问介质,例如光盘只读存储器(CD-ROM)、数字多功能光盘(DVD)和软盘、载波和/或其它传播信号。在一个实施例中,主存储器512可向计算装置502(例如,其可以是处理器)提供可执行指令以供执行。
虽然前面的描述已经指定在本发明方法中使用的某些步骤和材料,但是本领域技术人员将领会,可进行许多修改和替换。相应地,预计所有这类修改、变更、替换和添加被认为落入随附权利要求书所定义的本发明精神及范围之内。另外要领会,微电子封装结构的某些方面在本领域中是众所周知的。因此要领会,本文所提供的附图仅示出涉及本发明实施的示范微电子封装结构的部分。因此,本发明并不局限于本文所述的结构。
Claims (23)
1.一种形成微电子结构的方法,包括:
形成通过积聚材料与设置在所述积聚材料上的光敏材料的至少一个开口,其中所述积聚材料包括封装衬底的一部分,其中所述至少一个开口包括通过所述光敏材料并且进入所述积聚材料中的线部分和在所述积聚材料中的通孔触点部分,其中所述线部分比所述通孔触点部分宽;
用含金属纳米胶填充所述至少一个开口;以及
烧结所述含金属纳米胶,以在所述至少一个开口中形成整体性质金属结构。
2.如权利要求1所述的方法,还包括:其中所述至少一个开口通过利用纳米压印和激光消融中至少之一来形成。
3.如权利要求1所述的方法,还包括:其中烧结温度包括在不到60分钟小于280摄氏度。
4.一种形成微电子结构的方法,包括:
形成通过光敏材料和积聚材料的至少一个开口,其中所述光敏材料设置在所述积聚材料上,以及其中所述积聚材料包括封装衬底的一部分,其中所述至少一个开口包括通过所述光敏材料并且进入所述积聚材料中的线部分和在所述积聚材料中的通孔触点部分,其中所述线部分比所述通孔触点部分宽;
用含金属纳米胶填充所述至少一个开口;以及
烧结所述含金属纳米胶,以在所述至少一个开口中形成整体性质金属结构。
5.如权利要求4所述的方法,还包括:其中所述封装衬底包括高密度封装衬底和母板中至少之一。
6.如权利要求4所述的方法,还包括:其中所述含金属纳米胶包括纳米大小金属粒子、分散剂、反应速率控制试剂和添加剂。
7.如权利要求6所述的方法,还包括:其中所述含金属纳米胶包括包含直径6nm或以下的铜纳米粒子,并且其中所述分散剂包括链烷酸和胺化合物中至少之一,并且其中所述反应速率控制试剂包括胺化合物,并且其中所述添加剂包括所述含金属纳米胶的溶剂。
8.如权利要求4所述的方法,还包括:其中烧结温度包括在60分钟或以下小于280摄氏度。
9.如权利要求8所述的方法,还包括:其中所述含金属纳米胶的烧结温度包括比所述整体性质金属结构的熔融温度更低的温度。
10.如权利要求6所述的方法,还包括:其中所述烧结从所述含金属纳米胶实质去除分散剂、反应速率控制试剂和添加剂,并且其中将所述金属纳米粒子变换成整体性质金属结构。
11.如权利要求4所述的方法,还包括:其中用含金属纳米胶填充所述至少一个开口通过使用挤压技术来执行。
12.如权利要求4所述的方法,还包括:其中用含金属纳米胶填充所述至少一个开口通过使用丝网印刷技术来执行。
13.如权利要求4所述的方法,还包括:其中在填充所述至少一个开口之前将疏水材料应用到所述光敏材料。
14.如权利要求4所述的方法,还包括:其中用激光消融形成所述至少一个开口。
15.如权利要求4所述的方法,还包括:其中所述整体性质金属结构包括线宽10微米或以下以及线间距10微米或以下的金属导线结构。
16.一种微电子结构,包括:
第一导电导线结构,设置在积聚材料中,其中所述积聚材料包括封装衬底的一部分;
第二导电导线结构,与所述第一导电导线结构相邻设置,
其中,所述第一和第二导电导线结构中的每一个通过形成通过所述积聚材料和设置在所述积聚材料上的光敏材料的开口而形成,其中所述至少一个开口包括通过所述光敏材料并且进入所述积聚材料中的线部分和在所述积聚材料中的通孔触点部分,其中所述线部分比所述通孔触点部分宽。
17.如权利要求16所述的结构,还包括:其中所述第一和第二导电导线结构包括包含整体金属性质的金属。
18.如权利要求16所述的结构,还包括:其中所述第一和第二导电导线结构包括金属导线结构。
19.如权利要求16所述的结构,还包括:其中所述封装衬底包括高密度封装衬底和母板中至少之一。
20.如权利要求17所述的结构,还包括:与所述第一和第二导电导线结构中至少之一相邻的通孔结构,其中所述通孔结构包括与所述第一和第二导电导线结构实质相同的材料。
21.如权利要求16所述的结构,还包括:其中所述第一和第二导电导线结构中至少之一包括铜、银、锡和金中至少之一。
22.一种微电子结构,包括:
第一导电导线结构,设置在积聚材料中,其中所述积聚材料包括封装衬底的一部分;以及
第二导电导线结构,与所述第一互连结构相邻设置,
其中,所述第一和第二导电导线结构中的每一个通过形成通过所述积聚材料和设置在所述积聚材料上的光敏材料的开口而形成,其中所述至少一个开口包括通过所述光敏材料并且进入所述积聚材料中的线部分和在所述积聚材料中的通孔触点部分,其中所述线部分比所述通孔触点部分宽。
23.一种微电子***,所述***包括:
如权利要求22所述的微电子结构;
总线,通信上耦合到所述第一和第二导电导线结构;以及
DRAM,通信上耦合到所述总线。
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US11/968,116 US20170004978A1 (en) | 2007-12-31 | 2007-12-31 | Methods of forming high density metal wiring for fine line and space packaging applications and structures formed thereby |
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CN111250715A (zh) * | 2020-03-06 | 2020-06-09 | 北京航空航天大学 | 一种基于粉末烧结工艺的三维mems结构金属填充方法 |
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US10485091B2 (en) * | 2016-11-29 | 2019-11-19 | Nxp Usa, Inc. | Microelectronic modules with sinter-bonded heat dissipation structures and methods for the fabrication thereof |
US10104759B2 (en) | 2016-11-29 | 2018-10-16 | Nxp Usa, Inc. | Microelectronic modules with sinter-bonded heat dissipation structures and methods for the fabrication thereof |
US9865527B1 (en) | 2016-12-22 | 2018-01-09 | Texas Instruments Incorporated | Packaged semiconductor device having nanoparticle adhesion layer patterned into zones of electrical conductance and insulation |
US9941194B1 (en) * | 2017-02-21 | 2018-04-10 | Texas Instruments Incorporated | Packaged semiconductor device having patterned conductance dual-material nanoparticle adhesion layer |
CN112786531B (zh) * | 2020-12-31 | 2022-04-19 | 广东工业大学 | 一种基于纳米金属的深孔互连结构制备方法 |
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SG189728A1 (en) | 2013-05-31 |
CN105762083B (zh) | 2020-01-14 |
US20170004978A1 (en) | 2017-01-05 |
TWI515849B (zh) | 2016-01-01 |
KR101235510B1 (ko) | 2013-02-20 |
WO2009088592A1 (en) | 2009-07-16 |
KR20100094598A (ko) | 2010-08-26 |
CN101911293A (zh) | 2010-12-08 |
TW200945524A (en) | 2009-11-01 |
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