CN2508464Y - Sampling interface circuit structure using switch capacitance technique - Google Patents
Sampling interface circuit structure using switch capacitance technique Download PDFInfo
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- CN2508464Y CN2508464Y CN 01254270 CN01254270U CN2508464Y CN 2508464 Y CN2508464 Y CN 2508464Y CN 01254270 CN01254270 CN 01254270 CN 01254270 U CN01254270 U CN 01254270U CN 2508464 Y CN2508464 Y CN 2508464Y
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Abstract
The utility model relates to an interface circuit used for sampling the analog signal by utilizing the switch-capacitance technology. The prior art has no problem when being used for sampling the input analog signal of single pole, but in the actual application, the input signal can be double polar, and in the modern CMOS integrated circuit, because of cost and other reasons, generally a single power supply is used for power supply. The utility model aims at providing a switch-capacitance circuit structure for solving the problems without changing the power supply way. The bipolar input voltage can be allowed in the circuit structure provided by the utility model. The circuit comprises a first switch tube, a controller, a second switch tube and a bias circuit, wherein the input terminal of the first switch tube is connected with the input signal, and the output terminal is connected with a sampling capacitance, and the controlling terminal is controlled by a controller; and the controller is used for generating the clock controlling signal of a sampling phase and a charge transfer phase, and the clock controlling signal adopts a single pole voltage signal; the input terminal of the second switch tube is connected with the output terminal of the first switch tube and the sampling capacitance, the output terminal is connected with a reference voltage (usually the ground), and the controlling terminal is controlled by a controller; and the bias circuit is used for providing appropriate bias voltage for the controlling terminals of the switch tubes to ensure the terminals operate in an on-state, and the on-state can allow the bipolar voltage in a certain range to get through.
Description
Technical field
The utility model is a kind of structure of utilizing switched capacitor technique to the interface circuit of analog signal sampling.
Background technology
Switched-capacitor circuit is widely used in the analog to digital converter (ADC).In analog to digital converter, need an interface circuit to be used for to the sampling of input analog signal, to offer the change-over circuit of back.Usually this task can be finished by a switched-capacitor circuit, and Fig. 1 is exactly a concrete realization circuit.Switched-capacitor circuit shown in Figure 1 comprises a sampling capacitance Cs and four switching tube m1, m2, and m3 and m4 output on the node n3.Fig. 2 is the control signal Phi1 of these four switching tubes, the waveform of Phi2.The work of circuit can be divided into two stages: sampling is shifted mutually with electric charge mutually.In the sampling phase, control signal Phi2 makes m1 and m3 conducting, and Phi1 turn-offs m2 and m4.Q=Cs is just arranged in the finish time of sampling phase like this
*The Charge Storage of Vin size is on sampling capacitance Cs, and wherein Vin is an input analog voltage.Shift phase at electric charge, control signal Phi2 turn-offs m1 and m3, and Phi1 makes m2 and m4 conducting, and sampling capacitance Cs goes up the electric charge that stores and just transfers on the node n3.
The circuit of Fig. 1 adopts 0 to 5V unipolarity power supply power supply, and the simulation ground VREF of circuit generally is half of supply voltage, i.e. 2.5V.It is no problem that this circuit is used for to unipolar input analog signal sampling, but input signal might be ambipolar in actual applications, both might be positive voltage, also might be negative voltage.If make circuit into dual power supply in this case, still can operate as normal.But in modern CMOS integrated circuit,, therefore just must adopt other method to solve this problem because cost and other generally all adopt single power supply.
Summary of the invention
The purpose of this utility model is to provide a kind of circuit structure of the switching capacity that does not change supply power mode and address the above problem.
The circuit structure that the utility model proposes allows ambipolar input voltage, and circuit comprises: first switching tube, and its input connects input signal, and output connects sampling capacitance, and control end is controlled by controller; A controller is used for producing sampling phase and electric charge transfer clock control signal mutually.This clock control signal is unipolar voltage signal; Second switching tube, its input connects first output end of switching tube and sampling capacitance, and output connects reference voltage (normally), and control end is controlled by controller; Biasing circuit offers the suitable bias voltage of switching tube so that they are operated in conducting state when sampling and electric charge shift, this conducting state can allow the interior bipolar voltage of certain limit be able to by.
The sampling capacitance of the utility model circuit is store charge on sampling phase time electric capacity, and the quantity of electric charge of storage and the signal voltage of input are proportional, shifts phase time at electric charge the store charge on the electric capacity is transferred to output.The characteristics of this circuit are that the power supply of other electronic components in incoming signal level and the circuit can be independently, and it is bipolar voltage that input signal allows, and can be higher or lower than ground level within the specific limits.
The utility model also has switching tube, control circuit and biasing circuit except the single power supply circuit, their circuit structure is:
First switching tube, its input termination input analog signal, output termination sampling capacitance, control termination control signal;
A control circuit, its produces the not control clock signal of crossover of two-phase, and this clock signal to another voltage, is used for the operating state of control interface circuit by a change in voltage, and operating state has two kinds: sampling phase and clock are mutually; The variation of this clock signal is unipolar, therefore can produce with the single power supply system;
First biasing circuit, it is used for to the control grid biasing of first switching tube; Biasing circuit has a level translation electric capacity, and this electric capacity is connected between clock control signal and the switch controlled end; Shift phase time at electric charge and on first control end of switching tube, store an initial voltage, when circuit working state shifts phase change to the sampling phase time by electric charge, level translation electric capacity can be with the suitable value of the level translation on first switch controlled end, and the input analog signal that makes the switching tube conducting also can allow to change is within the specific limits transmitted by switching tube smoothly.
Second switching tube, its input termination sampling capacitance and first output end of switching tube, the common-mode voltage of output termination analog input signal, control termination control signal.
Second biasing circuit, it is used for to the control grid biasing of second switching tube; Biasing circuit has a level translation electric capacity, and this electric capacity is connected between clock control signal and the switch controlled end; On first control end of switching tube, store an initial voltage at the sampling phase time, when circuit working state shifts phase time by the sampling phase change to electric charge, level translation electric capacity can be with the suitable value of the level translation on second switch controlled end, and the input analog signal that makes the switching tube conducting also can allow to change is within the specific limits transmitted by switching tube smoothly.
Biasing circuit of the present utility model has a diode, the positive termination switch controlled of this diode end, and negative terminal connects input signal.This diode be used for electric charge shift phase time with the control end of switching tube clamping on the current potential of a high threshold voltage than input signal, on-off switching tube.This level also can be used as the initial voltage that level translation electric capacity carries out level translation at the sampling phase time.
Biasing circuit of the present utility model also has two diodes in addition except an above-mentioned diode is arranged, their positive termination input signals in series connection back, and negative terminal connects the switch controlled end.These two diodes are used in sampling phase time and the effect of joining together of level translation electric capacity the control end of switching tube clamping on the current potential than low two threshold voltages of input signal, being made the switching tube conducting.
The forward voltage drop sum of above-mentioned three diodes is less than the amplitude of variation of switching tube clock control signal.
The input of the output of first switching tube in the utility model circuit structure, second switching tube all is connected with first pole plate of sampling capacitance; The the 3rd, the 4th switching tube arranged in the circuit, second pole plate of the 3rd switching tube input termination sampling capacitance wherein, the median of output termination supply voltage, control end is the clock signal control that is produced by control circuit; Second pole plate of the input termination sampling capacitance of the 4th switching tube, output is the output of this interface circuit, the clock signal control that control end is produced by control circuit.Clock control signal makes the 3rd switching tube in the conducting of sampling phase time, and electric charge shifts phase time to be ended; Make the 4th switching tube shift the phase time conducting at electric charge, the sampling phase time ends.
The structures such as switching tube, controller, biasing circuit of utilizing the utility model have realized that a kind of supply power mode that do not change makes the interface circuit that analog signal is sampled can gather bipolar signal.The utility model circuit is reasonable, simple in structure, cost is not high, be easy to realization.After this circuit structure uses, obtain good result in the power measurement chip.
Description of drawings
Fig. 1 is traditional switching capacity interface circuit;
Fig. 2 is the sequential chart of switch controlled signal in Fig. 1 circuit;
Fig. 3 is the switching capacity interface circuit that the present invention proposes;
Fig. 4 is the sequential chart of switch controlled signal in the circuit shown in Figure 3.
Embodiment
Example is exactly the switching capacity interface circuit that the utility model proposes between input analog signal VIN and output node N3 as shown in Figure 3.Input analog signal VIN fluctuates up and down at ground level (0V), in this circuit the excursion of VIN can for-1V～+ 1V.
Entire circuit comprises: the switching tube 1,2 that the pMOS transistor is realized, and the input termination input analog signal Vin of switching tube 1, output termination sampling capacitance Cs, control end (grid) is controlled jointly by control circuit and biasing circuit; The output and the sampling capacitance of the input termination switch pipe 1 of switching tube 2, the common-mode voltage of output termination input analog signal is ground herein, control end (grid) is controlled jointly by control circuit and biasing circuit.Control circuit 10 is used to provide not crossover clock signal Phi1 of the necessary two-phase of switched-capacitor circuit work, Phi2, as shown in Figure 4.Phi1, the excursion of Phi2 all be 0V to 5V, therefore can power with unipolar power supply.Phi1, Phi2 not only can be used as the clock signal of this interface circuit, also can be used as the clock of other switched-capacitor circuits in the system.Biasing circuit 12,15 is used for adding suitable bias voltage to the control end of switching tube 1 and 2 (being grid), make switching tube 1 sampling be on good terms transmission-1V successfully～+ voltage of 1V, switching tube 2 shifts to be on good terms at electric charge ground level (0V) nondestructively is delivered to the N1 point.These two biasing circuit functions are identical, are the example explanation with 12 below.Biasing circuit 12 has comprised 5, one capacitance Cb1 of an inverter, three diodes, and the positive termination N4 point of diode 6 wherein, negative terminal meets Vin, the positive termination Vin in diode 7,8 series connection backs, negative terminal meets N4.The effect of inverter 5 is with the negative 0V that jumps to of control clock signal anti-phase the become 5V of input from the 0V positive transition to 5V.The clock signal of this negative saltus step and capacitor C b combine the effect that can play level translation, and its waveform can be referring to Fig. 4.Diode the 6,7, the 8th, clamp diode, the control grid with switching tube 1 after the clock saltus step causes level translation is clamped to the signal specific of a certain suitable potential with transmission requirement.
The operation principle of foregoing circuit is as follows: the forward voltage drop of establishing diode is Vth, Vth ≈ 1V.Shift phase at electric charge, the voltage on the P1 pole plate of capacitor C b1 is+5V, because input voltage vin＜5-Vth, so diode 6 is positively biased, and because its clamping action makes the P2 polar plate voltage of Cb1 remain on Vin+Vth.This voltage also is the control end voltage of switching tube 1.Because switching tube 1 is a pMOS pipe, add that at grid it turn-offs behind the voltage of Vin+Vth.In the sampling phase, the P1 polar plate voltage of Cb1 drops to 0V from 5V, because the voltage at electric capacity two ends can not suddenly change, so the voltage of P2 pole plate is also with decline 5V.The voltage that shifts on the phase node N4 at previous electric charge is Vin+Vth, becomes Vin+Vth-5 now.This voltage ratio Vin hangs down 5-Vth, therefore this moment diode 7,8 positively biaseds, the voltage that their clamping action finally makes N4 order remains on Vin-2Vth.According to the transmission characteristic of pMOS pipe as can be known, at this moment Vin can waltz through switching tube 1 and passes on the sampling capacitance Cs.It should be noted that the forward voltage drop sum of three diodes 6,7,8 can not surpass the amplitude of variation of clock signal Phi2, be 5V herein, can not play clamping action otherwise shift phase change at circuit from electric charge to sampling phase time diode.
Also comprise another switching tube 2 and biasing circuit 15 thereof in the circuit.Its structure is identical with 1.Same analysis can draw, in the sampling phase, and 2 control end voltage, promptly the N5 point voltage is Vth, turn-off this moment 2; Shift phase at electric charge, the N5 point voltage becomes :-2Vth, and switching tube 2 conductings, ground level can nondestructively be transferred on the sampling capacitance Cs by 2.
Other switching tube is 3,4 in the circuit, and the input of switching tube 3 is the simulation ground of system, generally is half of power supply, is 2.5V herein; Output connects the other end N2 point of sampling capacitance, control termination Phi2.The input of switching tube 4 is N2 points, and output meets integrating capacitor Cint (N3 point), control termination Phi1.These two switching tubes are realized with the nMOS pipe.We just can know the course of work of entire circuit like this: in the sampling phase, and switching tube 1 and 3 conductings, 2 and 4 end, and the electric charge that accumulates on the sampling capacitance Cs in the finish time of sampling phase is: Q=Cs
*(Vin-2.5); Shift phase at electric charge, switching tube 1 and 3 ends, 2 and 4 conductings, and the Q electric charge is transferred on the node N3.In fact because N3 connects is the input of amplifier, these electric charges will finally be transferred to output Vout by integrating capacitor Cint.
Claims (4)
1, a kind of structure of utilizing the sampling interface circuit of switched capacitor technique, mainly contain sampling capacitance, the single power supply circuit, the switch controlled circuit, biasing circuit is characterized in that this circuit has a sampling capacitance, store charge on sampling phase time electric capacity, the quantity of electric charge that stores and the signal voltage of input are proportional, shift phase time at electric charge the store charge on the electric capacity is transferred to output;
The single power supply circuit;
First switching tube, its input termination input analog signal, output termination sampling capacitance, control termination control signal;
A control circuit, its produces the not control clock signal of crossover of two-phase, and this clock signal to another voltage, is used for the operating state of control interface circuit by a change in voltage, and operating state has two kinds: sampling phase and clock are mutually; The variation of this clock signal is unipolar, therefore can produce with the single power supply system;
First biasing circuit, it is used for to the control grid biasing of first switching tube; Biasing circuit has a level translation electric capacity, and this electric capacity is connected between clock control signal and the switch controlled end;
Second switching tube, its input termination sampling capacitance and first output end of switching tube, the common-mode voltage of output termination analog input signal, control termination control signal;
Second biasing circuit, it is used for to the control grid biasing of second switching tube; Biasing circuit has a level translation electric capacity, and this electric capacity is connected between clock control signal and the switch controlled end;
2, the structure of utilizing the sampling interface circuit of switched capacitor technique according to claim 1 is characterized in that the biasing circuit in the circuit has a diode, the positive termination switch controlled of this diode end, and negative terminal connects input signal.
3, the structure of utilizing the sampling interface circuit of switched capacitor technique according to claim 2 is characterized in that biasing circuit has two diodes in addition, their positive termination input signals in series connection back, and negative terminal connects the switch controlled end.
4, the structure of utilizing the sampling interface circuit of switched capacitor technique according to claim 1 is characterized in that the input of the output of first switching tube in the circuit structure, second switching tube all is connected with first pole plate of sampling capacitance; The the 3rd, the 4th switching tube arranged in the circuit, second pole plate of the 3rd switching tube input termination sampling capacitance wherein, the median of output termination supply voltage, control end is the clock signal control that is produced by control circuit; Second pole plate of the input termination sampling capacitance of the 4th switching tube, output is the output of this interface circuit, the clock signal control that control end is produced by control circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01254270 CN2508464Y (en) | 2001-10-18 | 2001-10-18 | Sampling interface circuit structure using switch capacitance technique |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01254270 CN2508464Y (en) | 2001-10-18 | 2001-10-18 | Sampling interface circuit structure using switch capacitance technique |
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| CN2508464Y true CN2508464Y (en) | 2002-08-28 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 01254270 Expired - Fee Related CN2508464Y (en) | 2001-10-18 | 2001-10-18 | Sampling interface circuit structure using switch capacitance technique |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7339415B2 (en) | 2003-12-10 | 2008-03-04 | Infineon Technologies Ag | SC circuit arrangement |
| CN100418301C (en) * | 2005-03-04 | 2008-09-10 | 清华大学 | Integrator of power supply by AC power supply in switch condenser circuit |
| CN102291113A (en) * | 2010-06-18 | 2011-12-21 | 联阳半导体股份有限公司 | Capacitive interface circuit |
| CN101770811B (en) * | 2009-12-29 | 2012-07-25 | 浙江大学 | Sampling hold circuit of clock-controlled floating-gate MOS tube based on threshold cancellation function |
-
2001
- 2001-10-18 CN CN 01254270 patent/CN2508464Y/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7339415B2 (en) | 2003-12-10 | 2008-03-04 | Infineon Technologies Ag | SC circuit arrangement |
| CN100454761C (en) * | 2003-12-10 | 2009-01-21 | 因芬尼昂技术股份公司 | SC circuit structure |
| CN100418301C (en) * | 2005-03-04 | 2008-09-10 | 清华大学 | Integrator of power supply by AC power supply in switch condenser circuit |
| CN101770811B (en) * | 2009-12-29 | 2012-07-25 | 浙江大学 | Sampling hold circuit of clock-controlled floating-gate MOS tube based on threshold cancellation function |
| CN102291113A (en) * | 2010-06-18 | 2011-12-21 | 联阳半导体股份有限公司 | Capacitive interface circuit |
| CN102291113B (en) * | 2010-06-18 | 2013-07-10 | 联阳半导体股份有限公司 | Capacitive interface circuit |
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Legal Events
| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20020828 Termination date: 20101018 |