CN1599071A - EEPROM cell structures having non-uniform channel-dielectric thickness and methods of making the same - Google Patents
EEPROM cell structures having non-uniform channel-dielectric thickness and methods of making the same Download PDFInfo
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- CN1599071A CN1599071A CNA2004100631378A CN200410063137A CN1599071A CN 1599071 A CN1599071 A CN 1599071A CN A2004100631378 A CNA2004100631378 A CN A2004100631378A CN 200410063137 A CN200410063137 A CN 200410063137A CN 1599071 A CN1599071 A CN 1599071A
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
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- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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Abstract
An EEPROM cell structure, having varied gate-dielectric thickness, can include: a semiconductor substrate; a memory transistor and a select transistor on the substrate; and a floating junction formed in the substrate between the transistors and extending partially underneath the memory transistor; a gate-dielectric layer in the memory transistor, along a lateral direction, being arranged into a tunnel region having thickness Ttunnel and overlying a portion of the floating junction, a near-channel region having thickness Tnear>Ttunnel and located at a side of the tunnel region opposite the select transistor, and a far-channel region having thickness Tfar<Tnear and located at a side of the near-channel-region opposite the tunnel-region. A related method making such an EEPROM cell structure has corresponding steps.
Description
Technical field
The present invention relates to a kind of electrically erasable programmable read-only memory (EEPROM) cell structure and manufacture method thereof with non-uniform channel-dielectric thickness.
Background technology
Electrically Erasable Read Only Memory (EEPROMs) is known.Fig. 1 is the profile of typical EEPROM cellular construction 100, and according to background technology, this structure comprises the 140 and corresponding transistors 142 of selecting of a memory transistor (MTR) on the substrate 101.MTR140 comprises a gate dielectric structure 156, and this structure comprises that a thickness is T
104aAnd T
104zGate-dielectric part 104a and 104z, T wherein
104z＞T
104aAmong Fig. 1, Reference numeral 118a represents an interlayer dielectric.
Floating grid 116a (comprising polysilicon layer (a plurality of)) charge/discharge to MTR140 increases/reduces the threshold voltage (Vth) of MTR140 with respect to rated value.In EEPROM cellular construction 100, with (decreased/increased) threshold voltage (V of an increase/minimizing
Th Decreased, V
Th Increased) or presentation logic 0/1 value conversely.This logical value is stored among the MTR100 and whether is enough to open MTR100 and reflects by the predetermined voltage (Vr) of reading.
As other integrated circuit, ongoing purpose of design is for further highly integrated this EEPROM, particularly realizes by the size that reduces cellular construction.Because channel length L reduces, MTR 140 shows the effect of short channel, and this is that people are undesirable.This background technology distinguishes 149 by anti-breakdown (PTP) that the low doping concentration (P-) with respect to substrate 101 forms highly doped (for example, a P-type) concentration (P+), has remedied this defective.
Summary of the invention
One of embodiments of the invention relate to an EEPROM cellular construction with non-homogeneous gate dielectric thickness.This EEPROM cellular construction can comprise: the semiconductor substrate; Memory transistor on the substrate and one is selected transistor; And in substrate, form between the transistor and partly extend to a floating junction below this memory transistor; Gate dielectric layer in the memory transistor, the edge is horizontal, is arranged to have thickness T
TunnelTunnel (tunnel) district in overlapping with the part of floating junction, a thickness is T
Near＞T
TunneAnd the next door that is set at Close Tunnel is relative with the selection transistor
1Nearly channel region, and a thickness is T
Far＜T
NearAnd the one side that is set at nearly channel layer far away channel region relative with Close Tunnel.
An alternative embodiment of the invention relates to the method that a kind of manufacturing has the EEPROM cellular construction of non-homogeneous gate dielectric thickness.This method can comprise: form a gate-dielectric ground floor on semiconductor substrate, wherein said substrate has respectively corresponding to first of the tunnel of making subsequently, raceway groove far away and nearly channel region, the second and the 3rd zone, this first and the 3rd zone is separated by second area; Optionally remove the ground floor of part on the first and the 3rd zone; On ground floor and substrate-exposing part, form the gate-dielectric second layer; The thickness of the gate dielectric material on the first, the second and the 3rd zone is respectively T
Tunnel, T
NearAnd T
Far, have the T of relation
Near＞T
TunnelAnd T
Near＞T
FarOn the second layer, continue to form extra play corresponding to a transistorized composition; And optionally remove part this first, the second and extra play in order to the memory at definition initial stage with select transistor so that this first, the second and the 3rd zone is set at below the memory transistor.
Specific descriptions other features and advantages of the present invention by following embodiment and accompanying drawing will be more obvious.
Description of drawings
Fig. 1 is the profile of Electrically Erasable Read Only Memory (EEPROM) cellular construction according to background technology.
Other figure is: be used to describe embodiments of the invention and should be interpreted as qualification to its scope.
Fig. 2 is the profile of EEPROM cellular construction according to an embodiment of the invention.
Fig. 3 is a simple explanation of superposing circuit image shown in Figure 2.
Fig. 4 is the explanation of Fig. 2, and it has marked the thickness and the length of selected composition.
Fig. 5 A-5H is the profile in each stage when making the EEPROM cellular construction according to embodiments of the invention.
Embodiment
Fig. 2 is the profile of Electrically Erasable Read Only Memory according to an embodiment of the invention (EEPROM) cellular construction 200.This EEPROM cellular construction 200 is included in such as a memory transistor (MTR) 240 that forms on the such semi-conductive substrate 201 of polysilicon and a corresponding transistor (STR) 242 of selecting.MTR240 and STR242 be, for example, and such as the such field-effect transistor of MOSFETs (mos field effect transistor).As an example will discussing at remainder, can use P-type alloy doped substrate 201; Optionally, also can use N-type alloy.
The district that forms in substrate 201 comprises: field region 202; Drain/source (D/S) district 246 with the STR242 associating; D/S district 248 with the MTR240 associating; One anti-breakdown (PTP) district 249, its concentration higher (for example, P+ is according to the top example of introducing) with respect to substrate 101 the P-type alloys of P-type concentration of dopant lower (P-); And a floating junction 244, it is between MTR240 and STR242 and partly extend to below the MTR240.Floating junction 244 is codope thing drain electrodes (DDD), and it has the zone 228 with respect to zone 206 the N-type concentration of dopant lower (for example, N-is according to the example of introducing above) of N-type concentration of dopant higher (N+).Zone 206 is that floating junction 244 extends to the part below the MTR240, and 228 general zones between MTR240 and STR242, zone.D/ S district 246 and 248 has lightly doped drain (LDD) structure, comprise respectively be positioned at MTR240 and above the STR242 near the zone 231 and 227 of low-doped substrate concentration (for example, N-is according to the example of initial introduction); And the zone 230 and 226 that is positioned near the highly doped substrate concentration N+ the field region 202.
Each MTR240 and STR242 have a bigrid (floating grid and control grid) structure.MTR240 comprises following structure: a gate-dielectric, and for example, silica has 204a, 204b, the structure 256 of 204c and 204d part; Floating grid layer 216a for example, is made of polysilicon; One dielectric medium structure 218a, for example, monoxide-nitride-oxide (ONO) structure; And a control grid layer 220a, for example, constitute by polysilicon.It should be noted that gate-dielectric part 204b is corresponding with the gate-dielectric part 104z of background technology altogether with 204c.What notice simultaneously is, gate- dielectric part 204b and 204c represent the non-uniform thickness of gate dielectric material, yet opposite is the thickness T of the gate-dielectric part 104z of background technology
104zBe uniform.
Gate-dielectric part 204a is positioned on the zone 206 of floating junction 244, and corresponding with the Close Tunnel of MTR240, at first utilizes Fowler-Nordheim (F-N) tunnel effect generation charge/discharge by this Close Tunnel.The F-N tunnel effect is main mechanism, utilizes this mechanism, to floating grid 216a charge/discharge so that increase/minimizing Vth threshold value.Gate- dielectric part 204b and 204c are arranged in the top of substrate 201 channel regions.Equally, gate- dielectric part 204b and 204c can be described to nearly raceway groove and channel part far away because they respectively with tunnel effect district and gate-dielectric part 204a relatively near and away from.Gate-dielectric part 204e is positioned at: on (equally) zone 206; One side at gate-dielectric part 204a is relative with gate-dielectric part 204b; And between gate-dielectric part 204a and STR242.
By it tunnel effect, the thickness T of gate- dielectric part 204b and 204d take place in order to suppress this zone
NearAnd T
EdgeShould compare thickness T
TunnelMuch bigger, that is, be respectively T
Near＞T
TunnelAnd T
Edge＞T
TunnelEqually, thickness T
FarShould compare T
NearMuch smaller, i.e. T
Far＜T
NearThe thickness T of gate-dielectric part 204a
TunnelCan with the thickness T of gate-dielectric part 204c
FarApproximately equate T
Tunnel≈ T
FarFor production efficiency, the thickness T of gate-dielectric part 204d
EdgeThickness T with gate dielectric structure 204e
STRSeparately can with thickness T
NearApproximately equate, i.e. T
Edge≈ T
NearAnd T
STR≈ T
NearAnd, the ratio of thickness
Can be in scope
In.And the ratio of thickness
Can be in scope
In.The lateral dimensions of nearly channel region, L
Near, should be L
Near〉=0.1 μ m is so that the tunnel effect of inhibition and gate-dielectric part 204a respective area.As the length with gate-dielectric part 204d respective edges district also is like this.
STR242 and 204e contrast; One floating grid layer 216b for example, is made of polysilicon; Dielectric medium structure 218b, for example, the ONO structure; And a control grid layer 220b, for example, constitute by polysilicon.With respect to gate dielectric structure 256 and 204e, item number 216a/b-220a/b can be described as other compositions that expression is typically arrived seen in field-effect transistor, and for briefly, can be used as extra play 222a/b and be grouped together in together respectively.
In expansion process of the present invention, its physical property is familiar with and has been determined to the following problem in the background technology.Before using PTP district 149, usually one 1.8 volts the voltage Vr that reads is added on the EEPROM cellular construction 100.According to the use in background technology PTP district 149 without exception with V
Th DecreasedAnd V
Th IncreasedUpwards Δ V is measured in one of change/increase
PTPTherefore, exemplary allocations (Vthdecreased+ Δ VPTP) i { (Vthdecreased+ Δ VPTP) i} value comprises that is now gone up a scope { Vth (i) decreased (+) }, and it has than reading the big value of voltage.No matter an example with MTR140 of Vthdecreased (+) has identical logical value be interpreted into always and the logical value of actual storage, because V
Th Decreased (+)＞Vr, this is a problem.A simple solution to this problem is by change/increase Δ V that Vr is made progress accordingly
PTPCompensate V
r Simplistic=V
r+ Δ V
PTPBut this simple compensation has increased the consumption figure of power supply equally accordingly, and this also is a problem.Be used at EEPROM cellular construction 100 under the situation of low power consumption equipment, for example, the small battery powered equipment as the smart card, V
r SimplisticBe undesirable especially.Alternatively, need a kind of like this technology,, can reduce V by this technology
Th PTP=V
Th Pre-PTP+ Δ V
PTPAs the compensation that this PTP-induction threshold voltage is increased.In other situation,, demonstrated downward change/minimizing Δ V that a unification is arranged in threshold voltage (Vth) according to embodiments of the invention
Non-unichannel-dielec≈-Δ V
PTPThereby obtain following equation,
V
th comp＝V
th PTP+ΔV
non-unichannel-dielec
＝(V
th pre-PTP+ΔV
halo)+(-ΔV
halo)
V
Th Comp≈ V
Th Pre-PTP(equation 1)
Δ V wherein
Non-unichannel-dielecRepresent in the threshold voltage unified because the caused downward change of the uneven thickness of gate dielectric material (below will be described in a more detailed discussion) on the channel region of memory transistor/reduce.
According to an aspect of the present invention, this threshold voltage that reduces or compensate (Vth), i.e. V
Th Comp, be explained as follows.Form the gate dielectric structure 256 of MTR240, to such an extent as to gate- dielectric part 204b and 204c represent the non-uniform thickness of gate dielectric material on the raceway groove together.This uneven degree is far longer than the manufacturing tolerance that is produced in the manufacturing of thickness conforming layer.The thickness this heterogeneous of gate dielectric material has been realized at V on the raceway groove of being represented together by gate- dielectric part 204b and 204c
Th PTPIn the identical Δ V of change/minimizing downwards
Non-unichannel-dielec≈-Δ V
PTP
More specifically, MTR240 can represent by following circuit,
(circuit 1)
It has series capacitors C1=C
218aAnd C2=C
256(C2 is connected with zero volt).In charging process, V1 is high voltage (V
H), V1=V
HAnd be added to control grid layer 220a, and V3 is zero volt, V3=0
V, and be added to floating junction 244.On the contrary, in discharge process, V1=0
VBe added to control grid layer 220, and V3=V
HBe added to floating junction 244.Voltage V1 forms following V2 through capacitor C1 and C2 dividing potential drop
Wherein
Be capacitive coupling rate, C
Dielec_nearest_VHBe to be V from institute's making alive
HThe nearest capacitor volume of node.What it should be noted that is that V2 just in time is directly proportional with the intensity of MRT240 charge/discharge.
That notice equally is C
256=C
204c+ C
204b+ C
204a+ C
204dCorrespondingly, circuit 1 can be repainted as following,
Capacitor C with 204c
204aAnd C
204cMuch smaller.Therefore, circuit 2 can followingly repaint again.
Fig. 3 is the simple explanation of Fig. 2, and it shows circuit 3 overlapping on MTR240.According to equation 3, capacitor C
204bAnd C
204dCan ignore and do not participate in equation, as follows.
According to embodiments of the invention, equation 5 is the unified explanations that change downwards/reduce of threshold voltage, for example, and to V
Th PTPCompensation.In addition, in charging process, V1=V
HAnd be added to control grid layer 220a, and V3=0
VAnd be added to floating junction 244, so C
Dielec_adjacent_VH=C
218aSubstitution equation 4 obtains following equation.
In addition, in discharge process, V1=0
VAnd be added to control grid layer 220a, and V3=V
HAnd be added to floating junction 244, and C
Dielec_adjcent_VH=C
204aSubstitution equation 4 obtains following equation.
By checking of equation 5 and 6 shown
With
May be summarized to be following equation.
On the contrary, as follows according to the ratio of the V2 of background technology MTR140.
By the inhomogeneities that gate- dielectric part 204c and 204b represent together, according to embodiments of the invention an extra item has been introduced in the denominator of V2 ratio, i.e. C
204c
In other words, according to embodiments of the invention, there is ratio
Its with at V2
MTR_240Do not have corresponding to C in the ratio
204cThe background technology of item form contrast.Similarly, gate-dielectric part 204c can be used for downward change/reduce threshold voltage.
Recall electric capacity and thickness is inversely proportional to,
Can pass through T
FarBe reduced to and compare T
TunnelThe little capacitor C that improves
204c, i.e. T
Far＜T
TunnelBy improving C
204cReduce V2 with respect to background technology
MTR_140V2
MTR_240
The thickness heterogeneous (according to embodiments of the invention) of the gate dielectric material of being come together to represent by gate- dielectric part 204b and 204c has produced one and has compared less V2 value, V2 with background technology
MTR_240＜V2
MTR_140, like this with regard to make MTR240 compare with the MTR140 of background technology charge function a little less than.This more weak charging causes threshold voltage to reduce accordingly.Equally, come together to represent that by gate- dielectric part 204b and 204c this inhomogeneities causes the discharging function of the MTR240 relative with the MTR140 of background technology stronger.This stronger discharge causes threshold voltage to reduce relatively equally.Therefore, according to Δ V
Non-unigate-dielec≈-Δ V
PTP, the undesired increase that is produced in the net effect voltage of this inhomogeneities that gate- dielectric part 204b and 204c represent has together obtained compensation because of the represented together described heteropical net effect of gate- dielectric part 204b and 204c.
The example of introducing above will be expanded in conjunction with the approximation (though being example) of some parameters that are used for EEPROM cellular construction 200 now, as shown in following table.Fig. 4 is the explanation of Fig. 2, and it shows the thickness and the length of the expansion example of mentioning below.Length L
MTRBe the length of MTR240.The length of gate-dielectric part 204a-204d is respectively L
a, L
b, L
cAnd L
d
| Parameter | Approximation | Parameter | Approximation | Parameter | Approximation | ||
| ??L a | ????0.18≤La≤0.20 | ??T tunnel | ??＝70 | ?T 216 | ???0.15μ ??????m | ||
| ??L b | ????≥0.10μm | ??T near | ??250≤T edge??≤280 | ?T 218 | ???90 | ||
| ??L c | ????＝0.43μm | ??T far | ??＝70 | ?T 220 | ???0.15μ ??????m | ||
| ??L d | ????＝0.12μm | ??T edge | ??250≤T edge??≤280 | ||||
| ??L MTR | ????＝0.9μm | ??T STR | ??250≤T edge??≤280 | ||||
In addition, above in the form the concrete value of length and thickness only be that example has been not the qualification effect.
Now discussion is used to make the example of the method for embodiments of the invention, according to the example of former introduction, and with respect to Fig. 5 A-5H, it be the cross section of various states during according to embodiments of the invention manufacturing EEPROM cellular construction 200.Among Fig. 5 A, provide the substrate 201 of P-type conduction.Inject formation PTP layer 249 by ion, for example, 700Kev ﹠amp; 2.0 (10
13)/cm
2Boron also can 50Kev ﹠amp; 1.5 (10
12)/cm
2Then, form field region 202.Form the gate-dielectric ground floor 204 that a thickness is approximately 240～280 .Carry out ion in the fabrication region 206 of N-type alloy then and inject, for example, use 50-70Kev ﹠amp; 7.0 (10
13)/cm
2Phosphorus or 60-120Kev ﹠amp; 7.0 (10
13)～1.5 (10
14)/cm
2Arsenic.
In Fig. 5 B, designed ground floor 204, then that part of the removing that is positioned on the zone 208 and 210, wherein zone 208 is corresponding with Close Tunnel of making subsequently and channel layer far away respectively with 210.
Among Fig. 5 C, randomly carry out more polyion injection, for example, adopt 25-45Kev ﹠amp to make compensating basin 250; 2.0 (10
11)/cm
2～5.0 (10
11)/cm
2Arsenic.If produced district 250, the concentration of the N-type alloy in the zone 206 just has been enhanced so.Among Fig. 5 D, form the second layer 204 that thickness is approximately the gate-dielectric of 70～80 , it has generated gate- dielectric part 204c, 204b, 204a and 204y.
Among Fig. 5 E, form floating grid layer 216, for example, thickness is approximately the polysilicon of 1000～2000 .Among Fig. 5 F, form dielectric medium structure 218, for example, thickness is approximately the ONO structure with protoxide layer of 50 , and thickness is approximately the nitride layer of 80 and the last oxide skin(coating) that thickness is approximately 60 .Then, form control grid layer 220, for example, thickness is approximately the polysilicon of 1000～2000 , and this has just formed intermediate structure.
Among Fig. 5 G, designed intermediate structure 502 and removed some part selectively in order to the MTR240 at definition initial stage and the STR242 at initial stage.As a result, gate-dielectric part 204y becomes the gate-dielectric part 204d of MTR240 at initial stage and the gate-dielectric part 204e of the STR242 at initial stage.Carry out polyion more then and inject the zone 227,228 and 231 that has the initial stage of N-type alloy one low concentration (N-) in order to manufacturing, for example, adopt 25Kev ﹠amp; 2.0 (10
14)/cm
2Arsenic.Among Fig. 5 H, form sidewall spacers 252 and 254.Then, carry out more ion and inject the zone 226 and 230 that has N-type alloy one higher concentration (N+) with formation, for example, adopt 50Kev ﹠amp; 5.0 (10
15)/cm
2Arsenic.Correspondingly the concentration in the zone at initial stage rises to N+.At last, carry out another ion injection and become N-again, for example, adopt 90Kev ﹠amp with concentration with zone 228; 8.0 (10
12)/cm
2Phosphorus.Next, on the sidewall of MTR and STR, form sidewall spacers 252 and 254.
The present invention is so described, and it is evident that, can adopt several different methods to change this structure and method.This variation does not break away from the spirit and scope of the present invention, and all such modifications all are included in the scope of the present invention.
Claims (27)
1, EEPROM cellular construction with non-uniform channel-dielectric thickness, this EEPROM cellular construction comprises:
The semiconductor substrate;
Memory transistor on the substrate and one is selected transistor; And
That in substrate, form between the transistor and partly extend to a floating junction below the memory transistor;
Gate dielectric layer in the memory transistor is along laterally being arranged to
Thickness is T
TunnelAnd be superimposed upon a Close Tunnel on a part of floating junction,
Thickness is T
Near＞T
TunnelAnd be positioned at the next door of Close Tunnel and select the relative nearly channel region of transistor, and
Thickness is T
Far＜T
NearAnd the next door that is positioned at a nearly channel region far away channel region relative with Close Tunnel.
2, EEPROM cellular construction as claimed in claim 1, wherein T
Tunnel≈ T
Far
3, EEPROM cellular construction as claimed in claim 1 wherein is fit to one of the following at least:
With
4, EEPROM cellular construction as claimed in claim 1, wherein T
NearApproximate the thickness of selecting transistorized gate dielectric layer greatly.
5, EEPROM cellular construction as claimed in claim 1, the lateral dimension of wherein near channel region, L
Near, be L
Near〉=0.1 μ m.
6, EEPROM cellular construction as claimed in claim 1, wherein the gate-dielectric in the memory transistor is arranged to further comprise that a thickness is T
Edge≈ T
NearAnd next door that is positioned at Close Tunnel and nearly channel region opposed edges district.
7, EEPROM cellular construction as claimed in claim 1, wherein:
This substrate is first conduction type; And
Form a light dope compensating basin of second conduction type in the substrate below gate-dielectric channel region far away.
8, EEPROM cellular construction as claimed in claim 7, wherein channel region far away regional corresponding of automatic alignment so and gate dielectric layer adopted in the compensating basin zone.
9, EEPROM cellular construction as claimed in claim 7, wherein:
The degree of depth of compensating basin is d
CompAnd
Forming a degree of depth in the substrate of contiguous compensating basin is d
Source＞d
CompThe source region.
10, EEPROM cellular construction as claimed in claim 7, wherein the conduction type of this compensating basin is the N-type.
11, EEPROM cellular construction as claimed in claim 7, wherein gate-dielectric is a kind of oxide.
12, EEPROM cellular construction as claimed in claim 7, wherein:
This selection transistor comprises a gate dielectric layer; And
Each transistor also comprises
Poly floating grid layer on the gate dielectric layer,
Another dielectric layer on the floating grid layer, and
Polysilicon control grid utmost point layer on other dielectric layers;
13, as the EEPROM cellular construction of claim 12, should the another kind dielectric be ONO wherein.
14, a kind of manufacturing has the method for the EEPROM cellular construction of non-uniform channel-dielectric thickness, and this method comprises:
Form a gate-dielectric ground floor on semiconductor substrate, wherein said substrate has and the tunnel of making subsequently, raceway groove far away and nearly channel region corresponding respectively first, second and the 3rd zone, and this first and the 3rd zone is separated by second area;
Selectively remove the part of the ground floor on the first and the 3rd zone;
On the expose portion of ground floor and substrate, form the gate-dielectric second layer;
The thickness T of the gate dielectric material on the first, the second and the 3rd zone respectively
Tunnel, T
NearAnd T
Far, have the T of relation
Near＞T
TunnelAnd T
Near＞T
Far
On the second layer, continue to form and the corresponding extra play of transistorized composition; And
Selectively remove part the first, the second and extra play with the memory at definition initial stage and select transistor so that make this first, the second and the 3rd zone be positioned at memory transistor below.
15, as the method for claim 14, T wherein
Tunnel≈ T
Far
16, as the method for claim 14, wherein use one of the following at least:
With
17, as the method for claim 14, T wherein
NearApproximate the thickness of selecting transistorized gate dielectric layer greatly.
18, as the method for claim 14, the lateral dimension of nearly channel region wherein, L
Near, be L
Near〉=0.1 μ m.
19, as the method for claim 14, wherein selectively remove the step of part ground floor, cause the thickness T of gate dielectric material
EdgeHas the T of relation
Edge≈ T
Near, wherein said material on the 4th zone, to be positioned at a side of first area relative with second area and corresponding to the marginal zone.
20, as the method for claim 14, wherein:
This substrate is first conduction type; And
This method also comprises
In the 3rd zone of substrate, form a light dope compensating basin of second conduction type.
21, as the method for claim 20, also comprise:
This compensating basin is extended downwardly into depth d
CompAnd
Forming a downward degree of depth in substrate is d
Source＞d
CompThe source region.
22, as the method for claim 20, also comprise:
The conduction type that makes this compensating basin is the N-type.
23, as the method for claim 14, also comprise:
Use the material of oxide as first and second layers of this gate-dielectrics.
24, EEPROM cellular construction with non-homogeneous gate dielectric thickness, this EEPROM comprises:
A semiconductor substrate;
Memory transistor on the substrate and a corresponding transistor of selecting; And
That in substrate, form between the transistor and partly extend to a floating junction below this memory transistor;
Be positioned at the in uneven thickness of gate-dielectric layer segment above the channel region in the memory transistor, this uneven degree is much larger than the manufacturing tolerance that is produced in the thickness manufacturing of layer uniformly.
25, as the EEPROM cellular construction of claim 24, wherein:
On the channel region away from the thickness T of the transistorized gate dielectric layer of this corresponding selection
FurtherThickness T less than the approaching transistorized gate dielectric layer of this corresponding selection on the channel region
Closer, T
Further＜T
Closer
26, a kind of manufacturing has the method for the EEPROM cellular construction of non-homogeneous gate dielectric thickness, and this method comprises:
On semiconductor substrate, form the gate-dielectric ground floor;
Selectively remove the ground floor of part on the substrate presumptive area;
On the expose portion of ground floor and substrate, form the gate-dielectric second layer;
On the second layer, continue to form extra play corresponding to transistorized composition; And
Selectively remove part this first, the second and extra play in order to the memory transistor that defines an initial stage and the selection transistor at a corresponding initial stage;
The thickness that is arranged in the memory transistor gate dielectric material at initial stage on the channel region is heterogeneous, and this uneven degree is much larger than the manufacturing tolerance that is produced in making the uniform layer of thickness.
27, as the EEPROM cellular construction of claim 26, also comprise:
To such an extent as to selectively remove on the part ground floor channel layer the thickness T that is obtained away from the transistorized gate dielectric material of corresponding selection
FurtherThe thickness T that is obtained less than the approaching transistorized gate dielectric layer of corresponding selection on the channel layer
Closer, T
Further＜T
Closer
Applications Claiming Priority (8)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR31910/2003 | 2003-05-20 | ||
| KR20030031910 | 2003-05-20 | ||
| KR31910/03 | 2003-05-20 | ||
| KR1020030060763A KR20040100813A (en) | 2003-05-20 | 2003-09-01 | EEPROM device including memory gate oxide having partially different thickness and fabrication method thereof |
| KR60763/03 | 2003-09-01 | ||
| KR60763/2003 | 2003-09-01 | ||
| US10/834,226 US20040232476A1 (en) | 2003-05-20 | 2004-04-29 | EEPROM cell structures having non-uniform channel-dielectric thickness and methods of making the same |
| US10/834,226 | 2004-04-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1599071A true CN1599071A (en) | 2005-03-23 |
| CN100401521C CN100401521C (en) | 2008-07-09 |
Family
ID=33424824
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100631378A Expired - Fee Related CN100401521C (en) | 2003-05-20 | 2004-05-20 | EEPROM cell structures having non-uniform channel-dielectric thickness and methods of making the same |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JP2005012191A (en) |
| KR (1) | KR100604850B1 (en) |
| CN (1) | CN100401521C (en) |
| DE (1) | DE102004025976B4 (en) |
| FR (1) | FR2855325B1 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101431078B (en) * | 2007-11-05 | 2010-04-14 | 国际商业机器公司 | CMOS EPROM and EEPROM devices and programmable CMOS inverters |
| CN101983423A (en) * | 2008-03-31 | 2011-03-02 | 富士通半导体股份有限公司 | Semiconductor device |
| CN106206748A (en) * | 2016-08-29 | 2016-12-07 | 上海华虹宏力半导体制造有限公司 | SONOS device and manufacture method thereof |
| CN106972021A (en) * | 2016-01-12 | 2017-07-21 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic installation |
| CN107785274A (en) * | 2017-11-09 | 2018-03-09 | 上海华力微电子有限公司 | A kind of method for improving flash memory programming efficiency |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11641739B2 (en) * | 2020-06-01 | 2023-05-02 | Globalfoundries Singapore Pte. Ltd. | Semiconductor non-volatile memory devices |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CH633123A5 (en) * | 1979-08-24 | 1982-11-15 | Centre Electron Horloger | Electrically reprogrammable non-volatile memory element |
| JPS5857750A (en) * | 1981-10-01 | 1983-04-06 | Seiko Instr & Electronics Ltd | Non-volatile semiconductor memory |
| JPS58130571A (en) * | 1982-01-29 | 1983-08-04 | Hitachi Ltd | Semiconductor device |
| EP0105802A3 (en) * | 1982-09-30 | 1986-02-26 | Fairchild Semiconductor Corporation | Programmable read only memory |
| JPS61194877A (en) * | 1985-02-25 | 1986-08-29 | Nec Corp | Insulation gate-type nonvolatile semiconductor memory |
| JPS61222175A (en) * | 1985-03-01 | 1986-10-02 | Fujitsu Ltd | Manufacture of semiconductor memory device |
| JPH02277269A (en) * | 1989-04-19 | 1990-11-13 | Matsushita Electron Corp | Manufacture of nonvolatile memory |
| JPH088314B2 (en) * | 1989-10-11 | 1996-01-29 | 株式会社東芝 | Nonvolatile semiconductor memory device and manufacturing method thereof |
| JP3124334B2 (en) * | 1991-10-03 | 2001-01-15 | 株式会社東芝 | Semiconductor storage device and method of manufacturing the same |
| KR940009644B1 (en) * | 1991-11-19 | 1994-10-15 | 삼성전자 주식회사 | Non-volatile semiconductor memory device and manufacturing method thereof |
| JPH05275707A (en) * | 1992-03-30 | 1993-10-22 | Toshiba Corp | Manufacture of nonvolatile semiconductor memory device |
| DE19614011C2 (en) * | 1996-04-09 | 2002-06-13 | Infineon Technologies Ag | Semiconductor component in which the tunnel gate electrode and the channel gate electrode are interrupted by an insulation structure at the interface with the tunnel dielectric or gate dielectric |
| KR100311971B1 (en) * | 1998-12-23 | 2001-12-28 | 윤종용 | Non-volatile Memory Semiconductor Device Manufacturing Method |
| KR100383703B1 (en) * | 1999-04-01 | 2003-05-14 | 아사히 가세이 마이크로시스템 가부시끼가이샤 | Method of manufacturing semiconductor deⅴice |
-
2004
- 2004-05-11 KR KR1020040033074A patent/KR100604850B1/en active IP Right Grant
- 2004-05-18 DE DE102004025976A patent/DE102004025976B4/en not_active Expired - Fee Related
- 2004-05-19 FR FR0405487A patent/FR2855325B1/en not_active Expired - Fee Related
- 2004-05-20 JP JP2004150136A patent/JP2005012191A/en active Pending
- 2004-05-20 CN CNB2004100631378A patent/CN100401521C/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101431078B (en) * | 2007-11-05 | 2010-04-14 | 国际商业机器公司 | CMOS EPROM and EEPROM devices and programmable CMOS inverters |
| CN101983423A (en) * | 2008-03-31 | 2011-03-02 | 富士通半导体股份有限公司 | Semiconductor device |
| CN101983423B (en) * | 2008-03-31 | 2014-03-26 | 富士通半导体股份有限公司 | Semiconductor device |
| CN106972021A (en) * | 2016-01-12 | 2017-07-21 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic installation |
| CN106972021B (en) * | 2016-01-12 | 2019-12-13 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method thereof and electronic device |
| CN106206748A (en) * | 2016-08-29 | 2016-12-07 | 上海华虹宏力半导体制造有限公司 | SONOS device and manufacture method thereof |
| CN106206748B (en) * | 2016-08-29 | 2020-02-07 | 上海华虹宏力半导体制造有限公司 | SONOS device and manufacturing method thereof |
| CN107785274A (en) * | 2017-11-09 | 2018-03-09 | 上海华力微电子有限公司 | A kind of method for improving flash memory programming efficiency |
Also Published As
| Publication number | Publication date |
|---|---|
| DE102004025976B4 (en) | 2011-04-28 |
| KR20040100909A (en) | 2004-12-02 |
| JP2005012191A (en) | 2005-01-13 |
| FR2855325A1 (en) | 2004-11-26 |
| KR100604850B1 (en) | 2006-07-31 |
| FR2855325B1 (en) | 2008-12-05 |
| CN100401521C (en) | 2008-07-09 |
| DE102004025976A1 (en) | 2004-12-16 |
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