CN1286329C - Pi/4DQPSK demodulator and its method - Google Patents

Abstract

The present invention provides a Pi/4DQPSK demodulator and a demodulation method thereof. A software radio technology is introduced in a demodulator which is based on a structure with both limiter and phase discriminator so that the angular resolution of the demodulator is not limited by the magnitude of a sampling frequency any more. Simultaneously, a reception matched filter adopts a root elevating cosine filter so as to reduce intersymbol interference, and thus, the problem that a demodulator based on the structure of a hard limiter is sensitive to a roll-off factor of a root elevating cosine filter at a sending end is solved. Because the structure of the demodulator of the present invention integrates the architecture with both a limiter and a phase discriminator, and a software radio structure, the present invention has the advantages of simple structure and no need of an AGC or an A/D converter, and is not much sensitive to the variation of signal amplitude. The structure not only can be applied to a PHS system and a PCS system, but also can be applied to signal demodulation of a wireless communication system based on a PSK modulation technique, such as a satellite communication system.

Description

A kind of π/4DQPSK demodulator and demodulation method thereof

Technical field

The present invention relates to moving communicating field, relate in particular to a kind of PHS of being applied to system, pcs system and based on the π/4DQPSK modem device and the demodulation method thereof of the signal demodulation of the wireless communication system of PSK modulation technique.

Background technology

In mobile communication system, PHS (Nippon Standard) and PCS (Unite States Standard) adopt the mode of time division multiplexing (TDMA), and each channel is used in the different moment by a plurality of users, and is promptly so-called multiplexing.PHS and PCS are respectively the information of 384kb/s (PHS) and 48.6kb/s (PCS) for the channel speed that is respectively 300kHz (PHS) and 30kHz (PCS) at frequency range, all adopted the high high-order modulating of spectrum efficiency, i.e. π/4 DQPSK modulation systems.π/4 DQPSK modulation systems are compared with other high-order modulating, except having the high advantage of spectrum efficiency, also have following advantage:

1) be fit to adopt coherent demodulation mode, differential ference spiral mode and frequency discrimination to add the demodulation mode of integrator, for back two kinds of demodulation modes, their biggest advantage is simple in structure; For the coherent demodulation mode, owing to need carrier recovery circuit, so structure is complicated, verified simultaneously, to the residing fast fading channel of mobile communication system, the error rate of coherent demodulation mode will be higher than the non-coherent demodulation mode;

2) because the constellation space of π/4DQPSK has 8 constellation point, not by initial point, so the envelope of π/4DQPSK signal rises and falls less than other high-order modulating, as QPSK, this linearity to power amplifier requires and can reduce when constellation point is changed for it.

In order further to improve the π/performance of 4DQPSK modulation system under mobile communication environment,, can adopt following technology as the message transmission rate and the network coverage:

1) at transmitting terminal signal spectrum is carried out shaping, to reduce interference (CCI) to adjacent channel signal, simultaneously, by the matched filter (being similarly root raised cosine filter) that is complementary with transmitting terminal root raised cosine filter (RRCF) is set in the demodulator of receiving terminal, can reduce intersymbol interference (ISI), it is the root raised cosine filter (RRCF) of 0.5 (the PHS system is 0.3 to pcs system) that transceiving filter adopts roll-off factor;

2) intelligent antenna technology, intelligent antenna technology adds array signal process technique by a plurality of antenna receiving signals, can reduce the influence of interference signal, improves communication quality and system and covers.

At present, comprising the PHS system that adopts intelligent antenna technology, π/4 DQPSK demodulators often adopt software radio architecture (softwrae Radio), as structure (Journal ofSystems Engineering and Electronics as described in the following document, vol.14, No.2,2003, pp20-24, A NewSignal Processing Technique of π/4 DQPSK Modem Based on softwraeRadio), be that the radiofrequency signal that receiver receives at first is exaggerated in AFE (analog front end), filtering is down-converted to intermediate frequency again, and the A/D converter is sampled to analog if signal, sampled signal is handled through digital down-conversion technology, become baseband signal, baseband signal is made differential ference spiral, can recover subscriber signal.The receiver that adopts intelligent antenna technology remakes differential ference spiral to multichannel after base band signal weighted.

Because mobile communication environment lower channel intercropping rapid fading at any time, so signal amplitude alters a great deal, reach tens decibels (dB), therefore, in order to guarantee the performance of receiver under fast fading channel, need before the A/D converter, add automatic gain control (AGC) based on software radio architecture.

The another kind of normal receiver structure that adopts is that amplitude limiter adds the phase discriminator structure, promptly be down-converted to the intermediate-freuqncy signal of intermediate frequency through AFE (analog front end), by a logarithmic amplifier, logarithmic amplifier divides two-way output, one the tunnel is hard-limiting (Hard limiter) output, and another road is signal intensity indication signal (RSSI) output.The phase modulation square-wave signal of amplitude limiter output can obtain π/4 DQPSK phase-modulated signals (user data) by phase discriminator, integrator and phase difference.

Compare with the demodulator of software radio architecture, the demodulator that amplitude limiter adds the phase discriminator type has simple in structure, need not AGC, the advantage of A/D converter, simultaneously, because its signal after to amplitude limit is made phase discrimination processing, signal amplitude is changed not too responsive, so be more suitable for the fast fading channel of wireless communication system.

Fig. 1 is the schematic diagram that amplitude limiter adds the demodulator of phase discriminator structure, and it is specially the PHS system adds the phase discriminator structure based on amplitude limiter π/4 DQPSK differential ference spiral device theory diagrams.After radio frequency amplification in the signal process PHS receiver that antenna receives, the filtering, subtract each other, become intermediate-freuqncy signal, as IF-FRE F1=10.8MHz with local frequency.10.8MHz intermediate-freuqncy signal by behind amplitude limiter, export two signals, one is continuous in time logical signal z (t) with two logic levels, and this, position of logical signal zero crossing comprised the angle modulated information of π/4 DQPSK continuous time; Another output signal is signal strength signal intensity indication RSSI (t) signal, and this signal has reflected the amplitude information of input signal.

The phase discriminator module is sampled to the logical signal of amplitude limiter output by sampling clock, obtains discrete in time logical signal c (k), k=1, and 2,3 ...,

As: c (k)=0,0,0,0,0,0,1,1,1,1,1,0,0,0,0,0 ...,

The processing mode of back is different to passband differential ference spiral and base band differential ference spiral mode.

To the passband differential ference spiral, as Chinese patent (application number: 98105882.5, publication number: CN1192526A) described, the sliced sample signal of a last symbol period and the sliced sample signal of next symbol period are made XOR XOR, then XOR is exported by an integration/overworked device (Integrate/Dump) that puts out, then obtain the difference angle, the difference angle signal obtains modulation symbol by decision circuit.

To base band demodulating, as patent United States Patent (USP) (United States Patent, 6,055,281, Hendrickson, et al., April 25,2000, Passband DQPSK detector for a digitalcommunications receiver), different with above-mentioned passband differential ference spiral mode is that the sliced sample signal of a symbol period is made XOR XOR with the local square-wave signal that produces, and the output of Integrate/Dump is done to adjudicate output behind the angular difference.

The IF-FRE F1=10.8MHz of bidding standard, symbol rate is Fb/2, and sampling clock is Fs, and obviously, the angular resolution of the demodulator of this structure is F1/Fs*2 π, if reach the angle requirement of antenna system ± 5 degree, then Fs=800MHz.If the reduction sample rate only takes extra super-heterodyne architecture to reduce IF-FRE, make system complexity improve.This is the contradiction that amplitude limiter adds phase discriminator structure angular resolution and sample rate.

Also have, because Integrate/Dump is an infinite bandwidth the transmit matched filter of waveform, so, do not match less than 1 the finite bandwidth waveform (be as roll-off factor 0.5 PHS system) that transmits for roll-off factor, so can't eliminate intersymbol interference.

Fig. 2 is the schematic diagram of the demodulator of software radio architecture, it is specially the structured flowchart of the π/4 DQPSK demodulators that adopt the software wireless structure, the intermediate frequency input signal at first becomes the continuous analog signal into signal discrete on time/amplitude by the A/D sampler, multiply each other with local oscillation signal in multiplier in the back, multiplied result reduces sampling rate through behind the extraction/filtering extraction, enter root raised cosine filter again, do base band differential ference spiral and judgement at last.Software radio architecture does not have the contradiction of angular resolution and sample rate, because according to the sampling law, as long as sample rate is greater than the twice of signal highest frequency component, and restoring signal characteristic (comprising angle information) fully just.

Have above-mentioned advantage though amplitude limiter adds the phase discriminator structure, its phase discriminator adopts the Direct Phase digitizing technique, as U.S. Pat .Paten No.5084669, and Chinese patent (application number: 98105882.5, publication number: CN 1192526A) described.The amplitude limiter of employing phase digitization technology adds its shortcoming of phase discriminator structure and is:

1) phase accuracy is subjected to the restriction of sampling clock size, and in intelligent antenna technology, for the performance that guarantees algorithm is not lost, it is high that the phase estimation precision is wanted, as ± 5 degree, and will reach such phase accuracy, sample frequency reaches more than the hundreds of MHz, this can reduce the stability of circuit, increases difficulty and the cost realized;

2) receiving terminal does not have the root raised cosine matched filter, can't satisfy the requirement of ISI, we know to have only the sending and receiving end to adopt root raised cosine filter simultaneously, could realize the matched filtering of sending and receiving end, eliminate intersymbol interference, otherwise, if having only transmitting terminal to adopt root raised cosine filter, then the intersymbol interference of introducing in advance thus can't be eliminated, increased the intersymbol interference of system, do not reached the purpose of eliminating intersymbol interference, this also is based on the reason of the receiver of amplitude limiter structure to the roll-off factor sensitivity;

3) filter behind the phase discriminator adopts the Integrate/Dump structure based on counter structure because structure is limit, and performance of filter can not guarantee, can't satisfy the requirement of angle resolution.

Summary of the invention

The object of the present invention is to provide a kind of π/4 DQPSK demodulators, this demodulator is introduced amplitude limiter with software and radio technique and is added the phase discriminator structure, adopt amplitude limiter to add the mixed form of phase discriminator structure and software radio architecture, with solve amplitude limiter in the prior art add phase discriminator structure phase resolution low, do not receive the problem that matched filter and phase discriminator postfilter can't satisfy the antenna system requirement.

Another object of the present invention is to provide the demodulation method of a kind of π/4 DQPSK demodulators, software and radio technique is introduced amplitude limiter add the phase discriminator structure, adopt amplitude limiter to add the mixed form of phase discriminator structure and software radio architecture, with solve amplitude limiter in the prior art add phase discriminator structure phase resolution low, do not receive the problem that matched filter and phase discriminator postfilter can't satisfy the antenna system requirement.

The present invention is achieved in that

The invention discloses a kind of π/4 DQPSK demodulators, be applied in the mobile communcations system, adopt amplitude limiter to add phase discriminator structure and software radio architecture mixed form, comprise following several sections:

(1) hard limiter is used for continuous logical signal of output time and signal intensity indication signal RSSI;

(2) sampling/down conversion module is used for the logical signal of hard limiter output is sampled, and its fundamental component is carried out conversion;

(3) multiplication module is used for sampled signal and local sinusoidal signal and the cosine signal that produces are multiplied each other, and realizes the frequency spectrum translation conversion;

(4) extraction/filter module is used for down-sampled processing is done in multiplication module output;

(5) root raised cosine matched filter, the filter that is used for receiving filter and transmitting terminal synthesizes raised cosine filter, in the sampling instant of the best, eliminates intersymbol interference;

(6) differential ference spiral/synchronization module is used to carry out optimum sampling estimation constantly and frequency offset estimating and compensation;

(7) sine and cosine table and clock module, sine and cosine table are used to described multiplier that the cosine and sine signal of quadrature is provided, and clock module provides essential clock for all the other modules of described demodulator.

Described logical signal has two logic levels, with the corresponding relation of input intermediate-freuqncy signal be, when input intermediate-freuqncy signal amplitude is a high level greater than 0 the time, and when input intermediate-freuqncy signal amplitude be low level less than 0 the time, mathematic(al) representation is: z (t)=sign (z (t)) sign (x) expression is got symbolic operation to x.

The frequency spectrum of described logical signal frequency spectrum on the harmonic wave frequency is identical, harmonic component is (2n+1) F1.

The spectral sample frequency Fs of described logical signal and the pass of signal center frequency F1 and signal spectrum are:

Fs=mF1/ (2n+1), simultaneously, Fs=l * F2, F2 are the fundamental frequency that produces behind the Fs sampling F1.

Described hard limiter can be logarithmic amplifier.

Before the described extraction signal is carried out Filtering Processing.

Described sampling/down conversion module can be d type flip flop.

Described extraction/filter module can be half-band filter and cic filter.

Described optimum sampling estimates to realize by the sampling instant restore circuit symbol sampler of no intersymbol interference constantly.

Described frequency offset estimating makes receiving terminal consistent with the transmitting terminal frequency with compensation.

The invention also discloses the demodulation method of a kind of π/4 DQPSK demodulators, comprise that step is as follows:

(1) the analog intermediate frequency continuous signal of receiving terminal changes the logical signal and the signal intensity indication signal RSSI of two level into through hard limiter;

(2) logical signal of hard limiter output is sampled through over-sampling/low-converter, and realizes that simultaneously the first harmonic frequency of logical signal is F2 from the F1 down conversion;

(3) logical signal after the sampling multiplies each other through multiplier and cosine and sine signal, to realize the frequency spectrum translation conversion;

(4) signal of the frequency spectrum translation conversion by multiplier output extracts to finish sampling rate conversion through extractions/filter, with the sample rate reduction, makes follow-up unit promptly receive the designs simplification of root raised cosine matched filter;

(5) signal of Chou Quing carries out matched filtering by root raised cosine reception matched filter on lower sample rate, eliminates intersymbol interference;

(6) receive the signal process differential ference spiral/synchronization module of matched filter output to estimating owing to the inconsistent frequency deviation that causes of sending and receiving end frequency and compensating, simultaneously, determine the optimum sampling moment of judgement, carry out calculus of differences and judgement then, thereby finished π/4 DQPSK signal demodulation.

In the described step (1), described logical signal has two logic levels, with the corresponding relation of input intermediate-freuqncy signal be, when input intermediate-freuqncy signal amplitude is a high level greater than 0 the time, and when input intermediate-freuqncy signal amplitude be low level less than 0 the time, mathematic(al) representation is: z (t)=sign (z (t)) sign (x) expression is got symbolic operation to x.

In the described step (2), signals sampling/low-converter sampling can realize by d type flip flop.

In the described step (4), signal also comprised the step of signal being carried out Filtering Processing before extraction/filter extracts.

The frequency spectrum of described logical signal frequency spectrum on the harmonic wave frequency is identical, harmonic component is (2n+1) F1.

The spectral sample frequency Fs of described logical signal and signal center frequency F1 and signal general pass are frequently:

Fs=mF1/ (2n+1), simultaneously, Fs=l * F2, F2 are the fundamental frequency that produces behind the Fs sampling F1.

Described hard limiter can be logarithmic amplifier.

Described sampling/down conversion module can be d type flip flop.

Described extraction/filter module can be half-band filter and cic filter.

Described frequency offset estimating makes receiving terminal consistent with the transmitting terminal frequency with compensation.

In the described step (6), optimum sampling is estimated to realize by the sampling instant restore circuit constantly.

The described moment estimates to realize by the sampling instant restore circuit symbol sampler of no intersymbol interference.

In the described step (6), frequency offset estimating and collocation structure comprise that forward direction structure and back are to structure.

Described frequency deviation estimating method comprises auxiliary and auxiliary two classes of non-data of data.

π of the present invention/4 DQPSK demodulator and demodulation methods thereof, by being introduced, software and radio technique adds in the demodulator of phase discriminator structure based on amplitude limiter, make the angular resolution of demodulator no longer be subjected to the restriction of sample frequency size, simultaneously, adopted root raised cosine filter owing to receive matched filter, reduced intersymbol interference, feasible demodulator based on the hard limiter structure is solved transmitting terminal root raised cosine filter roll-off factor sensitive issue.

Since the structure composition of demodulator of the present invention amplitude limiter add phase discriminator structure and software radio architecture, so it also has simple in structure, need not AGC, A/D converter, signal amplitude is changed not too responsive advantage.This structure not only can be applicable to PHS system and pcs system, and can be applicable to the signal demodulation based on the wireless communication system of PSK modulation technique, as satellite communication system.

Description of drawings

Fig. 1 is the schematic diagram that amplitude limiter adds the demodulator of phase discriminator structure;

Fig. 2 is the schematic diagram of the demodulator of software radio architecture;

Fig. 3 is the structural representation of π of the present invention/4 DQPSK demodulators;

Fig. 4 is the specific implementation method schematic diagram of π of the present invention/4 DQPSK demodulators;

Fig. 5 is the FPGA output planisphere of the concrete technical application scheme of π of the present invention/4 DQPSK demodulators.

Embodiment

The present invention introduces software and radio technique in amplitude limiter adds the demodulator of phase discriminator structure, effectively overcome the contradiction of angular resolution and sample rate in the demodulator that amplitude limiter adds the phase discriminator structure, the introducing of software and radio technique, make to add and realize in the demodulator of phase discriminator structure that receiving matched filter becomes possibility, has reduced intersymbol interference at amplitude limiter.The scheme that above-mentioned two kinds of structures are organically combined formation of the present invention has had both two kinds of schemes advantage separately, simultaneously, has overcome two kinds of schemes shortcoming separately.

Below in conjunction with accompanying drawing, be example with π in the PHS system/4 DQPSK base band differential ference spirals, the enforcement of technical solution of the present invention is described in further detail.

As shown in Figure 3, this figure is the structural representation of π of the present invention/4 DQPSK demodulators, and it consists of the following components: (1) hard limiter; (2) sampling/down conversion module; (3) multiplication module; (4) extraction/filter module; (5) root raised cosine matched filter; (6) differential ference spiral/synchronization module; (7) sine and cosine table and clock module.

The present invention organically combines π/4 DQPSK demodulators and the software and radio technique that amplitude limiter adds the phase discriminator structure, forms a complete π/4 DQPSK demodulation schemes, and its concrete demodulation method will elaborate in conjunction with Fig. 4.

If the modulated intermediate frequency signal through rf analog front-end output is:

z(t)＝a(t)cos(2πf ₁t+θ _k+θ ₀)， (1)

If f1=10.8MHz in the formula (1), θ _kBe the phase modulation of k symbol period, θ ₀Be initial phase.For π/4 DQPSK modulation signals, differential phase θ _k-θ _K-1=Φ _k, Φ wherein _k∈ { π/4,3 π/4 ,-π/4 ,-3 π/4}, Φ _kClosing with hinting obliquely at of the bit that transmits is shown in the following table:

Emission bit b1 b0	Differential phase Φ k
		0 0	π/4
0 1	3π/4
		1 1	-3π/4
1 0	-π/4

10.8MHz intermediate-freuqncy signal by behind amplitude limiter, export two signals, continuous in time logical signal for having two logic levels, this logical signal with the corresponding relation of input intermediate-freuqncy signal is, when input signal amplitude is a high level greater than 0 the time, and when input signal amplitude be low level less than 0 the time.Mathematic(al) representation is:

z(t)＝sign(z(t)) (2)

Sign (x) expression is got symbolic operation to x in the formula (2).

Another output signal is the RSSI signal, and this signal has reflected the amplitude information of input signal, can be expressed as:

RSSI(t)＝abs(z(t)) (3)

So behind hard limiter, the phase place and the amplitude of input intermediate-freuqncy signal have been separated, this point can be found out by following formula:

z(t)＝abs(z(t))×sign(z(t))＝RSSI(t)× z(t) (4)

Because π/4 DQPSK adopt modulation angle carrying modulation intelligence, so, at this, only z (t) is handled and obtain beared information.

If transmitting terminal pulse-shaping filter is a rolloff-factor is the root raised cosine filter of α=0.5, then the frequency spectrum Z (ω) of z (t) is for being positioned at the band limit frequency band at f=+10.8MHz place, and its width is (1+ α) * F1.

Because hard limiter is a nonlinear device, so z (t) has produced odd high order harmonic component frequency component through the signal z (t) that exports behind the hard limiter, the frequency spectrum Z (ω) of z (t) expands on the whole frequency axis, be f=[-∞, ∞].Be expressed as follows with mathematical expression:

$\stackrel{\‾}{Z}\left(\mathrm{\ω}\right)=\underset{N=-\∞}{\overset{\∞}{\mathrm{\Σ}}}c(2n+1)Z(\mathrm{\ω}-(2n+1){\mathrm{\ω}}_1)...\left(5\right)$

Obviously, except the frequency location at f=± F1 comprises the spectrum component Z (ω) of z (t), also comprise Z (ω) among the frequency spectrum Z (ω) of z (t) in harmonic frequency (2n+1) * F1 position of F1, n=-∞ ... ,-1,0,1 ... + ∞.Although z (t) is a band-limited signal, but z (t) no longer is a band-limited signal, sampling obviously can't realize to z (t) to utilize the sampling law, so be software and radio technique to be introduced amplitude limiter add the greatest problem that the phase discriminator structure is faced to the correct sampling of z (t).Characteristics of the present invention are the correct sampling of hard-limiting signal.

In software radio architecture, the input intermediate-freuqncy signal is z (t), its frequency spectrum is for being positioned at the band-limited frequency spectrum at f=on the frequency axis ± F1 place, according to sampling thheorem, as long as sample frequency Fs＞2F1, then can be by the signal { z (k) after the sampling, k=1,2,3, complete restoring signal, the angular resolution of demodulator is not subjected to the restriction of sample rate at this moment.

For the signal z (t) after the hard-limiting, because its frequency spectrum Z (ω) expands to whole frequency axis, if with the sample rate of Fs it is sampled, then its sampling frequency spectrum is:

${\stackrel{\‾}{Z}}_S\left(\mathrm{\ω}\right)=\frac{1}{\mathrm{Ts}}\underset{m=-\∞}{\overset{\∞}{\mathrm{\Σ}}}\stackrel{\‾}{Z}(\mathrm{\ω}-m{\mathrm{\ω}}_S)...\left(6\right)$

Promptly the frequency spectrum ZS (ω) of sampling back signal is frequency displacement a plurality of stacks afterwards of the frequency spectrum Z (ω) of original signal z (t), because these frequency displacement a plurality of stacks afterwards of Z (ω) as the frequency spectrum Z (ω) of signal z (t), so, can imagine, to cause the serious aliasing of signal z (t) frequency spectrum to the sampling of signal z (t), make that subsequent treatment can't restoring signal, also restituted signal that just can't be correct.

The correct solution of this problem come from the contrary of the bandpass sample theory in the software and radio technique used, this also is one of characteristics of the present invention.The Bandpass Sampling in Software Defined Radio theorem is pointed out, if the centre frequency of bandpass signal is F1, as long as then sample frequency Fs satisfies following relation, then can be correct recover original signal accurately with Fs equal interval sampling signal:

Fs＝4F1/(2n+1) (7)

For the bandpass signal of a plurality of frequencies shown in following, can be the frequency sampling of Fs by frequency all conversely speaking:

F1＝Fs×(2n+1)/4 (8)

Although bandpass sample theory requires under sample frequency Fs, in a series of frequencies, can only there be a signal spectrum to exist by the following formula decision, otherwise can cause frequency alias, and the adjacent spectra of above-mentioned a series of frequencies is " doubling " with respect to center frequency point.

But the contrary of bandpass sample theory in the software and radio technique analyzed, be the invention provides a very important enlightenment, an approach to z (t) sampling has been pointed in this enlightenment just, and this very important enlightenment is exactly:

Satisfy under the certain condition at sample frequency Fs and signal center frequency F1 and signal spectrum, can sample simultaneously to one group of band signal with a sample rate, condition is as long as this group frequency spectrum is identical, and adjacent two frequency frequency spectrums do not have " doubling " phenomenon.

The frequency spectrum of considering z (t) just in time possesses These characteristics, that is:

1) frequency spectrum is identical on the harmonic wave frequency;

2) because harmonic component is (2n+1) F1, there is not the even number spectrum component, so, the phenomenon of adjacent two frequency frequency spectrums " doubling " in the bandpass sampling just avoided.

So spectral aliasing is not taken place for z (t) sampling is possible, how correct key be definite Fs and F1.In fact, can obtain the relation of Fs and F1 by (5) formula and (6) formula:

Fs＝mF1/(2n+1) (9)

Make that F2 is the fundamental frequency (first harmonic component) that produces behind the Fs sampling F1, then, then also need satisfy following relation between Fs and the F2 in order to guarantee that the sampling to local oscillator F2 does not produce spectral aliasing in the next unit of demodulator:

Fs＝l×F2 (10)

To system shown in Figure 4, Fs, F1, F2 value are: Fs=9.6MHz, F1=10.8MHz, F2=1.2MHz.Corresponding to m=8, n=4,1=8.

After having solved the sampling problem of z (t), the specific implementation of z (t) sampling is that d type flip flop shown in Figure 4 is finished.The input signal of d type flip flop is hard-limiting signal z (t), and sample frequency is 9.6MHz, and the fundamental frequency of d type flip flop output signal is F2=1.2MHz.D type flip flop has been finished the effect of down-conversion simultaneously except the sampling function, the fundamental component that is about to 10.8MHz among the z (t) transforms to the output signal { z (k) of d type flip flop, k=0,1,2,3, the fundamental component of F2=1.2MHz among the A}.

The output signal of d type flip flop { z (k), k=0,1,2,3, sinusoidal signal and cosine signal that A} produces with this locality respectively in multiplier 1 and multiplier 2 multiply each other, and in specific implementation shown in Figure 4, adopting frequency is sine and the cosine table sampling that realizes local oscillator in ROM of the clock reading and saving of F2.The output of multiplier 1 and multiplier 2 is respectively:

x1(k)＝ z(k)×cos(2πF2/Fs×k)，k＝0，1，2，3，Λ

x2(k)＝- z(k)×sin(2πF2/Fs×k)，k＝0，1，2，3，Λ。(11)

The sample rate of multiplier output is very high, among the embodiment as Fig. 4, the every symbol of sample rate reaches 50 times, every symbol reaches 50 times sample rate follow-up conversion speed and device (FPGA and DSP) has been proposed very high requirement, for this reason, the output of multiplier is done down-sampled processing by integer decimation/filtering extraction unit, establishes extraction factor D=10, and then integer decimation is exactly with multiplier output signal sequence x ₁(k) and x ₂(k) get one every (D-1) individual data, to form a new sequence:

x _1D(m)＝x ₁(mD)

x _2D(m)＝x ₂(mD) (12)

Because the extraction of signal causes the aliasing that extracts the back signal spectrum, so, for fear of the aliasing of the useful frequency spectrum of extraction process signal, must carry out Filtering Processing to signal before extracting.Decimation filter has multiple implementation, and as half-band filter and cic filter, adopting exponent number in the embodiment shown in fig. 4 is 10 cic filter, i.e. CIC10.

After 10 times of extractions, the sample rate of withdrawal device output signal is 5 a times/symbol, the withdrawal device output signal enters the reception matched filter: root raised cosine filter RRCF1 and RRCF2, for π/4 DQPSK demodulators based on the PHS standard, the roll-off factor of root raised cosine filter RRCF1 and RRCF2 is 0.5, and to the π/4 DQPSK demodulators based on the PCS standard, the roll-off factor of root raised cosine filter RRCF1 and RRCF2 is 0.3.In demodulator embodiment shown in Figure 4, the parameter of root raised cosine filter is that roll-off factor is 0.5, and sample rate is 5 a times/symbol, and filter length is 31, and structure adopts the FIR filter.

Because receive matched filter introducing herein, the filter of receiving filter and transmitting terminal synthesizes raised cosine filter, in the sampling instant of the best, intersymbol interference is eliminated, and the demodulator angular resolution improves, and the error rate reduces.

After receiving matched filter, intersymbol interference is eliminated, and signal enters differential ference spiral/synchronization module, and synchronization module is mainly realized two functions: 1) optimum sampling is estimated constantly; 2) frequency offset estimating and compensation.

After receiving matched filter, each symbol still has 5 times sample rate, in each sampled point, only in the sampling instant (sampled point) of the best, the intersymbol interference minimum of signal, so optimum sampling estimates to realize by the sampling instant restore circuit symbol sampler of no intersymbol interference constantly, it is output as sample/symbol 1 time.The algorithm that the sampling instant restore circuit is commonly used comprises M﹠amp; The M algorithm, Gardner algorithm and adverse modulation loop structure (referring to " digital communication, John G.Proakis work, Electronic Industry Press ") adopt the Gardner algorithm in Fig. 4.

Frequency offset estimating and compensation mainly solve receiving terminal and the inconsistent problem of transmitting terminal frequency, with the PHS system is example, for the PHS system that is operated in the 1.9GHz frequency range, if the frequency stability of PHS mobile phone (transmitter) is 3ppm, then the frequency deviation of sending and receiving end can reach 6KHz, must estimate this frequency deviation at receiving terminal, then with compensate of frequency deviation, could guarantee the operate as normal of demodulator, frequency offset estimating commonly used and collocation structure have forward direction structure (Feed forwards) and back to structure (Back forwards), frequency deviation estimating method has data auxiliary (DA:Data Aided) and auxiliary (NDA:Non DataAided) two classes of non-data (referring to " digital communication, John G.Proakis work, the Electronic Industry Press ").Adopt the NDA method of forward direction structure (Feed forwards) in the realization of Fig. 4.

Make differential ference spiral through the data synchronously, establish through the two paths of signals up and down behind the synchronization module and be respectively y ₁(i) and y ₂(i), i=1,2,3, Λ, then calculus of differences is:

u(i)＝y ₁(i)*y ₁(i-1)+y ₂(i)*y ₂(i-1)

v(i)＝y ₂(i)*y ₁(i-1)-y ₁(i)*y ₂(i-1) (13)

The calculus of differences result can recover π/4 DQPSK modulation intelligence bit B1B2 by following criterion:

If u (i)＞0, then B1=1; U (i)＜0, then B1=0;

If v (i)＞0, then B2=1; V (i)＜0, then B2=0.

So far, π/4 DQPSK demodulation are finished.

Fig. 5 is under Fig. 4 execution mode, is under the 100dB condition in signal to noise ratio, the output planisphere of demodulator FPGA.As can be seen, angular resolution was not subjected to the restriction of sample frequency when the angular resolution of demodulator added the phase discriminator structure as amplitude limiter, because at F2=1.2MHz, under the situation of Fs=9.6MHz, the demodulator angular resolution that amplitude limiter adds the phase discriminator structure is 45 degree.And to frequency F1=10.8MHz, symbol rate is 192Kb/s, and sampling clock is the PHS system of Fs=9.6MHz, and π of the present invention/4 DQPSK demodulators show with the FPGA result of implementation, the angular resolution of demodulator reaches the angle requirement of PHS antenna system ± 5 degree less than ± 5 degree.

Claims (24)

1. π/4DQPSK demodulator is applied to it is characterized in that in the mobile communcations system, adopts amplitude limiter to add phase discriminator structure and software radio architecture mixed form, comprises following several sections:

(1) hard limiter is used for continuous logical signal of output time and signal intensity indication signal RSSI;

(2) sampling/down conversion module is used for the frequency spectrum of the logical signal of hard limiter output is sampled, and its fundamental component is carried out conversion;

(3) multiplication module is used for sampled signal and local sinusoidal signal and the cosine signal that produces are multiplied each other, and realizes the sampling of local oscillator;

(4) extraction/filter module is used for down-sampled processing is done in multiplication module output;

(5) root raised cosine matched filter, the filter that is used for receiving filter and transmitting terminal synthesizes raised cosine filter, in the sampling instant of the best, eliminates intersymbol interference;

(6) differential ference spiral/synchronization module is used to carry out optimum sampling estimation constantly and frequency offset estimating and compensation;

(7) sine and cosine table and clock module, sine and cosine table are used to described multiplier that the cosine and sine signal of quadrature is provided, and clock module provides essential clock for all the other modules of described demodulator.

2. π as claimed in claim 1/4DQPSK demodulator, it is characterized in that, described logical signal has two logic levels, with the corresponding relation of input intermediate-freuqncy signal be, when input intermediate-freuqncy signal amplitude is a high level greater than 0 the time, and when input intermediate-freuqncy signal amplitude be low level less than 0 the time, mathematic(al) representation is: z (t)=sign (z (t)) sign (x) expression is got symbolic operation to x.

3. π as claimed in claim 2/4DQPSK demodulator is characterized in that, the frequency spectrum of described logical signal frequency spectrum on the harmonic wave frequency is identical, harmonic component is (2n+1) F1, n=-∞, ,-1,0,1 ... + ∞, F1 is the centre frequency of input intermediate-freuqncy signal.

4. as claim 2 or 3 described π/4DQPSK demodulators, it is characterized in that, the spectral sample frequency Fs of described logical signal and the pass of signal center frequency F1 and signal spectrum are: Fs=mF1/ (2n+1), simultaneously, Fs=l * F2, F2 is the fundamental frequency that produces behind the Fs sampling F1, and m, l are non-vanishing positive integer.

5. π as claimed in claim 1/4DQPSK demodulator is characterized in that described hard limiter can be logarithmic amplifier.

6. π as claimed in claim 1/4DQPSK demodulator is characterized in that, before the described extraction signal is carried out Filtering Processing.

7. π as claimed in claim 1/4DQPSK demodulator is characterized in that described sampling/down conversion module can be d type flip flop.

8. π as claimed in claim 1/4DQPSK demodulator is characterized in that described extraction/filter module can be half-band filter and cic filter.

9. π as claimed in claim 2/4DQPSK demodulator is characterized in that, described optimum sampling estimates to realize by the sampling instant restore circuit symbol sampler of no intersymbol interference constantly.

10. π as claimed in claim 2/4DQPSK demodulator is characterized in that, described frequency offset estimating makes receiving terminal consistent with the transmitting terminal frequency with compensation.

11. the demodulation method of π/4DQPSK demodulator is characterized in that, comprises that step is as follows:

(1) the analog intermediate frequency continuous signal of receiving terminal changes the logical signal and the signal intensity indication signal RSSI of two level into through hard limiter;

(2) logical signal of hard limiter output is sampled through over-sampling/low-converter, and realizes that simultaneously the first harmonic frequency of logical signal is F2 from the F1 down conversion;

(3) logical signal after the sampling multiplies each other through multiplier and cosine and sine signal, to realize the frequency spectrum translation conversion;

(4) signal of the frequency spectrum translation conversion by multiplier output extracts to finish sampling rate conversion through extractions/filter, with the sample rate reduction, makes follow-up unit promptly receive the designs simplification of root raised cosine matched filter;

(5) signal of Chou Quing carries out matched filtering by root raised cosine reception matched filter on lower sample rate, eliminates intersymbol interference;

(6) receive the signal process differential ference spiral/synchronization module of matched filter output to estimating owing to the inconsistent frequency deviation that causes of sending and receiving end frequency and compensating, simultaneously, determine the optimum sampling moment of judgement, carry out calculus of differences and judgement then, thereby finished π/4DQPSK signal demodulation.

12. the demodulation method of π as claimed in claim 11/4DQPSK demodulator, it is characterized in that, in the described step (1), described logical signal has two logic levels, with the corresponding relation of input intermediate-freuqncy signal be, when input intermediate-freuqncy signal amplitude is a high level greater than 0 the time, and when input intermediate-freuqncy signal amplitude be low level less than 0 the time, mathematic(al) representation is: z (t)=sign (z (t)) sign (x) represents x is got symbolic operation.

13. the demodulation method of π as claimed in claim 11/4DQPSK demodulator is characterized in that, in the described step (2), signals sampling/low-converter sampling can realize by d type flip flop.

14. the demodulation method of π as claimed in claim 11/4DQPSK demodulator is characterized in that, in the described step (4), signal also comprised the step of signal being carried out Filtering Processing before extraction/filter extracts.

15. the demodulation method of π as claimed in claim 11/4DQPSK demodulator is characterized in that, the frequency spectrum of described logical signal frequency spectrum on the harmonic wave frequency is identical, harmonic component is (2n+1) F1, n=-∞, ,-1,0,1 ... + ∞, F1 is the centre frequency of input intermediate-freuqncy signal.

16. the demodulation method as claim 11 or 15 described π/4DQPSK demodulators is characterized in that, the spectral sample frequency Fs of described logical signal and the pass of signal center frequency F1 and signal spectrum are:

Fs=mF1/ (2n+1), simultaneously, Fs=l * F2, F2 are the fundamental frequency that produces behind the Fs sampling F1, m, l are non-vanishing positive integer.

17. the demodulation method of π as claimed in claim 11/4DQPSK demodulator is characterized in that described hard limiter can be logarithmic amplifier.

18. the demodulation method of π as claimed in claim 11/4DQPSK demodulator is characterized in that described sampling/down conversion module can be d type flip flop.

19. the demodulation method of π as claimed in claim 11/4DQPSK demodulator is characterized in that described extraction/filter module can be half-band filter and cic filter.

20. π as claimed in claim 11/4DQPSK demodulator is characterized in that, described frequency offset estimating makes receiving terminal consistent with the transmitting terminal frequency with compensation.

21. the demodulation method of π as claimed in claim 11/4DQPSK demodulator is characterized in that, in the described step (6), optimum sampling is estimated to realize by the sampling instant restore circuit constantly.

22. the demodulation method of π as claimed in claim 11/4DQPSK demodulator is characterized in that, the described moment estimates to realize by the sampling instant restore circuit symbol sampler of no intersymbol interference.

23. the demodulation method of π as claimed in claim 11/4DQPSK demodulator is characterized in that, in the described step (6), frequency offset estimating and collocation structure comprise that forward direction structure and back are to structure.

24. the demodulation method of π as claimed in claim 11/4DQPSK demodulator is characterized in that, described frequency deviation estimating method comprises auxiliary and auxiliary two classes of non-data of data.

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