CN1516279A

CN1516279A - Film transistor array and its driving circuit structure

Info

Publication number: CN1516279A
Application number: CNA031016332A
Authority: CN
Inventors: 陈信铭
Original assignee: Toppoly Optoelectronics Corp
Current assignee: TPO Displays Corp
Priority date: 2003-01-10
Filing date: 2003-01-10
Publication date: 2004-07-28
Anticipated expiration: 2023-01-10
Also published as: CN1293632C

Abstract

The invention relates to a film transistor array and its drive circuit structure, set in a base plate and mainly composed of many scanning wirings, signal wirings, film transistors, pixel electrodes, memory capacitors and CMOS transistors. The film transistor is mainly composed of a polycrystal silicon layer on the base plate, a source/drawer above the olycrystal silicon, an N plus doped film between the polycrystal silicon layer and the source/drawer, a gate above the polycrystal silicon and a gate insulating layer between the polycrystal silicon and the gate.

Description

Thin film transistor (TFT) array and driving circuit structure thereof

Technical field

The present invention relates to a kind of thin film transistor (TFT) array and driving circuit structure thereof, and particularly a kind of thin film transistor (TFT) array and the driving circuit structure thereof that can finish with six road light shield processing procedures.

Background technology

At improving rapidly of multimedia society, be indebted to the leap progress of semiconductor element or man-machine display device mostly.With regard to display, (Cathode Ray Tube CRT) because of having excellent display quality and its economy, monopolizes monitor market in recent years to cathode ray tube always.Yet, operate the environment of most terminating machine/display equipments on the table for the individual, or with the incision of the viewpoint of environmental protection, if predicted cathode ray tube because of still there being a lot of problems in space utilization and the energy resource consumption with the trend of saving the energy, and the method for solution can't effectively be provided for the demand of light, thin, short, little and low consumpting power.Therefore, have that high image quality, space utilization efficient are good, the Thin Film Transistor-LCD (TFT-LCD) of low consumpting power, advantageous characteristic such as radiationless becomes the main flow in market gradually.

Our known thin-film transistor can be divided into two kinds of amorphous silicon thin-film transistor and polysilicon thin-film transistors haply.Low temperature poly-silicon (LTPS) (LTPS) technology is different from general traditional amorphous silicon (a-Si) technology, its electron mobility can reach more than the 200cm2/V-sec, therefore can make the size of thin-film transistor littler, have the aperture opening ratio (aperture ratio) that increases display, reduce function such as power consumption.In addition, the low temperature poly-silicon (LTPS) processing procedure can be manufactured in the part drive circuit on the substrate in company with the thin-film transistor processing procedure in the lump, significantly promotes the characteristic and the reliability of display panels, so manufacturing cost significantly reduces.

Fig. 1 (A) illustrates profile into existing thin film transistor (TFT) array and drive circuit processing procedure to Fig. 1 (H).Please refer to Figure 1A, one substrate 100 at first is provided, and on substrate 100, form a polysilicon layer (polysilicon layer), then define this polysilicon layer, so that it forms

island structure

102a, 102b, the 102c of a plurality of polysilicon materials with the first road light shield processing procedure (Mask 1).

Island structure 102a is in order to formation thin-film transistor (TFT), and island structure 102b and island structure 102c are in order to form drive circuit, as complementary metal oxide semiconductor (CMOS).Because island structure 102a is that so island structure 102a normally is arranged on the substrate 100 with array way, island structure 102b and island structure 102c then normally are disposed at edge or other zones of substrate 100 in order to the formation thin-film transistor.

Then please refer to Fig. 1 (B), on the substrate 100 that is formed with

island structure

102a, 102b, 102c, form one first dielectric layer 104 and a conductor layer (not painting among the figure) in regular turn.Then define this conductor layer with the second road light shield processing procedure (Mask 2) again, on

island structure

102a, 102b, 102c, forming

gate

106a, 106b, 106c respectively, and on the appropriate location of substrate 100, form the bottom electrode 108 of reservior capacitor.

Then please refer to Fig. 1 (C),,, and in island structure 102c, form N+ doped region 112 with formation N+ doped region 110 in island structure 102a with the position of the 3rd road light shield processing procedure (Mask 3) decision N+ doped region 110,112.Wherein, the N+ doped region 110 among the island structure 102a is the both sides that are distributed in gate 106a, and the N+ doped region 112 among the island structure 102c then is the both sides that are distributed in gate 106c.

Then please refer to Fig. 1 (D), then,, and in island structure 102c, form N-doped region 116 with formation N-doped region 114 in island structure 102a with the position of the 4th road light shield processing procedure (Mask 4) decision N-doped region.Wherein, the N-doped region 114 among the island structure 102a is to be distributed between gate 106a and the N+ doped region 110, and the N-doped region 116 among the island structure 102c then is to be distributed between gate 106c and the N+ doped region 112.

Then please refer to Fig. 1 (E), with the position of the 5th road light shield processing procedure (Mask 5) decision P+ doped region, in island structure 102b, to form P+ doped region 118.Wherein, the P+ doped region 110 among the island structure 102b is the both sides that are distributed in gate 106b.

Then please refer to Fig. 1 (F), forming one second dielectric layer 120 is covered on the substrate 100, then with the 6th road light shield processing procedure (Mask 6) definition first dielectric layer 104 and second dielectric layer 120, to determine the pattern of first dielectric layer 104 and second dielectric layer 120.

Have opening 122a, opening 122b and opening 122c in first dielectric layer 104 and second dielectric layer 120.Wherein, opening 122a exposes N+ doped region 110, and opening 122b exposes P+ doped region 118, and opening 122c exposes N+ doped region 112.

Then please refer to Fig. 1 (G), form a conductor layer (not painting among the figure) and be covered on second dielectric layer 120, then define above-mentioned conductor layer to form source/drain 124 with the 7th road light shield processing procedure (mask 7) again.Wherein, source/drain 124 is to expose with N+ doped region 110, P+ doped region 118 respectively by opening 122a, opening 122b and opening 122c and N+ doped region 112 electrically connects.

Then please refer to Fig. 1 (H), form a flatness layer 126 and be covered on the substrate 100 that is formed with source/drain 124, then again with the 8th road light shield processing procedure (Mask 8) definition flatness layer 126, with the pattern of decision flatness layer 126.Wherein, flatness layer 126 has opening 128, and this opening 128 is in order to source/drain 124a is exposed.

After with the 8th road light shield processing procedure (Mask 8) definition flatness layer 126, then can form a conductive layer (not painting among the figure) on substrate 100, this conductive layer is transparent material such as tin indium oxide normally.At last again with the above-mentioned conductive layer of the 9th road light shield processing procedure (Mask 9) definition, to form pixel electrode 130.

Please refer to Fig. 1 (H) equally, can be learnt by Fig. 1 (H) left side, N-doped region 116 among the island structure 102c and N+ doped region 112, gate 106c and source/drain 124c constitute a N type metal-oxide-semiconductor (MOS) (NMOS).P+ doped region 118 among the island structure 102b, gate 106b and source/drain 124b constitute a P type metal-oxide-semiconductor (MOS) (PMOS).And can constitute a complementary metal oxide semiconductor (CMOS) by above-mentioned N type metal-oxide-semiconductor (MOS) (NMOS) and P type metal-oxide-semiconductor (MOS) (PMOS), this complementary metal oxide semiconductor (CMOS) institute's role on panel is a built-in drive circuit (driving circuit), in order to driving Fig. 1 H right side thin-film transistor (TFT), and then the demonstration of control picture element.

Can learn that by Fig. 1 (H) right side N-doped region 110 among the island structure 102a and N+ doped region 114, gate 106a and source/drain 124a are the thin-film transistors (Poly-TFT) that constitutes a polysilicon kenel.Wherein, thin-film transistor is controlled the data (data) that writes pixel electrode 130 by the driving of above-mentioned complementary metal oxide semiconductor (CMOS).

Fig. 2 illustrates the making flow chart into existing thin film transistor (TFT) array and drive circuit.Please refer to Fig. 2, the making flow process of existing thin film transistor (TFT) array and drive circuit mainly is by definition polysilicon layer S200, definition Zha Ji ﹠amp; Pattern S210, the definition Yuan Ji/Ji Ji ﹠amp of the bottom electrode S202 of storage capacitors, definition N+ doped region S204, definition N-doped region S206, definition P+ doped region S208, definition first dielectric layer; The pattern S214 of the top electrode S212 of storage capacitors, definition second dielectric layer, and the steps such as pattern S216 of definition pixel electrode constitute.

Existing thin film transistor (TFT) array and driving circuit structure thereof, light shield number required on making is more, needs eight roads (not comprising the making of N-doped region 114,116) or nine road light shield processing procedures to finish usually, makes that the processing procedure cost is difficult to reduce.In addition, because required light shield number is more, the time that makes panel make can't effectively shorten, and yield is difficult to promote.

Summary of the invention

The objective of the invention is to propose a kind of thin film transistor (TFT) array and driving circuit structure thereof, it only needs can complete with six road light shield processing procedures.

For reaching above-mentioned purpose of the present invention, a kind of thin film transistor (TFT) array and driving circuit structure thereof are proposed, be suitable for being disposed on the substrate, it is made of a plurality of scan wirings, a plurality of signal wiring, a plurality of thin-film transistor, a plurality of pixel electrode, a plurality of storage capacitors and a plurality of complementary gold oxygen semitransistor.

Among the present invention, thin-film transistor mainly is by a polysilicon layer, one source pole/drain, a N+ doping film, a gate and a gate insulation layer.Wherein, the polysilicon layer is to be disposed on the substrate, and source/drain is disposed at the polysilicon top, and the N+ doping film is disposed between polysilicon layer and the source/drain, and gate is disposed at the polysilicon top, and gate insulation layer then is disposed between polysilicon and the gate.

Among the present invention, pixel electrode and storage capacitors are to be disposed on the substrate corresponding to thin-film transistor.

Among the present invention, complementary metal oxide semiconductor is made of a N type metal-oxide-semiconductor (MOS) and a P type metal-oxide-semiconductor (MOS).N type metal-oxide-semiconductor (MOS) is made of a polysilicon layer, one source pole/drain, a N+ doping film, a gate and a gate insulation layer.Wherein, the polysilicon layer is disposed on the substrate, and source/drain is disposed at the polysilicon top, and the N+ doping film is disposed between polysilicon and the source/drain, and gate is disposed at the polysilicon top, and gate insulation layer then is disposed between polysilicon layer and the gate.

In addition, in the N type metal-oxide-semiconductor (MOS), more comprise a N-doped region in the polysilicon layer between gate and source/drain.

P type metal-oxide-semiconductor (MOS) is made of a polysilicon layer, one source pole/drain, a P+ doping film, a gate and a gate insulation layer.Wherein, the polysilicon layer is disposed on the substrate, and source/drain is disposed at the polysilicon top, and the P+ doping film is disposed between polysilicon and the source/drain, and gate is disposed at the polysilicon top, and gate insulation layer then is disposed between polysilicon layer and the gate.

Above-mentioned gate insulation layer is made of at least one first dielectric layer, and wherein, the material of first dielectric layer for example is oxidation silicon, silicon nitride, hydrogeneous dielectric layer etc.In addition, gate insulation layer also can be made of at least one first dielectric layer and one second dielectric layer, and wherein, the material of first dielectric layer comprises oxidation silicon, silicon nitride, hydrogeneous dielectric layer etc., and the material of second dielectric layer for example is a photoresist.

Among the present invention, the material of gate for example is aluminium/molybdenum, aluminium/titanium etc., and the material of source/drain for example is aluminium/molybdenum, molybdenum etc.

At the penetration panel, the material of conductor layer can be selected transparent conductors such as tin indium oxide for use.At reflective panel, the material of conductor layer can select for use metal etc. to have the material of good reflection characteristic.In addition, be example with reflective panel, the surface of conductor layer (being generally the metal with good reflection ability) below protective layer is a concavo-convex surface for example, to promote the effect of conductor layer reflection ray.

For above-mentioned purpose of the present invention, feature and advantage can be become apparent, especially exemplified by a preferred embodiment, and cooperate appended graphicly, be described in detail below.

Description of drawings

Fig. 1 (A) is to the profile of Fig. 1 (H) for existing thin film transistor (TFT) array and drive circuit processing procedure;

Fig. 2 is the making flow chart of existing thin film transistor (TFT) array and drive circuit;

Fig. 3 (A) to Fig. 3 (I) be profile according to a preferred embodiment of the present invention thin film transistor (TFT) array and drive circuit processing procedure;

Fig. 4 is the making flow chart according to a preferred embodiment of the present invention thin film transistor (TFT) array and drive circuit;

Fig. 5 is according to the layout of a preferred embodiment of the present invention complementary metal oxide semiconductor (CMOS) (layout) schematic diagram; And

Fig. 6 is the schematic layout pattern according to a preferred embodiment of the present invention picture element.

Embodiment

Fig. 3 (A) to Fig. 3 (I) be profile according to a preferred embodiment of the present invention thin film transistor (TFT) array and drive circuit processing procedure.Please refer to Fig. 3 (A), one substrate 300 at first is provided, and on substrate 300, form a polysilicon layer and a N+ doping film in regular turn, then above-mentioned polysilicon layer and the N+ doping film of one first road light shield processing procedure (Mask 1) definition a plurality ofly piles up the island structure that forms by

polysilicon layer

302a, 302b, 302c and

N+ doping film

304a, 304b, 304c to form.

The generation type of above-mentioned polysilicon layer for example is to form an amorphous silicon film (a-Si) earlier on substrate 300, then again this amorphous silicon layer is carried out a quasi-molecule laser tempering manufacturing process (ExcimerLaser Annealing, ELA), so that amorphous silicon layer crystallization becoming polysilicon layer.And the formation method of N+ doping film for example is directly to have the amorphous silicon film of N+ doping on substrate 300 with long-pending mode Shen long-pending one, chemical gaseous phase Shen; Or form earlier an amorphous silicon film on substrate 300, after again this amorphous silicon is carried out N type ion doping, to form the N+ doping film.

Island structure 302a is in order to formation thin-film transistor (TFT), and island structure 302b and island structure 302c are in order to form drive circuit, as complementary metal oxide semiconductor (CMOS).Because island structure 302a is that so island structure 302a is arranged on the substrate 300 with array way, island structure 302b and island structure 302c then for example are edge or other zones that is disposed at substrate 300 in order to the formation thin-film transistor.

Then please refer to Fig. 3 (B) and Fig. 3 (C), with the position of the second road light shield processing procedure (Mask 2) decision P+ doped region 306, by the action of the doping of P type ion in the Zone Full (illustrating) of N+ doping film 304b or formation P+ doped region 306 in the zone (illustrating) partly as Fig. 3 (C) as Fig. 3 (B).

Then please refer to Fig. 3 (D), on substrate 300, form one first conductor layer (not illustrating among the figure), then again with the first above-mentioned conductor layer of the 3rd road light shield processing procedure (Mask 3) definition, on N+ doping film 304a, P+ doped region 306 and N+ doping film 304c, to form source/

drain

308a, 308b, 308c respectively.And on the appropriate location of substrate 300, form the bottom electrode 310 of reservior capacitor.

Yet when definition first conductor layer, the 3rd road light shield processing procedure can define

N+ doping film

304a, 304b, 304c or the P+ doped region 306 (shown in Fig. 3 (B), 3 (C)) that is positioned at first conductor layer below simultaneously.Therefore, source/drain 308a can have identical pattern with the N+ doping film 304a under it; Source/drain 308b can have identical pattern with the P+ doped region 306 under it; And source/drain 308c also can have identical pattern with the N+ doping film 304c under it.

Then please refer to Fig. 3 (E), on substrate 300, form one first dielectric layer (not illustrating among the figure) and one second conductor layer (not illustrating among the figure) in regular turn, then with the 4th road light shield processing procedure (Mask 4) the above-mentioned dielectric layer of definition and second conductor layer, on

polysilicon layer

302a, 302b, 302c, to form the stacked structure of

gate insulation layer

312a, 312b, 312c and

gate

314a, 314b, 314c respectively.

In the present embodiment,

gate insulation layer

312a, 312b, 312c for example can carry out a Rapid Thermal processing procedure (Rapid Thermal Process to

gate insulation layer

312a, 312b, 312c after forming, RTP), so that the quality of

gate insulation layer

312a, 312b, 312c more promotes.

Gate insulation layer

312a, 312b, 312c are made of at least one first dielectric layer, and wherein the material of first dielectric layer for example is oxidation silicon, silicon nitride, hydrogeneous dielectric layer etc.And

gate insulation layer

312a, 312b, 312c also can be made of at least one first dielectric layer and one second dielectric layer, wherein the material of first dielectric layer comprises oxidation silicon, silicon nitride, hydrogeneous dielectric layer etc., and the material of second dielectric layer for example is a photoresist.In addition, the material of

gate

314a, 314b, 314c for example is aluminium/molybdenum, aluminium/titanium etc., and the material of source/

drain

308a, 308b, 308c for example is aluminium/molybdenum, molybdenum etc.

Please refer to Fig. 3 (E) equally, can form a dielectric layer 316 and a top electrode 318 on bottom electrode 310 in the 4th road light shield processing procedure (Mask 4), bottom electrode 310, dielectric layer 316 and top electrode 318 promptly constitute a reservior capacitor.In addition, can on the appropriate location of substrate 300, form the stacked structure of dielectric layer 320 and distribution 322 in the 4th road light shield processing procedure (Mask 4).

Yet, have the knack of the production order that should be able to understand

gate

314a, 314b, 314c and source/

drain

308a, 308b, 308c easily of this technology and can adjust to some extent in response to processing procedure.Just, do not limit the production order of source/

drain

308a, 308b, 308c and

gate

314a, 314b, 314c in the present embodiment.

Then please refer to Fig. 3 (F), form a protective layer 324 on substrate 300, then again with the 5th road light shield processing procedure (Mask 5) definition protective layer 324, with the pattern of decision protective layer 324.For example have opening 326a, 326b, 326c, 326d, 326e in the protective layer 324.Wherein, opening 326a is in order to source/drain 308a is exposed, opening 326b is in order to source/drain 308b is exposed, opening 326c is in order to source/drain 308c is exposed, opening 326d exposes in order to the top electrode 318 with reservior capacitor, and opening 326e is in order to distribution 322 is exposed.

Then please refer to Fig. 3 (G), after with the 5th road light shield processing procedure (Mask 5) definition protective layer 324, then form a conductive layer (not illustrating among the figure) on substrate 300, this conductive layer is transparent material such as tin indium oxide normally.At last again with the above-mentioned conductive layer of the 6th road light shield processing procedure (Mask 6) definition, to form lead 328 and pixel electrode 330.

Then please refer to Fig. 3 (H) and Fig. 3 (I), it illustrates with Fig. 3 (F) and 3 (G) similar, and for its difference is that one is penetration panel (Fig. 3 (H) and Fig. 3 (I)), and another is reflective panel (Fig. 3 (F) and Fig. 3 (G)).Protective layer 324 among Fig. 3 (H) and Fig. 3 (I) has a convex-concave surface 332, and the pixel electrode 334 that is disposed on the convex-concave surface 332 for example is to select for use some to have the conductor of good result.Can promote the effect of pixel electrode 334 (reflecting electrode) reflection ray by the convex-concave surface on the protective layer 324 332.

Then please be simultaneously with reference to Fig. 3 (G) and Fig. 3 (I), can learn that by Fig. 3 (G) and Fig. 3 (I) left side polysilicon layer 302c, N+ doping film 304c, source/drain 308c, gate insulation layer 312c and gate 314c constitute a N type metal-oxide-semiconductor (MOS) (NMOS).Polysilicon layer 302b, P+ doping film 306, source/drain 308b, gate insulation layer 312b and gate 314b constitute a P type metal-oxide-semiconductor (MOS) (PMOS).And can constitute a complementary metal oxide semiconductor (CMOS) by above-mentioned N type metal-oxide-semiconductor (MOS) (NMOS) and P type metal-oxide-semiconductor (MOS) (PMOS), this complementary metal oxide semiconductor institute's role on panel is a built-in drive circuit, in order to driving Fig. 3 (G) and Fig. 3 (I) right side thin-film transistor, and then the demonstration of control picture element.

Can learn that by Fig. 3 (G) and Fig. 3 (I) right side polysilicon layer 302a, N+ doping film 304a, source/drain 308a, gate insulation layer 312a and gate 314a are the thin-film transistors that constitutes a polysilicon kenel.Wherein, thin-film transistor is to control the data that writes in pixel electrode 330 or the pixel electrode 334 by the driving of above-mentioned complementary metal oxide semiconductor.

Fig. 4 illustrates and is the making flow chart according to a preferred embodiment of the present invention thin film transistor (TFT) array and drive circuit.Please refer to Fig. 4, the making flow process of present embodiment thin film transistor (TFT) array and drive circuit mainly is by definition polysilicon layer S400, definition P+ doped region S402, definition Yuan Ji/Ji Ji ﹠amp; N+ doping film Hui Shi ﹠amp; The bottom electrode S404 of storage capacitors, definition Zha Ji ﹠amp; The pattern S408 of the top electrode S406 of storage capacitors, definition protective layer, and definition Hua Sudianji ﹠amp; Steps such as the pattern S410 of lead constitute.Need six road light shield processing procedures altogether by S400 to S410.Yet,, need to increase again the light shield processing procedure one if make N-doped region (lightly doped region) in the N type metal-oxide-semiconductor (MOS) (NMOS) in drive circuit.

Fig. 5 illustrates and is the schematic layout pattern according to complementary metal oxide semiconductor in a preferred embodiment of the present invention drive circuit.Please refer to Fig. 5, apply voltage Vin, Vdd and Vss respectively on contact 504,506 and 508, because contact 504 electrically connects with gate 500 and gate 502, therefore in order to the conducting of control N type metal-oxide-semiconductor (MOS) and P type metal-oxide-semiconductor (MOS) channel layer whether the Vin that puts on the contact 504 can be, and the conducting of N type metal-oxide-semiconductor (MOS) and P type metal-oxide-semiconductor (MOS) channel layer with otherwise can directly have influence on the output Vout of complementary metal oxide semiconductor by contact 510, and by the Vout value of contact 510 output may for Vdd or Vss one of them.

Yet, the drive circuit that is illustrated among Fig. 5 only is the schematic layout pattern of one complementary metal oxide semiconductor unit, and the drive circuit that should be able to understand on the panel of haveing the knack of this technology can be arranged in pairs or groups other circuit or element and constituted by above-mentioned complementary metal oxide semiconductor, to drive the pixel array on the panel.

Fig. 6 illustrates and is the schematic layout pattern according to a preferred embodiment of the present invention picture element.Please refer to Fig. 6, comprise that mainly one scan distribution 600, a signal wiring 602, a thin-film transistor 604, a reservior capacitor 606 and a pixel electrode 330 (334) are constituted to the produced image element structure of six road light shield processing procedures of Fig. 3 (I) by above-mentioned Fig. 3 (A).Wherein, thin-film transistor 604 is made of polysilicon layer 302a, gate 314a, N+ doping film 304a and source/drain 308a.In addition, scan wiring 600 is connected with gate 314a in the thin-film transistor 604, to control the switch of its lower channel layer (polysilicon layer 302a), the data of desiring to write then is to write in the pixel electrode 330 (334) via the control of signal wiring 602 transmission and thin-film transistor 604.

In sum, thin film transistor (TFT) array of the present invention and driving circuit structure thereof have following advantage at least:

1. thin film transistor (TFT) array of the present invention and driving circuit structure thereof only need six road light shields to finish on making, and its cost of manufacture is significantly reduced.

2. thin film transistor (TFT) array of the present invention and driving circuit structure thereof, its employed light shield number when making is less, and the time that makes panel make shortens many.

3. thin film transistor (TFT) array of the present invention and driving circuit structure thereof, its employed light shield number on making is less, helps the lifting of panel acceptance rate.

Though the present invention discloses as above with a preferred embodiment, so it is not in order to limit the present invention.

Claims

1. thin film transistor (TFT) array and driving circuit structure thereof are suitable for being disposed on the substrate, it is characterized in that this structure comprises:

A plurality of scan wirings are disposed on this substrate;

A plurality of signal wirings are disposed on this substrate;

Plurality of films transistor, those thin-film transistors are to drive by those scan wirings and those signal wirings, and each those thin-film transistor comprises:

One polysilicon layer is disposed on this substrate;

One source pole/drain is disposed at this polysilicon top;

One N+ doping film, be disposed at this polysilicon layer and this source/drain between;

One gate is disposed at this polysilicon top;

One gate insulation layer, be disposed at this polysilicon and this gate between;

A plurality of pixel electrodes, dispose corresponding to those thin-film transistors:

A plurality of storage capacitors are corresponding to those pixel electrode configurations; And

A plurality of complementary metal oxide semiconductors, each those complementary metal oxide semiconductor comprise a N type metal-oxide-semiconductor (MOS) and a P type metal-oxide-semiconductor (MOS).

2. thin film transistor (TFT) array as claimed in claim 1 and driving circuit structure thereof is characterized in that, described N type metal-oxide-semiconductor (MOS) comprises:

One second polysilicon layer is disposed on this substrate;

One second source/drain is disposed at this second polysilicon top;

One the 2nd N+ doping film, be disposed at this second polysilicon and this second source/drain between;

One second gate is disposed at this second polysilicon top; And

One second gate insulation layer, be disposed at this second polysilicon layer and this second gate between.

3. thin film transistor (TFT) array as claimed in claim 1 and driving circuit structure thereof is characterized in that, more comprise a N-doped region in this polysilicon layer between described gate and this source/drain.

4. thin film transistor (TFT) array as claimed in claim 1 and driving circuit structure thereof is characterized in that, described P type metal-oxide-semiconductor (MOS) comprises:

One the 3rd polysilicon layer is disposed on this substrate;

One the 3rd source/drain is disposed at the 3rd polysilicon top;

One P+ doping film, be disposed at the 3rd polysilicon and the 3rd source/drain between;

One the 3rd gate is disposed at the 3rd polysilicon top; And

One the 3rd gate insulation layer, be disposed at the 3rd polysilicon layer and the 3rd gate between.

5. thin film transistor (TFT) array as claimed in claim 1 and driving circuit structure thereof is characterized in that described gate insulation layer comprises a dielectric layer, and the material of this dielectric layer comprise oxidation silicon, silicon nitride, hydrogeneous dielectric layer wherein one.

6. thin film transistor (TFT) array as claimed in claim 1 and driving circuit structure thereof is characterized in that, described gate insulation layer comprises:

One first dielectric layer; And

One second dielectric layer is disposed on this first dielectric layer.

7. thin film transistor (TFT) array as claimed in claim 6 and driving circuit structure thereof, it is characterized in that, the material of described first dielectric layer comprise oxidation silicon, silicon nitride, hydrogeneous dielectric layer one of them, and the material of this second dielectric layer comprises a photoresist.

8. thin film transistor (TFT) array as claimed in claim 1 and driving circuit structure thereof is characterized in that, the material of described gate comprise aluminium/molybdenum, aluminium/titanium one of them.

9. thin film transistor (TFT) array as claimed in claim 1 and driving circuit structure thereof is characterized in that, the material of described source/drain comprise aluminium/molybdenum, molybdenum one of them.

10. thin film transistor (TFT) array as claimed in claim 1 and driving circuit structure thereof is characterized in that, described pixel electrode is to be a transparency electrode, and the material of this pixel electrode comprises tin indium oxide.

11. thin film transistor (TFT) array as claimed in claim 1 and driving circuit structure thereof is characterized in that, described pixel electrode is to be a reflecting electrode, and the material of this pixel electrode comprises metal.