CN100345310C - Thin-film transistor and method for making same - Google Patents
Thin-film transistor and method for making same Download PDFInfo
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- CN100345310C CN100345310C CNB2004100347102A CN200410034710A CN100345310C CN 100345310 C CN100345310 C CN 100345310C CN B2004100347102 A CNB2004100347102 A CN B2004100347102A CN 200410034710 A CN200410034710 A CN 200410034710A CN 100345310 C CN100345310 C CN 100345310C
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- 239000010409 thin film Substances 0.000 title claims abstract description 62
- 238000000034 method Methods 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 claims abstract description 14
- 230000004888 barrier function Effects 0.000 claims description 82
- 239000010408 film Substances 0.000 claims description 34
- 230000002093 peripheral effect Effects 0.000 claims description 11
- 238000009413 insulation Methods 0.000 abstract description 12
- 239000012212 insulator Substances 0.000 description 22
- 238000005516 engineering process Methods 0.000 description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 12
- 239000003990 capacitor Substances 0.000 description 10
- 239000011248 coating agent Substances 0.000 description 9
- 238000000576 coating method Methods 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 9
- 238000002360 preparation method Methods 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000003746 surface roughness Effects 0.000 description 3
- 238000005224 laser annealing Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
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- 239000013078 crystal Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
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Abstract
The present invention discloses a thin film transistor and a manufacture method thereof. The thin film transistor comprises a substrate, wherein the substrate comprises a first thin film transistor area and a second thin film transistor area. A first effective layer and a second effective layer are respectively formed on the first thin film transistor area and the second thin film transistor area of the substrate. A first grid electrode insulation layer is formed on the first effective layer and the second effective layer. A first grid electrode layer is formed on the first grid electrode insulation layer of the first thin film transistor area. A second grid electrode insulation layer is directly formed on the first grid electrode insulation layer of the second thin film transistor area, and a second grid electrode layer is formed on the second grid electrode insulation layer of the second thin film transistor area. The thickness of the insulation layer under the first grid electrode layer of the first thin film transistor area is the same as the thickness of the first grid electrode insulation layer, and the thickness of the insulation layer under the second grid electrode layer of the second thin film transistor area is the same as the total thickness of the first grid electrode insulation layer and the second grid electrode insulation layer.
Description
Technical field
The present invention is relevant for a kind of thin-film transistor (thin film transistor, TFT) technology, relevant especially a kind of technology that thin-film transistor with different gate insulator layer thicknesses can be provided simultaneously.
Background technology
Active matrix liquid crystal display (active matrix liquid crystal display, hereinafter to be referred as AMLCD) peripheral driving circuit or pixel switch element be utilization one thin-film transistor (thin film transistor, TFT), generally can be distinguished into two kinds of patterns of non-crystalline silicon tft and multi-crystal TFT.
Because the carrier transport factor integration higher, drive circuit of polycrystalline SiTFT is preferable, leakage current is less, so polycrystalline SiTFT more often is applied in the circuit of high service speed, as: static RAM (static random access memory, SRAM).
Polycrystalline SiTFT for improving driving force, often need reduce the thickness of grid lower gate insulating barrier, in the hope of can improve electric current under fixing operation voltage when being designed to peripheral driving circuit.
Yet, on the other hand, thin-film transistor is as the pixel switch element or be applied to horizontal switch (horizontal switch, HSW), electrostatic discharge protective (electrostatic discharge, ESD) etc. during circuit design, for cooperating high electric current, high-tension operational requirements, need to improve relatively the thickness of grid lower gate insulating barrier, to guarantee the reliability of thin-film transistor.Therefore, if cooperate the design of polycrystalline SiTFT as peripheral driving circuit, and reduce the thickness of gate insulator, then simultaneously as the pixel switch element or be applied to the thin-film transistor of circuit design such as horizontal switch, electrostatic discharge protective, its element Reliability will be greatly affected.
In addition, aspect the capacity cell of LCD indispensability, known manufacture method is to form a gate insulator above a polysilicon layer, on this gate insulator, form one more simultaneously in order to make the conductive layer of grid, then accompany the sandwich structure of gate insulator thus in the middle of conductive layer and the polysilicon layer, form above-mentioned capacity cell.In actual process, because the surface roughness of general polysilicon layer is quite big, if reduce the thickness of gate insulator on it, then the jut of polysilicon layer rough surface contacts with conductive layer easily, and causes the short circuit of this capacity cell relatively.
In sum, with regard to considering of circuit design, known thin-film transistor technology can't be at the different demands of element, provide one to conform with the technology of suitable requirement of all elements, that is, if reduce the gate insulator layer thickness of thin-film transistor at the peripheral driving circuit design, during with raising actuating force and service speed, just can't satisfy thin-film transistor the time,, also cause the short circuit of capacity cell simultaneously easily the requirement of element reliability as the pixel switch element design.
Summary of the invention
Purpose of the present invention just is to propose a kind of new thin-film transistor technology and structure, so that the thin-film transistor with different gate insulator layer thicknesses to be provided simultaneously, comes the different demands of each element in the coincident circuit design, and solves above-mentioned facing a difficult choice of can't taking into account.
Another object of the present invention by the basic structure that changes electric capacity, promotes the performance of capacity cell when the thin-film transistor with different gate insulator layer thicknesses is provided.
For reaching above-mentioned purpose, the present invention is divided into the making of two stages with gate insulator.That is, in the phase I, earlier form one deck first grid insulating barrier, in TFT regions top wherein, for example make first grid on the first film transistor area afterwards respectively at a first film transistor area and one second TFT regions top.Afterwards, in another TFT regions top, for example second TFT regions top forms a second grid insulating barrier, then makes second grid more thereon again.
By aforesaid way, the gate insulator layer thickness on the first film transistor area is the thickness of first grid insulating barrier, and the gate insulator layer thickness on second TFT regions is the summation thickness of first grid insulating barrier and second grid insulating barrier.Thus, can be in response to the demand of different circuit design, the thickness of gate insulator reaches the requirement of element operation speed and reliability simultaneously in control the first film transistor AND gate second thin-film transistor.
In addition, when reaching the requirement of element operation speed and reliability, thin-film transistor technology proposed by the invention can promote the performance of capacity cell simultaneously by the basic structure that changes electric capacity.
In the technology of above-mentioned two phase gate insulating barriers, comprise the technology of two phase gate simultaneously: first grid and second grid.The present invention is by the structure that accompanies the second grid insulating barrier between first grid and second grid, the structure that replaces known polysilicon-gate insulator-grid, not only form a kind of new capacitance structure, and this structure avoids the problem of polysilicon surface roughness, can effectively reduce the probability of capacitance short-circuit.
According to the thin-film transistor that the present invention carried, comprising: a substrate, it includes the first film transistor area and second TFT regions; First active layer (active layer) and second active layer are to be formed at respectively on the first film transistor area and second TFT regions; The first grid insulating barrier is to be formed on first active layer and second active layer; The first grid layer is on the first grid insulating barrier that is formed in the first film transistor area; The second grid insulating barrier is on the first grid insulating barrier that is formed in second TFT regions; And second grid layer, be on the second grid insulating barrier that is formed in second TFT regions, wherein, the thickness of insulating layer of first grid layer below is the thickness of this first grid insulating barrier in the first film transistor area, and the thickness of insulating layer of this second grid layer below is the summation thickness of first grid insulating barrier and second grid insulating barrier in second TFT regions.
According to the thin-film transistor that the present invention carried, it can further comprise a capacitive region, and capacitive region comprises: the first grid insulating barrier is to be formed at capacitive region; The first grid layer is to be formed on the first grid insulating barrier of capacitive region; The second grid insulating barrier is to be formed on the first grid layer of capacitive region; And the second grid layer, be to be formed on the second grid insulating barrier of capacitive region, wherein, first grid layer, second grid insulating barrier and this second grid layer form electric capacity.
According to the manufacture method of thin-film transistor that the present invention carries, comprise the following steps: to provide substrate, it includes the first film transistor area and second TFT regions; Form first active layer and second active layer respectively on this first film transistor area and second TFT regions of substrate; Form the first grid insulating barrier on first active layer and second active layer; Form on the first grid insulating barrier of first grid layer in the first film transistor area; Form on the first grid insulating barrier of second grid insulating barrier in second TFT regions; And form on the second grid insulating barrier of second grid layer in second TFT regions.
According to the manufacture method of thin-film transistor that the present invention carries, it can further comprise the making step of capacitive region: form the first grid insulating barrier in capacitive region; Form the first grid layer on the first grid insulating barrier of capacitive region; Form the second grid insulating barrier on the first grid layer of capacitive region; And form this second grid layer on the second grid insulating barrier of capacitive region, wherein, first grid layer, second grid insulating barrier and second grid layer form electric capacity.
In above-mentioned thin-film transistor and preparation method thereof, wherein the first film transistor area is for example as a peripheral driving circuit zone, and second TFT regions is for example as a cell array zone.
In above-mentioned thin-film transistor and preparation method thereof, wherein the second grid insulating barrier can be covered on this interior first grid layer of the first film transistor area simultaneously.Above-mentioned substrate can be a transparent insulation substrate or a glass substrate.Above-mentioned first, second active layer can be amorphous silicon layer (amorphoussilicon) or polysilicon layer (poly-silicon).Above-mentioned first and second gate insulator can be the stack layer of silicon oxide layer, silicon nitride layer, silicon oxynitride layer or its combination.
In above-mentioned thin-film transistor and preparation method thereof, and can further include resilient coating, be to be formed between the substrate and first active layer, and be formed between the substrate and second active layer.
In above-mentioned thin-film transistor and preparation method thereof, wherein the thickness of first grid layer is less than the thickness of second grid layer, in order to the growth of complying with of second grid insulating barrier thereon, and makes the second grid layer applicable to follow-up interconnect technology.
In the manufacture method of above-mentioned thin-film transistor, the making of first grid layer for example is prior to forming first conductive layer on this substrate, utilizing technologies such as exposure, development and etching that this first conductive layer is defined as the first grid layer again; The making of second grid layer for example is prior to forming one second conductive layer on this substrate, utilizing technologies such as an exposure, development and etching that second conductive layer is defined as this second grid layer again.
Description of drawings
Fig. 1 shows the thin-film transistor element of the embodiment of the invention and the generalized section of capacity cell;
Fig. 2 A～2F is the generalized section that shows the manufacture method of present embodiment thin-film transistor element.
Symbol description
I～the first film transistor area
II～second TFT regions
III～capacitor regions
1～substrate
2～resilient coating
10～the first active layers
20～the second active layers
11～first grid insulating barrier
21～second grid insulating barrier
12～first grid layer
22～second grid layer
Embodiment
The embodiment of the invention is to make the gate insulator of different-thickness at the thin-film transistor element of different operating voltage, provide simultaneously by two conductive layers and a gate insulator the common capacity cell of forming.
Present embodiment thin-film transistor element structure and preparation method thereof can be applicable to the thin-film transistor element in cell array zone and peripheral driving circuit zone, below be describe in detail thin-film transistor with different-thickness grid insulating barrier with by two conductive layers and a gate insulator the manufacture method of the common capacity cell of forming.
See also Fig. 1, it shows the thin-film transistor element of the embodiment of the invention and the generalized section of capacity cell.
One substrate 1 includes the first film transistor area I, the second TFT regions II, and capacitor regions III, and deposits a resilient coating 2 on the surface.
In the first film transistor area I, be manufactured with first active layer 10, first grid insulating barrier 11 and first grid layer 12 on the resilient coating 2 in regular turn.
In the second TFT regions II, be manufactured with second active layer 20, first grid insulating barrier 11, second grid insulating barrier 21 and second grid layer 22 on the resilient coating 2 in regular turn.
In capacitor regions III, be manufactured with first grid insulating barrier 11, first grid layer 12, second grid insulating barrier 21 and second grid layer 22 on the resilient coating 2 in regular turn.
The first film transistor area I is a peripheral driving circuit zone; The second TFT regions II is a cell array zone.
The preferably of substrate 1 is a transparent insulation substrate, for example: glass substrate.The preferably of resilient coating 2 is a dielectric materials layer, and for example: silicon oxide layer, its purpose is formed on the substrate 1 for helping first, second active layer 10,20.The preferably of first, second active layer 10,20 is the semiconductor silicon layer, for example: amorphous silicon layer or polysilicon layer.The preferably of first, second gate insulator 11,21 is the stack layer of silicon oxide layer, silicon nitride layer, silicon oxynitride layer or its combination.The preferably of first, second grid layer 12,22 is a metal level.
It below is the architectural feature of explanation the first film transistor area I.First active layer, 10 tops are formed with first grid insulating barrier 11 and first grid layer 12, and the thickness of its effective gate insulator is the thickness of first grid insulating barrier 11.
It below is the architectural feature of the explanation second TFT regions II.Second active layer, 20 tops are formed with first grid insulating barrier 11, second grid insulating barrier 21 and second grid layer 22, and the thickness of its effective gate insulator is the summation thickness of first grid insulating barrier 11 and second grid insulating barrier 21.
It below is the architectural feature of explanation capacitor regions III.Be formed with second grid insulating barrier 21 and second grid layer 22 in first grid layer 12 top, then these structure mutual group become the capacity cell of present embodiment.
See also Fig. 2 A～2F, it shows the generalized section of the manufacture method of present embodiment thin-film transistor element.
At first, shown in Fig. 2 A, provide a substrate 1, its include a first film transistor area I with as peripheral driving circuit, one second TFT regions II with as the pixel switch circuit, an and capacitor regions III.Then, deposition one resilient coating 2 on substrate 1 is again respectively at making first, second active layer 10,20 on the resilient coating 2 of first, second TFT regions I, II.The present invention does not limit thickness of first, second active layer 10,20 and preparation method thereof, for instance, can adopt low temperature polycrystalline silicon (low temperature polycrystallinesilicon, LTPS) technology, prior to forming an amorphous silicon layer on the glass substrate, (excimer laser annealing, mode ELA) converts amorphous silicon layer to the polysilicon material to utilize heat treatment or quasi-molecule laser annealing then.
Then, shown in Fig. 2 B, deposition first insulating barrier 11 on first, second active layer 10,20.The preferably of first insulating barrier 11 is the stack layer of silicon oxide layer, silicon nitride layer, silicon oxynitride layer or its combination.
Then, form first conductive layer (not shown) prior to first insulating barrier, 11 tops.The preferably of first conductive layer is a metal level.
Thereafter, on first conductive layer, form first photoresist layer of patterning, so that it covers the presumptive area of the first film transistor area I and capacitor regions III.Follow-up, first photoresist layer that utilizes patterning, with the pattern of the definition becoming of the conductive layer in the first film transistor area I and a capacitor regions III first grid layer 12, follow-uply removes photoresist layer, shown in Fig. 2 C to carry out an etch process as mask.
Then, shown in Fig. 2 D, in the first film transistor area I, the second TFT regions II and capacitor regions III top deposition second insulating barrier 21.The preferably of second insulating barrier 21 is the stack layer of silicon oxide layer, silicon nitride layer, silicon oxynitride layer or its combination.
Afterwards, form second conductive layer (not shown) prior to second insulating barrier, 21 tops.The preferably of second conductive layer is a metal level.
Then, on second conductive layer, form second photoresist layer of patterning, so that it covers the presumptive area of the second TFT regions II and capacitor regions III.Follow-up, to carry out an etch process, the pattern with the definition becoming of the conductive layer in the second TFT regions II and capacitor regions III second grid layer 22 removes photoresist layer, shown in Fig. 2 E second photoresist layer that utilizes patterning afterwards as mask.
At the same time, above-mentioned etch process can further be etched to second insulating barrier 21, to remove second insulating barrier 21 of first grid layer 12 top, shown in Fig. 2 F.
In the present embodiment, the thickness of first grid layer is less than the thickness of second grid layer, and the thickness of first grid layer for example is that (, angstrom), the thickness of second grid layer for example is 1500 ～4000 to 500 dusts～1500 dusts.By the design of these preferred thickness, remove the growth of complying with to be beneficial to second grid insulating barrier on the first grid layer, and make the second grid layer thickness can be applicable to follow-up interconnect technology completely.
Follow-up interconnect technology of carrying out includes the making of interconnect dielectric layer, contact hole and interconnect, and the execution mode of this step can materially affect feature of the present invention and effect, so do not write in detail.
From the above, thin-film transistor element of the embodiment of the invention and preparation method thereof has the following advantages:
The first, can adjust the thickness of first, second gate insulator 11,21 according to the demand of circuit design, to meet requirement simultaneously to service speed, reliability.
Second, special in the thin-film transistor that requires high driven nature, as in the present embodiment as the first film transistor I of peripheral driving circuit, can be by the thickness of thinning first grid layer 12, be beneficial to control etching, and reduce critical size (critical dimension) infringement.Have simultaneously in addition and can reduce driving voltage, and improve the advantage of reaction speed.
The 3rd, special in the thin-film transistor that requires high reliability, as in the present embodiment as the second thin-film transistor II of pixel switch element, can improve the thickness of effective gate insulator by storehouse first insulating barrier 11 and second insulating barrier 21, to improve the reliability of thin-film transistor, be beneficial to the operation under high voltage, the high electric current.
The 4th, especially for capacity cell, capacity cell III as present embodiment, the structure that can replace known polysilicon-gate insulator-grid by the stack architecture of first grid layer 12, second grid layer 22 and second grid insulating barrier 21, not only form a new capacitance structure, and this structure is avoided the problem of polysilicon surface roughness, effectively reduces the probability of capacitance short-circuit.
The 5th, according to the present invention, compare with known thin-film transistor technology, only need to increase by one mask (with definition second grid layer 22), can make above-mentioned multi-function membrane transistor base, and above-mentioned various advantages is provided.
Claims (9)
1. thin-film transistor is characterized in that described thin-film transistor comprises:
One substrate, it includes a first film transistor area, one second TFT regions and a capacitive region;
One first active layer and one second active layer are to be formed at respectively on this first film transistor area and this second TFT regions of this substrate;
One first grid insulating barrier is to be formed on this first active layer, second active layer and the capacitive region;
One first grid layer is on this first grid insulating barrier that is formed in this first film transistor area and this capacitive region;
One second grid insulating barrier is on this first grid insulating barrier that is formed in this second TFT regions, and on the first grid layer of this capacitive region; And
One second grid layer is on this second grid insulating barrier that is formed in this second TFT regions and this capacitive region;
Wherein, the thickness of insulating layer of this first grid layer below is the thickness of this first grid insulating barrier in this first film transistor area, and the thickness of insulating layer of this second grid layer below is the summation thickness of this first grid insulating barrier and this second grid insulating barrier in this second TFT regions;
Wherein, this first grid layer of this capacitive region, second grid insulating barrier and this second grid layer are formed this electric capacity.
2. thin-film transistor according to claim 1 is characterized in that: this first film transistor area is as a peripheral driving circuit zone, and second TFT regions is as a cell array zone.
3. thin-film transistor according to claim 1 is characterized in that: this second grid insulating barrier is on this first grid layer that is covered in simultaneously in this first film transistor area.
4. thin-film transistor according to claim 1 is characterized in that: the thickness of this first grid layer is less than the thickness of this second grid layer.
5. the manufacture method of a thin-film transistor, described manufacture method comprises the following steps:
One substrate is provided, and it includes a first film transistor area and one second TFT regions;
Form one first active layer and one second active layer respectively on this first film transistor area and this second TFT regions of this substrate;
Form a first grid insulating barrier on this first active layer and second active layer;
Form on a first grid layer this first grid insulating barrier in this first film transistor area;
Directly form on a second grid insulating barrier this first grid insulating barrier in this second TFT regions; And
Form on a second grid layer this second grid insulating barrier in this second TFT regions.
6. the manufacture method of thin-film transistor according to claim 5, wherein this first film transistor area is as a peripheral driving circuit zone, second TFT regions is as a cell array zone.
7. the manufacture method of thin-film transistor according to claim 5, wherein this second grid insulating barrier is on this first grid layer that is covered in simultaneously in this first film transistor area.
8. the manufacture method of thin-film transistor according to claim 5 more comprises the making step of a capacitive region:
Form this first grid insulating barrier on this capacitive region;
Form this first grid layer on this first grid insulating barrier on this capacitive region;
Form this second grid insulating barrier on this first grid layer of this capacitive region; And
Form this second grid layer on this second grid insulating barrier of this capacitive region, wherein, this first grid layer, second grid insulating barrier and this second grid layer are formed this electric capacity.
9. the manufacture method of thin-film transistor according to claim 5, wherein the thickness of this first grid layer is less than the thickness of this second grid layer.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2004100347102A CN100345310C (en) | 2004-04-26 | 2004-04-26 | Thin-film transistor and method for making same |
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| CNB2004100347102A CN100345310C (en) | 2004-04-26 | 2004-04-26 | Thin-film transistor and method for making same |
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| CN1691353A CN1691353A (en) | 2005-11-02 |
| CN100345310C true CN100345310C (en) | 2007-10-24 |
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Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8227808B2 (en) | 2007-12-06 | 2012-07-24 | Chimei Innolux Corporation | Method for manufacturing thin film transistor (TFT) and OLED display having TFTS manufactured by the same |
| TWI375282B (en) * | 2007-12-06 | 2012-10-21 | Chimei Innolux Corp | Thin film transistor(tft)manufacturing method and oled display having tft manufactured by the same |
| CN101834189B (en) * | 2009-03-11 | 2015-07-08 | 统宝光电股份有限公司 | Image display system |
| CN102087998B (en) * | 2009-12-04 | 2014-03-19 | 无锡华润上华半导体有限公司 | Dual polycrystalline structure device and manufacturing method thereof |
| CN104078469B (en) | 2014-06-17 | 2017-01-25 | 京东方科技集团股份有限公司 | Array substrate, array substrate manufacturing method, display panel and display device |
| CN105405866B (en) * | 2015-12-31 | 2019-01-04 | 昆山国显光电有限公司 | OLED display and its manufacturing method |
| CN107290913A (en) | 2017-07-31 | 2017-10-24 | 武汉华星光电技术有限公司 | Display panel, array base palte and forming method thereof |
| CN110660814A (en) * | 2019-09-29 | 2020-01-07 | 合肥京东方卓印科技有限公司 | Array substrate, display panel and manufacturing method of array substrate |
| CN113594182A (en) * | 2021-07-27 | 2021-11-02 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method thereof and display device |
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| US5719065A (en) * | 1993-10-01 | 1998-02-17 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device with removable spacers |
| CN1192044A (en) * | 1993-10-20 | 1998-09-02 | 株式会社半导体能源研究所 | Thin membrane semiconductor integrated circuit and its manufacturing method |
| JP2000216399A (en) * | 1998-11-17 | 2000-08-04 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its manufacture |
| US6316787B1 (en) * | 1996-06-04 | 2001-11-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor integrated circuit and fabrication method thereof |
| CN1445862A (en) * | 2002-03-11 | 2003-10-01 | 三洋电机株式会社 | Top-gate type thin film transistor |
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2004
- 2004-04-26 CN CNB2004100347102A patent/CN100345310C/en not_active Expired - Lifetime
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5719065A (en) * | 1993-10-01 | 1998-02-17 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device with removable spacers |
| CN1192044A (en) * | 1993-10-20 | 1998-09-02 | 株式会社半导体能源研究所 | Thin membrane semiconductor integrated circuit and its manufacturing method |
| US6316787B1 (en) * | 1996-06-04 | 2001-11-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor integrated circuit and fabrication method thereof |
| JP2000216399A (en) * | 1998-11-17 | 2000-08-04 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its manufacture |
| CN1445862A (en) * | 2002-03-11 | 2003-10-01 | 三洋电机株式会社 | Top-gate type thin film transistor |
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