CN1326234C - 堆栈型半导体装置 - Google Patents

堆栈型半导体装置 Download PDF

Info

Publication number
CN1326234C
CN1326234C CNB2004100597875A CN200410059787A CN1326234C CN 1326234 C CN1326234 C CN 1326234C CN B2004100597875 A CNB2004100597875 A CN B2004100597875A CN 200410059787 A CN200410059787 A CN 200410059787A CN 1326234 C CN1326234 C CN 1326234C
Authority
CN
China
Prior art keywords
wiring substrate
storehouse
type semiconductor
devices
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2004100597875A
Other languages
English (en)
Other versions
CN1574309A (zh
Inventor
西村隆雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Socionext Inc
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of CN1574309A publication Critical patent/CN1574309A/zh
Application granted granted Critical
Publication of CN1326234C publication Critical patent/CN1326234C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01025—Manganese [Mn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/1627—Disposition stacked type assemblies, e.g. stacked multi-cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Combinations Of Printed Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

一种堆栈型半导体装置，包括：一第一接线基底，其上安装一半导体元器件；一第二接线基底，通过电连接于第一接线基底的多个电极接线端，堆叠于第一接线基底上；以及一框架状导体支撑部，其以围绕半导体元器件并位于所述多个电极接线端的内侧的方式设置，并且连接于第一和第二接线基底中设置的地线层。

Description

堆栈型半导体装置
技术领域
本发明涉及一种半导体装置，特别涉及一种具有三维结构的堆栈型半导体装置，在该三维结构中多个半导体器件和半导体元器件(semiconductordevice elements)彼此堆叠。
背景技术
随着电子装置的新近发展，日益需要在电子装置中使用一种小型化、厚度减少、具有多种功能、具有增强功能和具有增大密度的半导体装置。
为了满足这样的需要，半导体封装的结构开始变为一种具有三维结构的堆栈型半导体装置，在该三维结构中，多个半导体器件或多个半导体元器件彼此堆叠。例如，日本公开专利申请号2001-223297，特别在其第8页和图15中，公开了一种相关的现有技术。
同时，随着电子装置的新近发展，不必要电波的影响，即由一电子装置所产生的不必要电波造成另一电子装置故障的可能性，实际上在许多情况下无法忽略。因此，日益需要满足EMS(电磁干扰规定，为了消除一电子装置对另一电子装置的影响，该规定规范了电磁噪声(电波)的辐射或传播)的电子装置。
在多个半导体器件和半导体元器件彼此堆叠于其中的堆栈型半导体装置中，在以混合载入方式将一射频电路器件，比如射频模拟信号处理半导体器件安装于其中的情况下，需要将其产生的电磁辐射(不必要的辐射/辐射电磁噪声/电波噪声)控制为尽可能低的水平。
日本公开专利申请号2000-174204，特别在其第3至5页和图2中，公开一种相关现有技术中的堆栈型半导体装置的实例，其设计为解决这样的电磁辐射问题。下面将参照图9对其具体的结构加以描述。在图9所示的堆栈型半导体装置中，射频电路器件3安装于腔部2中，同时一接地导体设置于在金属底座8上形成的第一电介质基底1的后侧上，并且堆叠第二电介质基底5，该第二电介质基底5具有一安装于其上的射频电路器件4。而且，在第一电介质基底1上设置一金属盖6用于覆盖第二电介质基底5，该金属盖6的一端连接至设置于第一电介质基底1中的通孔7，并且利用导电粘合剂，使金属盖6与第一电介质基底1相连接。金属盖6电磁屏蔽射频电路器件4，并且其同时以密封的方式封住射频电路器件4和射频电路器件3。
发明内容
在上述日本公开专利申请号2001-223297中，没有关于为堆栈型半导体装置所配备的电磁屏蔽以符合上述EMI规定的具体公开。而且，虽然在上述日本公开专利申请号2000-174204中，包括对于堆栈型半导体装置考虑EMI规定的公开，然而该第一基底具有上述空腔外形，并同时设置密封封闭，由此就节省生产成本而言，这样的结构并非有利。而且，由于该结构具有上述的金属盖，故难以在总体上有效地减少装置的厚度。因此，需要提供一种堆栈型半导体装置，其具有以混合载入方式安装于其中的射频电路器件，其发出的电磁辐射可减少到尽可能低的水平，并同时要求减少生产成本以及整体有效小型化。
为了满足该需要，按照本发明的一个方案，一种堆栈型半导体装置包括：一第一接线基底，其上安装一半导体元器件；一第二接线基底，通过电连接于第一接线基底的多个接线电极，堆叠于第一接线基底上；以及一框架状导体支撑部，其以围绕半导体元器件并位于所述多个电极接线端的内侧的方式设置，并且与设置于第一和第二接线基底中的地线层相连接。
根据本发明的另一方案，提供一种堆栈型半导体装置，包括：一第一接线基底，其上安装一半导体元器件；一第二接线基底，其通过电连接于所述第一接线基底的多个电极接线端，堆叠于所述第一接线基底上；以及多个导体支撑部，其以围绕所述半导体元器件并位于所述多个电极接线端的内侧的方式设置，并且连接于所述第一和第二接线基底中设置的地线层。
按照本发明，通过提供这样的结构，能够提供一种堆栈型半导体装置，其中，与相关现有技术中的结构相比，以混合载入方式安装于其中射频电路器件所产生的电磁辐射得以适当控制，并且能够以减少的成本和减少的厚度(小型化)来生产该堆栈型半导体装置。而且，按照本发明，由于接线基底不仅与电极接线端连接在一起，以将这些接线基底连接在一起，而且也与导体支撑部连接在一起，所以可有效地减少由于接线基底的弯曲等造成的电极接线端连接部分中的制造缺陷，并且因此能够提供一种可改善接线基底之间的连接可靠性的堆栈型半导体装置。
附图说明
当结合附图阅读时，从如下具体的描述中，本发明的其他目的和更多特征将会变得明显，在附图中：
图1示出本发明第一实施例中的堆栈型半导体装置的侧面正视剖面图；
图2示出说明图1所示的堆栈型半导体装置中导体支撑部结构的平面图；
图3A和3B示出说明图1中所示的堆栈型半导体装置中设置的地线层图案的可选实例的平面图；
图4示出按照本发明第二实施例中的堆栈型半导体装置的侧面正视剖面图；
图5示出按照本发明第三实施例中的堆栈型半导体装置的侧面正视剖面图；
图6示出说明图5所示堆栈型半导体装置中的导体支撑部结构的平面图；
图7示出本发明第四实施例中的堆栈型半导体装置的侧面正视剖面图；
图8示出本发明第五实施例中的堆栈型半导体装置的侧面正视剖面图；以及
图9示出相关现有技术中的堆栈型半导体装置的侧面正视剖面图。
具体实施方式
图1示出了本发明第一实施例中的堆栈型半导体装置的侧面正视剖面图；图2示出了说明图1中所示的堆栈型半导体装置中的导体支撑部12的结构平面图；以及图3A和3B示出了分别说明在图1中所示的堆栈型半导体装置中地线(ground wiring)层26图案的可选实例的平面图。如图所示，堆栈型半导体装置包括接线基底9和18；地线层11和26；导体支撑部12；连接垫片13、15、17、20、25和27；半导体元器件10、21、22和23；以及接线24。
在本发明第一实施例的堆栈型半导体装置中，接线基底9由比如玻璃环氧树脂、陶瓷等材料制成；半导体元器件10以倒装(flip-chip)方式安装于接线基底9的顶侧上；并且半导体元器件10通过绝缘树脂比如环氧树脂粘结于接线基底9的顶侧上。半导体元器件10为比如RF模拟信号处理半导体器件等射频电路器件。地线层11内嵌于接线基底9的内部，并且地线层11连接于用以连接导体支撑部12的连接垫片13，以及连接于用以连接接地端14的连接垫片15，如图1中所示。连接垫片13形成和设置为框架形，围绕着安装于接线基底9上的半导体元器件10。用于连接外部电路的外部电极接线端16以焊球的形式形成于连接垫片17上。在接线基底9的***中，设置许多连接垫片20，以通过用作电极接线端的焊球19，将接线基底9和18电连接在一起。
另一方面，接线基底18是由玻璃环氧树脂、陶瓷等材料制成的多层接线基底。半导体元器件21以倒装的方式安装在接线基底18的顶侧上，并且半导体元器件21通过绝缘树脂比如环氧树脂粘合于接线基底18的顶侧上。而且，半导体元器件22通过粘合剂粘合于半导体元器件21的顶侧上，并且半导体元器件23也通过粘合剂粘合于半导体元器件的顶侧上。由金制接线24通过利用接线基底18上设置的连接垫片25进行接线焊接，实现半导体元器件22和23与接线基底18之间的电路连接，如图1中所示。接线基底18上的所有半导体元器件21、22和23通过环氧树脂等树脂密封。
如图3A或3B所示，由铜(Cu)、镍(Ni)、钼(Mo)、锰(Mn)等金属制成的地线层26被设置于接线基底18的底侧上。该地线层26以电镀方式、层压方式、印光方式、蒸发方式等形成。图3A给出了一个实例，其中地线层26以实心图案的形式形成，而图3B给出了另一实例，其中地线层26以网孔图案的形式形成。由于接线基底18的顶面和底面之间的导体接线密度差异，接线基底18有可能弯曲。这时，在设计上应用如图3B所示的网孔图案是有利的。而且，许多连接垫片27设置于接线基底18***的底侧上，用于通过焊球19将接线基底18和接线基底9电连接在一起。在图2、3A和3B中，粗的虚线所限定的区域表示一用以在接线基底9上安装半导体元器件10的区域。
以打孔方式或蚀刻方式，半导体支撑部12由铝(Al)铜、镍、钛(Ti)、钴(Co)、钨(W)、铁(Fe)等金属或这些类型金属的合金制成的一薄片被制造成如图2所示的框架形式。框形导体支撑部12通过导电粘合剂，同时与接线基底9的顶侧上设置的连接垫片13和接线基底18的底侧上设置的地线层26相粘合。同时，焊球19用以将接线基底9的连接垫片20和接线基底18的底侧上设置的连接垫片27连接在一起。
在按照本发明第一实施例的堆栈型半导体装置的上述结构中，由于半导体元器件10的顶侧、底侧和横侧由处于零电位(ground potential)的导体(地线层11和26以及导体支撑部12)围绕，从半导体元器件10产生的不必要的辐射可有效地被阻止，因此能够有效地减少其对其他装置的不利影响。而且，由于导体支撑部12稳固地支撑接线基底9和接线基底18，并且因此保持二者之间的距离不变，所以能够有效地减少这些接线基底9和18弯曲的可能性，并且因此有效地减少在堆栈型半导体装置的制造过程中由于基底的弯曲而造成关于焊球19的制造缺陷出现的可能性。而且，由于接线基底9和18都通过框架形状的导体支撑部12连接和固定在一起，所以接线基底9和18之间的连接可靠性有所改善。因此，能够实现厚度减少(小型化)的堆栈型半导体装置，其具有这样的结构，即有效地阻止从安装于接线基底上的半导体元器件发出的不必要的辐射。应注意将半导体元器件10安装于接线基底9的方式并不限于上述倒装的方式，而可应用其他的方式，比如TAB(卷带自动结合)方式。
图4说明本发明第二实施例中的堆栈型半导体装置的侧面正视剖面图。
第二实施例与上述第一实施例的区别在于，接线基底29顶侧的地线层30嵌入于接线基底29的内部。除此之外，第二实施例在结构上与第一实施例相同。因此，按照第二实施例的堆栈型半导体装置提供与按照第一实施例的堆栈型半导体装置相同的优点。而且，在按照第二实施例的堆栈型半导体装置中，由于地线层30嵌入于接线基底29的内部，从而能够将地线层30放置得更接近于安装于接线基底29的顶侧上的半导体装置21、22和23。由此，能够改善由这些半导体元器件21至23形成的电路的高速信号传输性能。
图5示出了本发明第三实施例中的堆栈型半导体装置的侧面正视剖面图，图6示出了说明图5所示结构中导体支撑部31的布置的平面图。第三实施例与上述第一实施例的区别在于，焊球用作导体支撑部31。用作导体支撑部31的焊球设置于用作将接线基底9和18电连接在一起的电极接线端的焊球19的内侧，也设置于半导体元器件10的***中(与图2、3A和3B相同，由虚线28限定)。按照第三实施例，由于普通的焊球用作导体支撑部31，所以与其中设置框形导体支撑部的第一或第二实施例相比，能够有效地减少提供导体支撑部所需的成本。
图7示出了本发明第四实施例中的堆栈型半导体装置的侧面正视剖面图。
在第四实施例中，高导热(high-heat-conductive)粘合剂32比如含有银粉的树脂粘合剂填充于上述第三实施例中安装于接线基底9上的半导体元器件10的顶面和接线基底18的底面上形成的地线层26之间。在按照第四实施例的堆栈型半导体装置中，由高导热粘合剂32产生一路径，以通过地线层26和用作导体支撑部31的焊球，传递从半导体元器件10的顶面产生的热量。由此能够改善半导体元器件10的散热性能。
图8示出了本发明第五实施例中的堆栈型半导体装置的侧面正视剖面图。
在第五实施例中，半导体元器件34和芯片部件35比如电容安装于接线基底33的顶侧上。如图所示在接线基底33的内部，嵌入一地线层11，并且地线层11连接于用以连接导体支撑部31的连接垫片13和用以连接接地端14的连接垫片15。
而且，许多连接垫片20设置于接线基底33的顶侧上的***中，用于通过焊球19将接线基底33和接线基底36电连接在一起。
在接线基底36的顶侧上，安装一半导体元器件10，形成连接垫片38以连接导体支撑部37，并且在***中，设置许多连接垫片40以通过焊球39将接线基底36和接线基底18电连接在一起。在接线基底36的底侧上，形成一地线层41，并且在其***中，设置许多连接垫片27，用以通过焊球19将接线基底33和接线基底36电连接在一起。通过接线基底36的内部设置的导体部，将连接垫片38和地线层41连接在一起，以与导体支撑部37相连接。
其上安装有半导体元器件的接线基底18进一步堆叠于接线基底36的顶部上，其结构与上述第四实施例中的接线基底18的结构相同。
第五实施例是一堆栈型半导体装置的实例，其中通过用作半导体支撑部的焊球31和37以及用以将这些接线基底电连接在一起的焊球19和39，将三个接线基底33、36和18连接成三层。在第五实施例中，半导体元器件34和芯片部件35以及半导体元器件10的顶侧、底侧和横侧都分别被具有零电位的导体(用作导体支撑部的焊球31和37以及地线层11、41和26)围绕。
由此，有效地阻止这些半导体器件中产生的不必要的辐射，因此可有效地减少其对其他器件的不利影响。无需将本发明的实施例限定于这种三层堆叠接线基底的结构，而是也可进一步增加堆叠接线基底的层数。按照第五实施例，即使在多个射频电路元器件安装于半导体装置中的情况下，仍能够仅仅通过相应地增加堆叠基底的层数来简单地应用本发明。
而且，本发明并不限于上述实施例，不背离权利要求所定义的本发明的基本概念，可做出变化和改型。
本发明基于2003年6月24日提交的日本优先权申请号2003-180200，这里通过参照并入其全部内容。

Claims (6)

1.一种堆栈型半导体装置，包括：
一第一接线基底，其上安装一半导体元器件；
一第二接线基底，其通过电连接于所述第一接线基底的多个电极接线端，堆叠于所述第一接线基底上；以及
多个导体支撑部，其以围绕所述半导体元器件并位于所述多个电极接线端的内侧的方式设置，并且连接于所述第一和第二接线基底中设置的地线层。
2.如权利要求1所述的堆栈型半导体装置，其中：
所述导体支撑部为多个焊球。
3.一种堆栈型半导体装置，包括：
一第一接线基底，其上安装一半导体元器件；
一第二接线基底，其通过电连接于所述第一接线基底的多个电极接线端，堆叠于所述第一接线基底上；以及
一框架状导体支撑部，其以围绕所述半导体元器件并位于所述多个电极接线端的内侧的方式设置，并且连接于所述第一和第二接线基底中设置的地线层。
4.如权利要求3所述的堆栈型半导体装置，其中：
所述第一和第二接线基底中至少一个的地线层嵌入所述第一和第二基底的至少一个中。
5.如权利要求3所述的堆栈型半导体装置，其中：
安装于所述第一接线基底上的所述半导体元器件以倒装方式安装于其上。
6.如权利要求3所述的堆栈型半导体装置，其中：
所述第一接线基底上安装的所述半导体元器件的顶面和在所述第二接线基底上设置的地线层之间填充有高导热材料。
CNB2004100597875A 2003-06-24 2004-06-23 堆栈型半导体装置 Expired - Fee Related CN1326234C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2003180200A JP3858854B2 (ja) 2003-06-24 2003-06-24 積層型半導体装置
JP2003180200 2003-06-24

Publications (2)

Publication Number Publication Date
CN1574309A CN1574309A (zh) 2005-02-02
CN1326234C true CN1326234C (zh) 2007-07-11

Family

ID=33562247

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2004100597875A Expired - Fee Related CN1326234C (zh) 2003-06-24 2004-06-23 堆栈型半导体装置

Country Status (5)

Country Link
US (1) US7217993B2 (zh)
JP (1) JP3858854B2 (zh)
KR (1) KR100627099B1 (zh)
CN (1) CN1326234C (zh)
TW (1) TWI282153B (zh)

Families Citing this family (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200522293A (en) * 2003-10-01 2005-07-01 Koninkl Philips Electronics Nv Electrical shielding in stacked dies by using conductive die attach adhesive
JP4528062B2 (ja) * 2004-08-25 2010-08-18 富士通株式会社 半導体装置およびその製造方法
JP4185499B2 (ja) * 2005-02-18 2008-11-26 富士通マイクロエレクトロニクス株式会社 半導体装置
US7098073B1 (en) 2005-04-18 2006-08-29 Freescale Semiconductor, Inc. Method for stacking an integrated circuit on another integrated circuit
US7196427B2 (en) * 2005-04-18 2007-03-27 Freescale Semiconductor, Inc. Structure having an integrated circuit on another integrated circuit with an intervening bent adhesive element
US7311236B2 (en) 2005-04-25 2007-12-25 Tsi Manufacturing Llc Electric stapler having two anvil plates and workpiece sensing controller
DE102005041452A1 (de) * 2005-08-31 2007-03-15 Infineon Technologies Ag Dreidimensional integrierte elektronische Baugruppe
US8067831B2 (en) * 2005-09-16 2011-11-29 Stats Chippac Ltd. Integrated circuit package system with planar interconnects
JP2007142124A (ja) * 2005-11-18 2007-06-07 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
KR100892935B1 (ko) 2005-12-14 2009-04-09 신꼬오덴기 고교 가부시키가이샤 칩 내장 기판 및 칩 내장 기판의 제조방법
KR100690246B1 (ko) * 2006-01-10 2007-03-12 삼성전자주식회사 플립 칩 시스템 인 패키지 제조 방법
JP4577228B2 (ja) * 2006-02-09 2010-11-10 セイコーエプソン株式会社 半導体装置および半導体装置の製造方法
JP2007287906A (ja) * 2006-04-17 2007-11-01 Elpida Memory Inc 電極と電極の製造方法、及びこの電極を備えた半導体装置
US7633168B2 (en) * 2006-06-28 2009-12-15 Intel Corporation Method, system, and apparatus for a secure bus on a printed circuit board
JP5259059B2 (ja) 2006-07-04 2013-08-07 ルネサスエレクトロニクス株式会社 半導体装置
JP4976767B2 (ja) * 2006-07-19 2012-07-18 キヤノン株式会社 積層形半導体装置
KR100891516B1 (ko) * 2006-08-31 2009-04-06 주식회사 하이닉스반도체 적층 가능한 에프비지에이 타입 반도체 패키지와 이를이용한 적층 패키지
US7514774B2 (en) * 2006-09-15 2009-04-07 Hong Kong Applied Science Technology Research Institute Company Limited Stacked multi-chip package with EMI shielding
CN101502189B (zh) * 2006-10-24 2011-08-10 松下电器产业株式会社 三维电子电路装置
US20080128890A1 (en) * 2006-11-30 2008-06-05 Advanced Semiconductor Engineering, Inc. Chip package and fabricating process thereof
TWI376774B (en) * 2007-06-08 2012-11-11 Cyntec Co Ltd Three dimensional package structure
JP5049684B2 (ja) * 2007-07-20 2012-10-17 新光電気工業株式会社 積層型半導体装置及びその製造方法
US7952168B2 (en) * 2008-03-04 2011-05-31 Powertech Technology Inc. Substrate strip for semiconductor packages
US8779570B2 (en) * 2008-03-19 2014-07-15 Stats Chippac Ltd. Stackable integrated circuit package system
US9059074B2 (en) * 2008-03-26 2015-06-16 Stats Chippac Ltd. Integrated circuit package system with planar interconnect
US7871861B2 (en) * 2008-06-25 2011-01-18 Stats Chippac Ltd. Stacked integrated circuit package system with intra-stack encapsulation
US8043894B2 (en) * 2008-08-26 2011-10-25 Stats Chippac Ltd. Integrated circuit package system with redistribution layer
KR20100025750A (ko) * 2008-08-28 2010-03-10 앰코 테크놀로지 코리아 주식회사 반도체 패키지
US8129824B1 (en) * 2008-12-03 2012-03-06 Amkor Technology, Inc. Shielding for a semiconductor package
US8102032B1 (en) * 2008-12-09 2012-01-24 Amkor Technology, Inc. System and method for compartmental shielding of stacked packages
KR101004684B1 (ko) * 2008-12-26 2011-01-04 주식회사 하이닉스반도체 적층형 반도체 패키지
KR20110083969A (ko) * 2010-01-15 2011-07-21 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US8314486B2 (en) * 2010-02-23 2012-11-20 Stats Chippac Ltd. Integrated circuit packaging system with shield and method of manufacture thereof
US9355939B2 (en) * 2010-03-02 2016-05-31 Stats Chippac Ltd. Integrated circuit package stacking system with shielding and method of manufacture thereof
US8299595B2 (en) * 2010-03-18 2012-10-30 Stats Chippac Ltd. Integrated circuit package system with package stacking and method of manufacture thereof
US8569869B2 (en) * 2010-03-23 2013-10-29 Stats Chippac Ltd. Integrated circuit packaging system with encapsulation and method of manufacture thereof
KR101652831B1 (ko) * 2010-06-11 2016-08-31 삼성전자주식회사 열적 특성을 개선하는 패키지 온 패키지
TWI448226B (zh) * 2010-09-21 2014-08-01 Cyntec Co Ltd 電源轉換模組
US8861221B2 (en) 2010-09-24 2014-10-14 Stats Chippac Ltd. Integrated circuit packaging system with a shield and method of manufacture thereof
US9865310B2 (en) * 2011-02-24 2018-01-09 Interconnect Systems, Inc. High density memory modules
CN103460377B (zh) * 2011-04-14 2017-09-22 三菱电机株式会社 高频封装
KR20130005465A (ko) * 2011-07-06 2013-01-16 삼성전자주식회사 반도체 스택 패키지 장치
US8492888B2 (en) 2011-09-02 2013-07-23 Stats Chippac Ltd. Integrated circuit packaging system with stiffener and method of manufacture thereof
US10163744B2 (en) 2011-09-07 2018-12-25 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a low profile dual-purpose shield and heat-dissipation structure
TWI453873B (zh) * 2012-03-27 2014-09-21 Chipsip Technology Co Ltd 堆疊式半導體封裝結構
JP5959097B2 (ja) * 2012-07-03 2016-08-02 ルネサスエレクトロニクス株式会社 半導体装置
CN103681365B (zh) * 2012-08-31 2016-08-10 宏启胜精密电子(秦皇岛)有限公司 层叠封装结构及其制作方法
US10160638B2 (en) * 2013-01-04 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for a semiconductor structure
US8994191B2 (en) * 2013-01-21 2015-03-31 Advanced Micro Devices (Shanghai) Co. Ltd. Die-die stacking structure and method for making the same
US9293404B2 (en) 2013-01-23 2016-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Pre-applying supporting materials between bonded package components
JP6171402B2 (ja) * 2013-03-01 2017-08-02 セイコーエプソン株式会社 モジュール、電子機器、および移動体
JP6438225B2 (ja) * 2014-07-24 2018-12-12 株式会社ジェイデバイス 半導体パッケージ
US20200075501A1 (en) * 2016-03-31 2020-03-05 Intel Corporation Electromagnetic interference shielding for semiconductor packages using bond wires
TWI601219B (zh) * 2016-08-31 2017-10-01 矽品精密工業股份有限公司 電子封裝件及其製法
US10804115B2 (en) 2017-08-03 2020-10-13 General Electric Company Electronics package with integrated interconnect structure and method of manufacturing thereof
US10541209B2 (en) * 2017-08-03 2020-01-21 General Electric Company Electronics package including integrated electromagnetic interference shield and method of manufacturing thereof
CN109698170B (zh) * 2017-10-24 2021-03-12 长鑫存储技术有限公司 一种半导体封装结构及其制造方法
US10825774B2 (en) * 2018-08-01 2020-11-03 Samsung Electronics Co., Ltd. Semiconductor package
US10629455B1 (en) 2018-11-20 2020-04-21 Nanya Technology Corporation Semiconductor package having a blocking dam

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5783870A (en) * 1995-03-16 1998-07-21 National Semiconductor Corporation Method for connecting packages of a stacked ball grid array structure
US6274929B1 (en) * 1998-09-01 2001-08-14 Texas Instruments Incorporated Stacked double sided integrated circuit package
US6472741B1 (en) * 2001-07-14 2002-10-29 Siliconware Precision Industries Co., Ltd. Thermally-enhanced stacked-die ball grid array semiconductor package and method of fabricating the same

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5340771A (en) * 1993-03-18 1994-08-23 Lsi Logic Corporation Techniques for providing high I/O count connections to semiconductor dies
JPH06291216A (ja) * 1993-04-05 1994-10-18 Sony Corp 基板及びセラミックパッケージ
JP2944449B2 (ja) * 1995-02-24 1999-09-06 日本電気株式会社 半導体パッケージとその製造方法
JPH10125830A (ja) * 1996-10-24 1998-05-15 Hitachi Ltd 高周波モジュールおよびその製造方法
US5994166A (en) 1997-03-10 1999-11-30 Micron Technology, Inc. Method of constructing stacked packages
US6137693A (en) * 1998-07-31 2000-10-24 Agilent Technologies Inc. High-frequency electronic package with arbitrarily-shaped interconnects and integral shielding
JP2000091751A (ja) * 1998-09-10 2000-03-31 Toyo Commun Equip Co Ltd 積層基板を用いた高周波回路
JP3538045B2 (ja) * 1998-12-09 2004-06-14 三菱電機株式会社 Ｒｆ回路モジュール
US6310386B1 (en) * 1998-12-17 2001-10-30 Philips Electronics North America Corp. High performance chip/package inductor integration
US6122171A (en) * 1999-07-30 2000-09-19 Micron Technology, Inc. Heat sink chip package and method of making
JP2001111232A (ja) * 1999-10-06 2001-04-20 Sony Corp 電子部品実装多層基板及びその製造方法
JP3798597B2 (ja) 1999-11-30 2006-07-19 富士通株式会社 半導体装置
US7247932B1 (en) * 2000-05-19 2007-07-24 Megica Corporation Chip package with capacitor
JP4497683B2 (ja) * 2000-09-11 2010-07-07 ローム株式会社 集積回路装置
KR100426500B1 (ko) 2001-07-03 2004-04-13 앰코 테크놀로지 코리아 주식회사 반도체패키지
US20030006494A1 (en) 2001-07-03 2003-01-09 Lee Sang Ho Thin profile stackable semiconductor package and method for manufacturing
SG104279A1 (en) * 2001-11-02 2004-06-21 Inst Of Microelectronics Enhanced chip scale package for flip chips
JP2003273321A (ja) * 2002-03-13 2003-09-26 Toshiba Corp 半導体モジュール
KR101166575B1 (ko) * 2002-09-17 2012-07-18 스태츠 칩팩, 엘티디. 적층형 패키지들 간 도선연결에 의한 상호연결을 이용한반도체 멀티-패키지 모듈 및 그 제작 방법
US7049691B2 (en) * 2002-10-08 2006-05-23 Chippac, Inc. Semiconductor multi-package module having inverted second package and including additional die or stacked package on second package

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5783870A (en) * 1995-03-16 1998-07-21 National Semiconductor Corporation Method for connecting packages of a stacked ball grid array structure
US6274929B1 (en) * 1998-09-01 2001-08-14 Texas Instruments Incorporated Stacked double sided integrated circuit package
US6472741B1 (en) * 2001-07-14 2002-10-29 Siliconware Precision Industries Co., Ltd. Thermally-enhanced stacked-die ball grid array semiconductor package and method of fabricating the same

Also Published As

Publication number Publication date
CN1574309A (zh) 2005-02-02
JP3858854B2 (ja) 2006-12-20
TWI282153B (en) 2007-06-01
KR100627099B1 (ko) 2006-09-25
US7217993B2 (en) 2007-05-15
JP2005019568A (ja) 2005-01-20
KR20050001368A (ko) 2005-01-06
TW200501345A (en) 2005-01-01
US20050006745A1 (en) 2005-01-13

Similar Documents

Publication Publication Date Title
CN1326234C (zh) 堆栈型半导体装置
CN100563405C (zh) 立体电子电路装置及其中继基板和中继框
US6534879B2 (en) Semiconductor chip and semiconductor device having the chip
US6057601A (en) Heat spreader with a placement recess and bottom saw-teeth for connection to ground planes on a thin two-sided single-core BGA substrate
US7268426B2 (en) High-frequency chip packages
CN100461403C (zh) 半导体器件
CN101371353B (zh) 电子装置封装体、模块以及电子装置
US9006098B2 (en) Impedance controlled electrical interconnection employing meta-materials
US20050030231A1 (en) High frequency circuit module
JP3426842B2 (ja) 高周波用電力増幅器
US20070053167A1 (en) Electronic circuit module and manufacturing method thereof
CN100511614C (zh) 多芯片堆叠的封装方法及其封装结构
JP2010199286A (ja) 半導体装置
US20040004285A1 (en) BGA substrate via structure
CN101286500A (zh) 半导体模块及便携设备
US20100244274A1 (en) Wiring board
JP2008124072A (ja) 半導体装置
CN101752338A (zh) 球栅阵列封装结构及其封装工艺
JP2009182087A (ja) 積層型半導体パッケージおよび電子装置
CN100514585C (zh) 具有电感的晶片级构装结构及其构装方法
CN102769005A (zh) 半导体封装构造及其制造方法
CN114188312B (zh) 封装屏蔽结构和屏蔽结构制作方法
CN219998479U (zh) 电子器件
US20230048468A1 (en) Semiconductor emi shielding component, semiconductor package structure and manufacturing method thereof
CN112740845B (zh) 模块

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: FUJITSU MICROELECTRONICS CO., LTD.

Free format text: FORMER OWNER: FUJITSU LIMITED

Effective date: 20081107

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20081107

Address after: Tokyo, Japan

Patentee after: Fujitsu Microelectronics Ltd.

Address before: Kanagawa

Patentee before: Fujitsu Ltd.

C56 Change in the name or address of the patentee

Owner name: FUJITSU SEMICONDUCTOR CO., LTD.

Free format text: FORMER NAME: FUJITSU MICROELECTRON CO., LTD.

CP01 Change in the name or title of a patent holder

Address after: Japan's Kanagawa Prefecture Yokohama

Patentee after: FUJITSU MICROELECTRONICS Ltd.

Address before: Japan's Kanagawa Prefecture Yokohama

Patentee before: Fujitsu Microelectronics Ltd.

CP02 Change in the address of a patent holder

Address after: Japan's Kanagawa Prefecture Yokohama

Patentee after: Fujitsu Microelectronics Ltd.

Address before: Tokyo, Japan

Patentee before: Fujitsu Microelectronics Ltd.

ASS Succession or assignment of patent right

Owner name: SUOSI FUTURE CO., LTD.

Free format text: FORMER OWNER: FUJITSU SEMICONDUCTOR CO., LTD.

Effective date: 20150513

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20150513

Address after: Kanagawa

Patentee after: SOCIONEXT Inc.

Address before: Yokohama City, Kanagawa Prefecture, Japan

Patentee before: FUJITSU MICROELECTRONICS Ltd.

CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20070711

Termination date: 20210623