CN1300856C - Thin-film transistor structure and producing method thereof - Google Patents
Thin-film transistor structure and producing method thereof Download PDFInfo
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- CN1300856C CN1300856C CNB031363393A CN03136339A CN1300856C CN 1300856 C CN1300856 C CN 1300856C CN B031363393 A CNB031363393 A CN B031363393A CN 03136339 A CN03136339 A CN 03136339A CN 1300856 C CN1300856 C CN 1300856C
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Abstract
The present invention relates to a thin film transistor structure and a manufacture method thereof. The structure comprises a substrate, a semiconductor layer, a plurality of adjacent transistors and a pair of lightly doped drains (LDD), wherein the semiconductor layer is formed on the substrate; each transistor comprises a grid electrode and a pair of source electrode/ drain electrode regions. The grid electrode is positioned on the semiconductor layer. The pair of source electrode/ drain electrode regions are positioned in the semiconductor layers on both sides of the grid electrode. The pair of LLD are positioned in the semiconductor layer under the outside side walls of both of the two outside grid electrodes of the grid electrode. The semiconductor layer between the adjacent grid electrodes essentially does not have LDD. The thin film transistor structure simultaneously has the advantages of decreasing the element leakage current and maintaining the element supply current.
Description
Technical field
The present invention relates to a kind of thin-film transistor (thin film transistor, TFT) structure and preparation method thereof, be particularly to a kind of only have outermost (outermost) lightly doped drain (Lightly DopedDrain, multi-grid electrode film transistor structure LDD) and preparation method thereof.
Background technology
Polycrystalline SiTFT (Poly-Si TFT) has been widely used in active matrix-type liquid crystal display device (active matrix liquid crystal display, AMLCD) with static RAM (static random access memory, SRAM) in, be compared to amorphous silicon film transistor (amorphous TFT), because multi-crystal TFT lattice arrangement neat (order), help the transmission of internal electron, electron mobility (mobility) is very fast, in other words, the suffered resistance value of portion is less within it for electronics, cause having down in off position serious leakage current (leakage current) problem, make LCD loss electric charge, perhaps make the non-firm power consumption of SRAM.In order to address this problem, prior art develops lightly doped drain (lightly doped drain, LDD) structure are used for reducing the electric field at drain electrode contact-making surface place, thereby reduce leakage current.Have a high series impedance between source/drain electrode and suppress its conducting electric current (on-current) but the LDD structure can make, and if the LDD number many more, resistance value is just high more, the conducting electric current will be low more.Usually adopt multi grid in order to make element have stable reliability at work, and the LDD number of general multi grid (number of gates N 〉=2) is N times of device of single gate structure, that is to say, general multi grid has more LDD number, have shortcomings such as the conducting of causing electric current reduction, shown in Figure 1A.Below just in conjunction with Figure 1B～1D, the manufacture method of the multi-crystal TFT of the existing LDD of having multi grid is described.
At first, see also Figure 1B, a substrate 0 is provided, this substrate 0 is an insulation transparent substrate, includes the gate insulator 4 that semi-conductor layer 2 and covers semiconductor layer 2 on its surface.In existing manufacture method, at first on gate insulator 4, utilize conventional lithographic techniques to define the first photoresist layer 6 of a patterning, then utilize the first photoresist layer 6 to carry out a light ion doping injection technology 8, so that the semiconductor layer 2 that is covered by the first photoresist layer 6 does not form a light ion doped region 10 (N as mask
-Doped region).
Secondly, see also Fig. 1 C, order divests the first photoresist layer 6, utilize conventional lithographic techniques to redefine out the second photoresist layer 12 of a patterning on gate insulator 4 again, then utilize the second photoresist layer 12 to implement a heavy doping ion injection technology 14, so that the semiconductor layer 2 that is covered by this mask does not form a heavy ion doped region 16 (N as mask
+Doped region), be used as source/drain region.And the gap zone of above-mentioned light ion doped region 10 and heavy ion doped regions 16 promptly is a lightly mixed drain area 17 (LDD zone), is used as the LDD structure.
At last, see also Fig. 1 D, at first divest the second photoresist layer 12, then utilize sputter (Sputtering) method to deposit a grid conducting layer 18 on gate insulator 4, and define the multi grid of a patterning, it has a first grid metal and a second grid metal, constitutes existing thin-film transistor structure with multi-grid component, and the LDD number that it had equals 4.
Below, the manufacture method of the multi-crystal TFT of the another kind of existing LDD of having multi grid is described again in conjunction with Fig. 1 E～1G.
At first, see also Fig. 1 E, a substrate 20 is provided, this substrate 20 is insulation transparent substrate, includes the gate insulator 24 that semi-conductor layer 22 and covers semiconductor layer 22 on its surface.In existing manufacture method, at first on gate insulator 24, utilize sputtering method to deposit a grid conducting layer 26, and define the multi grid of a patterning, it has a first grid metal and a second grid metal, then utilize first grid metal and second grid metal to implement a light dope ion implantation technology 28, so that the semiconductor layer 22 that is covered by this mask does not form a light ion doped region 30 (N as mask
-Doped region).
Secondly, see also Fig. 1 F, define the photoresist layer 32 of a patterning on above-mentioned gate metal, and cover the part light ion doped region of these gate metal both sides, this part light ion doped region is reserved as a lightly mixed drain area 34 (LDD zone).And utilize this photoresist layer 32 to implement a heavy doping ion injection technology 36 as mask, so that the semiconductor layer 22 that is covered by this mask does not form a heavy ion doped region 38 (N
+Doped region), be used as source/drain region.
At last, see also Fig. 1 G, divest photoresist layer 32, constitute existing thin-film transistor structure with multi-grid component, the LDD number that it had equals 4.
Yet, though existing have multigrid thin-film transistor structure and have LDD,, but because of the LDD number that it had equals 4, cause between source/drain electrode resistance value too high can reduce the leakage current of element, therefore the conducting electric current reduces.Similarly, if the number of gates of this multi grid extends to N (N 〉=2), then the LDD number will increase to 2N, and the situation of high value will be more serious this moment, have influence on the drive current of supply element.
Summary of the invention
Therefore, the purpose of this invention is to provide a kind of multi-grid electrode film transistor structure that only has outermost LDD and preparation method thereof.
Another object of the present invention provides to have simultaneously and reduces the element leakage current and keep a kind of multi-grid electrode film transistor structure that only has outermost LDD of element supply of current and preparation method thereof.
The invention is characterized in that the LDD decreased number with multi grid is 2, can have the advantage that reduces the element leakage current and keep the element supply of current simultaneously.And if number of gates extends to N (N 〉=2), still keep LDD number=2, i.e. this design also is applicable to the element of N 〉=2 (N is a number of gates).
To achieve the above object, the invention provides a kind of manufacture method that only has the multi-grid electrode film transistor structure of outermost LDD, comprise the following steps: at first, a substrate is provided.Then, form and define a patterned semiconductor layer on substrate surface.Secondly, form a gate insulator on substrate and cover semiconductor layer.Then, on gate insulator, define the first photoresist layer of a patterning, wherein the first photoresist layer covers a plurality of grids fate and gate insulator therebetween, and utilize the first photoresist layer to implement a light dope ion implantation technology as mask, so that the semiconductor layer that is covered by this mask does not form a light ion doped region.Then, order divests the first photoresist layer, again on gate insulator, define the second photoresist layer of a patterning, wherein the second photoresist layer covers the light ion doped region of a plurality of grids fate and part, and utilize the second photoresist layer to implement a heavy doping ion injection technology as mask, so that the semiconductor layer of masked covering does not form a heavy ion doped region, be used as source/drain region.Then, divest the second photoresist layer.At last, form a grid conducting layer on gate insulator and define a plurality of adjacent grids.
To achieve the above object, the invention provides the another kind of manufacture method that only has the multi-grid electrode film transistor structure of outermost LDD, comprise the following steps: at first, a substrate is provided.Secondly, form and define a patterned semiconductor layer on substrate surface.Then, form a gate insulator on substrate and cover semiconductor layer.Then, on gate insulator, form a grid conducting layer and define a plurality of adjacent grid of a patterning.Then, utilize these a plurality of grids to implement a light dope ion implantation technology, so that the semiconductor layer that is covered by this mask does not form a light ion doped region as mask.Then, on these a plurality of grids, define the photoresist layer of a patterning, and cover the outside sidewall of outermost both sides grid in these grids and this light ion doped region of part.Come again, utilize this photoresist layer and a plurality of grid to implement a heavy doping ion injection technology, so that the semiconductor layer that is covered by this mask does not form a heavy ion doped region, as source/drain region as mask.At last, divest this photoresist layer again.
For purpose of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described below in detail.
Description of drawings
Figure 1A shows the influence of LDD structure for the leakage current and the conducting electric current of multi-grid electrode film transistor element.
Figure 1B～1D shows the existing method schematic diagram that utilizes non-self-aligned manner (Non self-alignment) to make the multi-grid electrode film transistor structure with LDD.
Fig. 1 E～1G shows the existing method schematic diagram that utilizes self-aligned manner (Self-alignment) to make the multi-grid electrode film transistor structure with LDD.
Fig. 2 A～2E shows that the present invention utilizes non-self-aligned manner (Non self-alignment) to make the method schematic diagram of the multi-grid electrode film transistor structure that only has outermost LDD.
Fig. 3 A～3E shows that the present invention utilizes self-aligned manner (Self-alignment) to make the method schematic diagram of the multi-grid electrode film transistor structure that only has outermost LDD.
Description of reference numerals
(existing part)
0 substrate, 2 semiconductor layers
4 gate insulators, 6 first photoresist layers
8 slight ion doping 10 light ion doped region (N
-Doped region)
12 second photoresist layers, 14 severe ion doping
16 heavy ion doped regions, 17 lightly mixed drain areas
(N
+Doped region) (LDD zone)
18 grid conducting layers, 20 substrates
22 semiconductor layers, 24 gate insulators
26 grid conducting layers, 28 slight ion dopings
30 light ion doped regions, 32 photoresist layers
(N
-Doped region)
34 lightly mixed drain areas (LDD zone), 36 severe ion dopings
38 heavy ion doped regions
(N
+Doped region)
(part of the present invention)
40 substrates, 42 semiconductor layers
44 gate insulators, 46 first photoresist layers
48 slight ion doping 50 light ion doped region (N
-Doped region)
52 second photoresist layers, 54 lightly mixed drain area (LDD zone)
56 severe ion dopings, 58 heavy ion doped region (N
+Doped region)
59 grid conducting layers, 60 substrates
62 semiconductor layers, 64 gate insulators
68 slight ion doping 70 light ion doped region (N
-Doped region)
72 photoresist layers, 74 lightly mixed drain area (LDD zone)
76 severe ion dopings, 78 heavy ion doped region (N
+Doped region)
66 grid conducting layers
Embodiment
First embodiment
Fig. 2 A～2E shows the manufacture method of the thin-film transistor structure of first embodiment of the invention.
At first, see also Fig. 2 A, for example on the surface of glass, utilize chemical vapour deposition (CVD) and etch process at a transparent insulation substrate 40, for example be semiconductor layer 42 definition of polysilicon layer and be formed on a presumptive area that with one the thickness range that it deposited is about 400～600 dusts.
Then, see also Fig. 2 B, utilizing chemical vapour deposition technique to deposit a gate insulator 44 for example is that gate oxide is covered on the surface and part substrate that semiconductor layer 42 for example is a polysilicon layer, and the thickness preferable range that it deposited is 500～1500 dusts.
Then, see also Fig. 2 C, the first photoresist layer 46 that defines a patterning for example is on the gate oxide in gate insulator 44, and cover a plurality of grids fate and gate insulator 44 therebetween, and utilize the first photoresist layer 46 to implement a light dope ion implantation technology 48 as mask, for example be the light dope ion implantation technology of phosphorus (P) or arsenic (As) ion, its preferred doping content scope is 0.2e
13～5e
13Cm
-2, so that not the semiconductor layer 42 that is covered by this mask for example polysilicon layer form a light ion doped region 50.
Come again, see also Fig. 2 D, order divests the first photoresist layer 46, again for example be the second photoresist layer 52 that defines a patterning on the gate oxide at gate insulator 44, wherein the second photoresist layer 52 covers a plurality of grids fate and part light ion doped region, and this part light ion doped region is reserved as lightly mixed drain area (LDD zone) 54, and utilize the second photoresist layer 52 to implement a heavy doping ion injection technology 56 as mask, for example be the heavy doping ion injection technology of phosphorus (P) or arsenic (As) ion, its preferred doping content scope is 0.2e
15～5e
15Cm
-2, so that not the semiconductor layer 42 that is covered by this mask for example polysilicon layer form a heavy ion doped region 58, be used as source/drain region.
At last, order divests the second photoresist layer 52, utilize again sputter (Sputtering) method deposit a grid conducting layer 59 for example a metal molybdenum layer in gate insulator 44 for example on the gate oxide, and define a plurality of adjacent grids, shown in Fig. 2 E, wherein a plurality of adjacent number of gates are more than or equal to 2; But in Fig. 2 E,, only draw two grids in order to simplify accompanying drawing.
Second embodiment
Fig. 3 A～3E shows the manufacture method of the thin-film transistor structure of second embodiment of the invention.
At first, see also Fig. 3 A, for example on the surface of glass, utilize chemical vapour deposition (CVD) and etch process at a transparent insulation substrate 60, for example be semiconductor layer 62 definition of polysilicon layer and be formed on a presumptive area that with one the thickness range that it deposited is about 400～600 dusts.
Then, see also Fig. 3 B, utilizing chemical vapour deposition technique to deposit a gate insulator 64 for example is that gate oxide is covered on the surface and part substrate that semiconductor layer 62 for example is a polysilicon layer, and the thickness preferable range that it deposited is 500～1500 dusts.
Then, see also Fig. 3 C, utilize sputter (Sputtering) method form a grid conducting layer 66 for example a metal molybdenum layer in gate insulator 64 for example on the gate oxide, the preferable range of the molybdenum layer thickness that it deposited is 1000～5000 dusts, and defining a plurality of adjacent grid of a patterning, wherein a plurality of adjacent number of gates are more than or equal to 2.
Then, still seeing also Fig. 3 C, utilize above-mentioned grid to implement a light dope ion implantation technology 68 as mask, for example is the light dope ion implantation technology of phosphorus (P) or arsenic (As) ion, and its preferred doping content scope is 0.2e
13～5e
13Cm
-2, so that not the semiconductor layer 62 that is covered by this mask for example polysilicon layer form a light ion doped region 70.
Come again, see also Fig. 3 D, for example define the photoresist layer 72 of a patterning on the metal molybdenum layer at above-mentioned grid conducting layer 66, and cover the outside sidewall and the part light ion doped region of outermost both sides grid in these a plurality of grids, and this part light ion doped region is reserved as lightly mixed drain area (LDD zone) 74.Utilizing this photoresist layer 72 and grid to implement a heavy doping ion injection technology 76 as mask again, for example is the heavy doping ion injection technology of phosphorus (P) or arsenic (As) ion, and its preferred doping content scope is 0.2e
15～5e
15Cm
-2,, be used as source/drain region so that the semiconductor layer 62 that is covered by this mask for example is not that polysilicon layer forms a heavy ion doped region 78.
At last, divest above-mentioned photoresist layer 72, form the multi-grid electrode film transistor structure that only has outermost example LDD shown in Fig. 3 E.Wherein, be reduced graph 3C～3E, only draw two grids.
The present invention also utilizes above-mentioned execution mode to make a kind of thin-film transistor structure, comprising: a substrate; Semi-conductor layer is formed on this substrate; A plurality of adjacent transistors, each transistor comprise a grid and the semiconductor layer pair of source that is positioned at these grid both sides that is arranged on this semiconductor layer; And a pair of lightly doped drain (lightly doped drain LDD), is arranged in this semiconductor layer under the outside sidewall of these grid outermost both sides grids, and does not have LDD in the semiconductor layer between the neighboring gates in fact.
Existing have multigrid thin-film transistor structure (number of gates is N) though have LDD, can reduce the leakage current of element, but too much cause between source/drain electrode resistance value too high because of it has LDD number 2N, therefore the conducting electric current reduces and badly influences the drive current of supplying element.
The feature of the inventive method is to utilize that the hard mask of zones of different size defines the position that only has outermost LDD symmetry in the photoresist technology, promptly be arranged in the beneath semiconductor layer of outside sidewall of outermost both sides, a plurality of grids Shen grid, as for not having LDD in the semiconductor layer between the neighboring gates in fact.
Therefore the method according to this invention with the LDD decreased number to 2 of multi grid, can have the advantage that reduces the element leakage current and keep the element supply of current simultaneously.No matter and number of gates N what are (N 〉=2), still keep the LDD number to equal 2.
Though the present invention discloses as above in conjunction with a preferred embodiment; right its is not in order to limit the present invention; those skilled in the art; without departing from the spirit and scope of the present invention; can do a little change and retouching; for example above-mentioned execution mode is to be that example describes with N-MOS, also can be according to above-mentioned making P-MOS element, so protection scope of the present invention is with being as the criterion that claim was defined.
Claims (22)
1. thin-film transistor structure comprises:
One substrate;
Semi-conductor layer is formed on this substrate;
A plurality of adjacent transistors, each transistor comprise one and are arranged in the grid on this semiconductor layer and are positioned at the doped region of the semiconductor layer of these grid both sides as source/drain region;
Wherein a pair of lightly doped drain is arranged in this beneath semiconductor layer of outside sidewall of this a plurality of grid outermosts both sides grid, and does not have lightly doped drain in the semiconductor layer between the neighboring gates;
Wherein the outside in the grid of outermost both sides refers to not that side in the face of neighboring gates in these a plurality of grids.
2. thin-film transistor structure as claimed in claim 1, wherein this substrate is made of glass.
3. thin-film transistor structure as claimed in claim 1, wherein this semiconductor layer is a polysilicon layer.
4. thin-film transistor structure as claimed in claim 1, wherein these a plurality of grids comprise gate insulator and grid conducting layer.
5. thin-film transistor structure as claimed in claim 4, wherein this gate insulator is an one silica layer.
6. thin-film transistor structure as claimed in claim 4, wherein this grid conducting layer is a molybdenum layer.
7. the manufacture method of a thin-film transistor comprises the following steps:
One substrate is provided;
Form and define a patterned semiconductor layer on this substrate surface;
Form a gate insulator on this substrate and cover this semiconductor layer;
On this gate insulator, define the first photoresist layer of a patterning, wherein this first photoresist layer covers a plurality of grids fate and gate insulator therebetween, and utilize this first photoresist layer to implement a light dope ion implantation technology as mask, so that the semiconductor layer that is covered by this mask does not form a light ion doped region;
Order divests this first photoresist layer, on this gate insulator, redefine out the second photoresist layer of a patterning, wherein this second photoresist layer covers a plurality of grids fate and part light ion doped region, and utilize this second photoresist layer to implement a heavy doping ion injection technology as mask, so that the semiconductor layer that is covered by this mask does not form a heavy ion doped region, be used as source/drain region;
Divest this second photoresist layer; And
Form a grid conducting layer on this gate insulator and define a plurality of adjacent grids;
8. the manufacture method of thin-film transistor as claimed in claim 7, wherein these a plurality of adjacent number of gates equal 2.
9. method as claimed in claim 8, wherein these a plurality of adjacent number of gates are greater than 2.
10. method as claimed in claim 7, wherein this substrate is made of glass.
11. method as claimed in claim 7, wherein this semiconductor layer is a polysilicon layer.
12. method as claimed in claim 7 wherein utilizes chemical vapour deposition technique to deposit this gate insulator of about 500～1500 dusts of a thickness range.
13. method as claimed in claim 7 wherein utilizes sputtering method to deposit this grid conducting layer.
14. method as claimed in claim 13, wherein this grid conducting layer is a molybdenum layer.
15. the manufacture method of a thin-film transistor, this method comprises the following steps:
One substrate is provided;
Form and define a patterned semiconductor layer on this substrate surface;
Form a gate insulator on this substrate and cover this semiconductor layer;
Form a grid conducting layer on this gate insulator and define a plurality of adjacent grid of a patterning;
Utilize these a plurality of grids to implement a light dope ion implantation technology, so that the semiconductor layer that is covered by this mask does not form a light ion doped region as mask;
On these a plurality of grids, define the photoresist layer of a patterning, and cover the outside sidewall of outermost both sides grid in these a plurality of grids and this light ion doped region of part;
Utilize this photoresist layer and these a plurality of grids to implement a heavy doping ion injection technology, so that the semiconductor layer that is covered by this mask does not form a heavy ion doped region, as source/drain region as mask;
Divest this photoresist layer; And
Wherein the outside in the grid of outermost both sides refers to not that side in the face of neighboring gates in these a plurality of grids.
16. method as claimed in claim 15, wherein these a plurality of adjacent number of gates equal 2.
17. method as claimed in claim 16, wherein these a plurality of adjacent number of gates are greater than 2.
18. method as claimed in claim 17, wherein this substrate is made of glass.
19. method as claimed in claim 15, wherein this semiconductor layer is a polysilicon layer.
20. method as claimed in claim 15 wherein utilizes chemical vapour deposition technique to deposit this gate insulator of about 500～1500 dusts of a thickness range.
21. method as claimed in claim 15 wherein utilizes sputtering method to deposit this grid conducting layer.
22. method as claimed in claim 21, wherein this grid conducting layer is a molybdenum layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031363393A CN1300856C (en) | 2003-05-29 | 2003-05-29 | Thin-film transistor structure and producing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031363393A CN1300856C (en) | 2003-05-29 | 2003-05-29 | Thin-film transistor structure and producing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1553515A CN1553515A (en) | 2004-12-08 |
| CN1300856C true CN1300856C (en) | 2007-02-14 |
Family
ID=34323304
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB031363393A Expired - Lifetime CN1300856C (en) | 2003-05-29 | 2003-05-29 | Thin-film transistor structure and producing method thereof |
Country Status (1)
| Country | Link |
|---|---|
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5412493A (en) * | 1992-09-25 | 1995-05-02 | Sony Corporation | Liquid crystal display device having LDD structure type thin film transistors connected in series |
| JP2002141358A (en) * | 2001-08-09 | 2002-05-17 | Matsushita Electric Ind Co Ltd | Thin film transistor and liquid crystal display unit using the same |
-
2003
- 2003-05-29 CN CNB031363393A patent/CN1300856C/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5412493A (en) * | 1992-09-25 | 1995-05-02 | Sony Corporation | Liquid crystal display device having LDD structure type thin film transistors connected in series |
| JP2002141358A (en) * | 2001-08-09 | 2002-05-17 | Matsushita Electric Ind Co Ltd | Thin film transistor and liquid crystal display unit using the same |
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| Publication number | Publication date |
|---|---|
| CN1553515A (en) | 2004-12-08 |
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Granted publication date: 20070214 |