CN1564313A - Thin film transistor and its mfg. method - Google Patents
Thin film transistor and its mfg. method Download PDFInfo
- Publication number
- CN1564313A CN1564313A CNA2004100315243A CN200410031524A CN1564313A CN 1564313 A CN1564313 A CN 1564313A CN A2004100315243 A CNA2004100315243 A CN A2004100315243A CN 200410031524 A CN200410031524 A CN 200410031524A CN 1564313 A CN1564313 A CN 1564313A
- Authority
- CN
- China
- Prior art keywords
- area
- layer
- doped region
- photoresist layer
- grid layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 33
- 238000000034 method Methods 0.000 title claims description 67
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 42
- 229920002120 photoresistant polymer Polymers 0.000 claims description 67
- 229920005591 polysilicon Polymers 0.000 claims description 35
- 238000004519 manufacturing process Methods 0.000 claims description 32
- 239000000758 substrate Substances 0.000 claims description 26
- 239000012212 insulator Substances 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 10
- 239000011248 coating agent Substances 0.000 claims description 9
- 238000000576 coating method Methods 0.000 claims description 9
- 238000004380 ashing Methods 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 239000011521 glass Substances 0.000 claims description 4
- 238000009413 insulation Methods 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 238000002955 isolation Methods 0.000 abstract 2
- 150000002500 ions Chemical class 0.000 description 14
- 238000005516 engineering process Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 238000007687 exposure technique Methods 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 238000002834 transmittance Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000003384 imaging method Methods 0.000 description 2
- 238000005224 laser annealing Methods 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000002238 attenuated effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
- H01L29/78627—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile with a significant overlap between the lightly doped drain and the gate electrode, e.g. GOLDD
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
A polycrystalline silicon layer of thin film transistor includes a channel area, a first doping area and a second doping area. The first doping area is formed between the channel area and the second doping area. Doping density in first doping area is smaller than doping density in second doping area. A grid pole isolation layer is formed on the polycrystalline silicon layer, and a grid pole layer including first area and second area is formed on the grid pole isolation layer. Thickness of the said first area is larger than thickness of the said second area. First area of the grid pole layer covers the channel area, and second area of the grid pole layer covers the first doping area, and the grid pole layer does not cover the said second doping area.
Description
Technical field
The present invention relates to a kind of thin-film transistor technologies, particularly a kind of (self-aligned) lightly doped drain (lightly doped drain, LDD) structure and manufacture method thereof of aiming at voluntarily.
Background technology
(thin filmtransistor TFT) is intended for the switch module of pixel to the thin-film transistor of LCD (liquid crystal display is hereinafter to be referred as LCD), generally can be distinguished into two kinds of patterns of non-crystalline silicon tft and multi-crystal TFT.Because the carrier mobility integrated level higher, drive circuit of multi-crystal TFT is preferable, leakage current is less, so multi-crystal TFT more often is applied in the circuit of high service speed, as: static random access memory (static random access memory, SRAM).But the problem of leakage current (leakage current) easily takes place down in multi-crystal TFT in off position, and regular meeting causes LCD loss electric charge or makes the consumption of SRAM non-firm power.In order to address this problem, (lightly doped drain, LDD) structure are used for reducing the electric field of drain junction place (drain junction), can effectively improve the phenomenon of leakage current to adopt a lightly doped drain at present.
The method that first kind of prior art made the LDD structure utilize earlier a photoresist layer as mask to carry out a heavy doping ion injection process, in a polysilicon layer, to form a heavily doped region.Make then a grid layer as mask to carry out a light dope ion injecting process, so that the not doped region of the exposure of polysilicon layer becomes a lightly doped region.Thus, lightly doped region is used as a LDD structure, and heavily doped region is used as one source/drain region, and the not doped region of polysilicon layer then is to be used as a channel region.Yet said method must accurately be controlled the position that the pattern of grid layer just can be guaranteed the LDD structure.And, be subject to the alignment error (photo misalignment) of exposure technique, be not easy to control the side-play amount of grid layer, then twice ion injecting process can make the problem of the offset of LDD structure can be more serious.Very and, the complex process of said method, production speed are low, the lateral length of also wayward LDD structure.
The method that second kind of prior art made the LDD structure make earlier a grid layer as mask to carry out a light dope ion injecting process, in a polysilicon layer, to form a lightly doped region.Then, utilize a photoresist layer as mask to carry out a heavy doping ion injection process, make exposure place of lightly doped region become a heavily doped region.Thus, the lightly doped region that is not exposed is used as a LDD structure, and heavily doped region is used as one source/drain region, and the not doped region of polysilicon layer then is to be used as a channel region.Though this kind method can be avoided the influence of the side-play amount of grid layer to the LDD structure, but the phenomenon of the offset of LDD structure still can take place in the ion injecting process of exposure technique alignment error and twice, and can't improve complex process, problem that productive rate is low.
Summary of the invention
Therefore, purpose of the present invention just is to provide a kind of thin-film transistor and manufacture method thereof, and the profile by the control grid layer is used as the mask of LDD structure, then can finish LDD structure and source/drain diffusion region simultaneously in ion injecting process once.
For reaching above-mentioned purpose, a polysilicon layer that the invention provides a kind of thin-film transistor comprises a channel region, one first doped region and one second doped region, wherein this first doped region is formed between this channel region and this second doped region, and the doping content of this first doped region is less than the doping content of this second doped region.One gate insulator is formed on this polysilicon layer.One grid layer is formed on this gate insulator, and comprises a first area and a second area, and wherein the thickness of this first area is greater than the thickness of this second area.The first area of this grid layer covers this channel region, and the second area of this grid layer covers this first doped region, and this grid layer does not cover this second doped region.
For reaching above-mentioned purpose, the invention provides the manufacture method of a thin-film transistor, comprise the following steps: to provide a substrate; Form a polysilicon layer on a presumptive area of this substrate; Form a gate insulator in this substrate, to cover this polysilicon layer; Form a grid layer on this gate insulator; Form a photoresist layer on this grid layer, this photoresist layer includes a first area and a second area, and the thickness of this first area is greater than the thickness of this second area; Use this photoresist layer as mask carrying out one first etching work procedure, the first area and the grid layer beyond the second area of this photoresist layer are removed; Carry out an ashing operation,, and the second area of this photoresist layer removed fully the first area thinning of this photoresist layer; The first area of using this photoresist layer as mask to carry out one second etching work procedure, this grid layer beyond the first area of this photoresist layer is removed to a predetermined thickness, then this grid layer comprises a first area and a second area, wherein the first area of this grid layer corresponds to the first area of this photoresist layer, the second area of this grid layer corresponds to the second area of this photoresist layer, and the thickness of the first area of this grid layer is greater than the thickness of the second area of this grid layer; Remove this photoresist layer; And use this grid layer as mask carrying out an ion injecting process, in this polysilicon layer, to form not doped region, one first doped region and one second doped region.Wherein, this not doped region covered by the first area of this grid layer, this first doped region is covered by the second area of this grid layer, this second doped region is exposed to the second area outside of this grid layer, this first doped region is formed at this not between doped region and this second doped region, and the doping content of this first doped region is less than the doping content of this second doped region.
Description of drawings
The generalized section of the manufacture method of the LDD structure of the thin-film transistor of Figure 1A to Fig. 1 H demonstration first embodiment of the invention.
The generalized section of the manufacture method of the LDD structure of the thin-film transistor of Fig. 2 A to Fig. 2 E demonstration second embodiment of the invention.
Description of reference numerals:
Substrate～10;
Resilient coating～12;
Silicon nitride layer～14;
Silicon oxide layer～16;
Polysilicon layer～18;
Doped region～18a not;
Light doping section～18b;
Heavily doped region～18c;
Gate insulator～20;
Grid layer～22;
First area～22a;
Second area～22b;
Photoresist layer～24;
First area～24a;
Second area～24b;
Photomask～26;
First area～26a;
Second area～26b;
The 3rd zone～26c;
Ion injecting process～28;
Nmos area territory～I;
PMOS zone～II;
First polysilicon layer～18I;
Second polysilicon layer～18II;
Doped region～18a not;
N
-Doped region～18b;
N
+Doped region～18c;
First grid layer～22I;
Second grid layer～22II;
Convex character shape photoresist layer～24I;
Rectangular shape photoresist layer～24II.
Embodiment
For above and other objects of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
First embodiment
See also Figure 1A to Fig. 1 H, the generalized section of the manufacture method of the LDD structure of the thin-film transistor of its demonstration first embodiment of the invention.
Shown in Figure 1A, a substrate 10 is provided, be preferably a transparent insulation substrate, for example: substrate of glass.Then, in substrate 10, deposit a resilient coating 12, be preferably the stacked material of a silicon nitride layer 14 and one silica layer 16.Then, on resilient coating 12, make a polysilicon layer 18, be preferably a low-temperature polycrystalline silicon layer.For example: adopt low temperature polycrystalline silicon (low temperature polycrystallinesilicon, LTPS) operation, prior to forming a noncrystalline silicon layer on the glass substrate, (excimer laser annealing, mode ELA) converts amorphous silicon layer to the polysilicon material to utilize heat treatment or quasi-molecule laser annealing then.Thereafter, shown in Figure 1B, deposition one gate insulator 20 is preferably one silica layer in above-mentioned substrate 10, in order to cover polysilicon layer 18 and resilient coating 12.Then, deposition one grid layer 22 is preferably a conductive material layer, a metal level or a polysilicon layer on gate insulator 20.
Shown in Fig. 1 C, the photoresist layer 24 of one convex character shape is provided on grid layer 22, it includes a first area 24a and two second area 24b, and wherein this first area 24a is arranged between this second area 24b, and the thickness of first area 24a is greater than the thickness of second area 24b.Be preferably, carry out the exposure imaging process by 26 pairs of photoresist layers of a decrescendo phase transfer (attenuated phase shifting) photomask 24.For example, photomask 26 includes: a first area 26a, and its light transmittance is almost 0%; One second area 26b is used as a phase transfer (phase-shifting) district around first area 26a, and its light transmittance is about 40～60%; And one the 3rd regional 26c around second area 26b, its light transmittance is 100%.Thus, utilize 26 pairs one eurymeric resistance materials of decrescendo photomask to carry out after the photo-mask process, different light transmittances by each zone, can make each opposite position of photoresist layer 24 accept the exposure effect of varying strength, so that the etched degree of depth difference of each opposite position, just can make the thickness of the thickness of first area 24a, and then constitute a convex character shape profile greater than second area 24b.Certainly, decrescendo photomask 26 also can be applied to the minus resistance material, as long as by changing each the regional position relation on the decrescendo photomask 26, just can form identical convex character shape profile on the minus resistance material.
Shown in Fig. 1 D, the photoresist layer 24 that utilizes convex character shape, is removed the grid layer beyond first, second regional 24a, 24b of photoresist layer 24 22 to carry out an etching work procedure as mask.Then, shown in 1E figure, carry out an ashing (ashing) operation, then can make the less thick of first area 24a, until removing second area 24b fully with thinning photoresist layer 24.Then, shown in Fig. 1 F, utilize photoresist layer 24 to carry out a dry ecthing operation, the grid layer 22 beyond the 24a of first area is removed to a predetermined thickness, then can make grid layer 22 become a convex character shape profile as mask.Follow-up with after photoresist layer 24 removals, the result is shown in Fig. 1 G.The grid layer 22 of convex character shape comprises a first area 22a and two second area 22b, and this first area 22a is arranged between this second area 22b, and the thickness D of first area 22a
1Thickness D greater than second area 22b
2, and first area 22a corresponds to the first area 24a of photoresist layer 24.Be preferably the thickness D of second area 22b
2Less than 1000 .
At last, shown in Fig. 1 H, the grid layer 22 that utilizes convex character shape to carry out an ion injecting process 28, can form not doped region 18a, a light doping section 18b and a heavily doped region 18c as mask in polysilicon layer 18.Doped region 18a is not covered by the first area 22a of grid layer 22, is intended for a channel region.Light doping section 18b is covered by the second area 22b of grid layer 22, and is formed at the not both sides of doped region 18a, is intended for a LDD structure.Heavily doped region 18c is exposed to the both sides of the second area 22b of grid layer 22, and is formed at the both sides of light doping section 18b, is intended for one source/drain diffusion region.With a nmos type thin-film transistor is example, and channel region is a P type polysilicon layer, and the LDD structure is a N
-Doped region, source/drain region are a N
+Doped region.With a pmos type thin-film transistor is example, and channel region is a N type polysilicon layer, and the LDD structure is a P
-Doped region, source/drain region are a P
+Doped region.
Above-mentioned method of manufacturing thin film transistor has the following advantages:
The first, the suitable etching work procedure of photoresist layer 24 collocation by convex character shape can make the thickness D of first area 22a of the grid layer 22 of convex character shape
1Thickness D greater than second area 22b
2But, and the precalculated position of source of exposure/drain diffusion region, so second area 22b can be used as the mask of the ion injecting process of LDD structure, and then can accurately control position, lateral length and the symmetry of LDD structure.
The second, can avoid the alignment error of exposure technique that the LDD structure is caused the problem of offset, so can solve the misalignment problem of LDD structure.
The 3rd, a photomask capable of reducing using and only carry out the primary ions injection process, thus have the processing step of simplification, reduce advantages such as technology cost, and then can improve product percent of pass, increase speed of production, to meet mass-produced demand.
Second embodiment
The inventive method can be simultaneously carried out in various degree doping to adjust its component characteristic, to simplify technology, improve product percent of pass, to increase speed of production to nmos area territory and PMOS zone.Below be the manufacture method of the LDD structure of example explanation thin-film transistor with a nmos area territory and a PMOS zone.
See also Fig. 2 A to Fig. 2 E, the generalized section of the manufacture method of the LDD structure of the thin-film transistor of its demonstration second embodiment of the invention.
Shown in Fig. 2 A, a substrate 10 is provided, it comprises a nmos area territory I and a PMOS area I I.Then, deposition one resilient coating 12 in substrate 10, it comprises a silicon nitride layer 14 and one silica layer 16.Then, on the resilient coating 12 of nmos area territory I, make one first polysilicon layer 18I, and on the resilient coating 12 of PMOS area I I, make one second polysilicon layer 18II simultaneously.Then, deposit a gate insulator 20 and a grid layer 22 in regular turn.And then, according to the described mode of first embodiment, by a decrescendo photomask one photoresist layer 24 is carried out the exposure imaging process, then can on the grid layer 22 of nmos area territory I, provide a convex character shape photoresist layer 24I, and a rectangular shape photoresist layer 24II can be provided on the grid layer 22 of PMOS area I I simultaneously.Wherein, the photoresist layer 24I of convex character shape includes a first area 24a and two second area 24b, and first area 24a is arranged between this second area 24b, and the thickness of first area 24a is greater than the thickness of second area 24b.
Shown in Fig. 2 B, utilize convex character shape photoresist layer 24I and rectangular shape photoresist layer 24II as mask to carry out an etching work procedure, grid layer beyond photoresist layer 24I, the 24II zone 22 is removed, then can in the I of nmos area territory, form a first grid layer 22I, and in PMOS area I I, form a second grid layer 22II.Then, shown in Fig. 2 C, carry out an ashing (ashing) operation, then can make the less thick of the first area 24a of convex character shape photoresist layer 24I, until removing second area 24b fully with thinning photoresist layer 24I, 24II.Simultaneously, also can make the less thick of rectangular shape photoresist layer 24II.
Then, shown in Fig. 2 D, utilize photoresist layer 24I, 24II to carry out a dry etch process, first, second grid layer 22I, 22II beyond photoresist layer 24I, the 24II zone are removed, become a convex character shape profile until first grid layer 22I as mask.The first grid layer 22I of convex character shape comprises a first area 22a and two second area 22b, and this first area 22a is arranged between this second area 22b, and the thickness D of first area 22a
1Thickness D greater than second area 22b
2, and first area 22a corresponds to the first area 24a of photoresist layer 24.Be preferably the thickness D of second area 22b
2Scope is less than 1000 .Profile as for second grid layer 22II is still kept rectangular shape.
At last, shown in Fig. 1 H, after photoresist layer 24 removed, provide another photoresist layer 30 to cover the PMOS area I, the first grid layer 22I that utilizes convex character shape again so that nmos area territory I is carried out an ion injecting process 28, then can form not doped region 18a, a N as mask in the first polysilicon layer 18I
-A doped region 18b and a N
+Doped region 18c.Wherein, doped region 18a is not covered by the first area 22a of first grid layer 22I, is intended for a channel region.N
-Doped region 18b is covered by the second area 22b of first grid layer 22I, and is formed at the not both sides of doped region 18a, is intended for a LDD structure.N
+Doped region 18c is exposed to the both sides of the second area 22b of first grid layer 22I, and is formed at N
-The both sides of doped region 18b are intended for one source/drain diffusion region.
Above-mentioned method of manufacturing thin film transistor has and is same as the described advantage of first embodiment, comprise: position, lateral length and the symmetry that can accurately control the LDD structure, the alignment error that can avoid exposure technique causes the problem of offset to the LDD structure, and a photomask capable of reducing using and only carry out the primary ions injection process.In addition, other has an advantage, and second embodiment of the invention can be simultaneously carried out in various degree doping to adjust its component characteristic, to simplify technology, improve product percent of pass, to increase speed of production to nmos area territory and PMOS zone.
Though the present invention with preferred embodiment openly as above; right its is not in order to limit the present invention; those skilled in the art under the premise without departing from the spirit and scope of the present invention; change and retouching when doing some, so protection scope of the present invention is as the criterion with the scope that appending claims was defined.
Claims (16)
1. the manufacture method of a thin-film transistor comprises the following steps:
One substrate is provided;
Form a polysilicon layer on a presumptive area of described substrate;
Form a gate insulator in described substrate, to cover described polysilicon layer;
Form a grid layer on described gate insulator;
Form a photoresist layer on described grid layer, described photoresist layer comprises a first area and a second area, and the thickness of described first area is greater than the thickness of described second area;
Use described photoresist layer as mask carrying out one first etching work procedure, the first area and the grid layer beyond the second area of described photoresist layer are removed;
Carry out an ashing operation,, and the second area of described photoresist layer removed fully the first area thinning of described photoresist layer;
The first area of using described photoresist layer as mask to carry out one second etching work procedure, described grid layer beyond the first area of described photoresist layer is removed to a predetermined thickness, then described grid layer comprises a first area and a second area, the first area of wherein said grid layer corresponds to the first area of described photoresist layer, the second area of described grid layer corresponds to the second area of described photoresist layer, and the thickness of the first area of described grid layer is greater than the thickness of the second area of described grid layer;
Remove described photoresist layer; And
Use described grid layer as mask carrying out an ion injecting process, in described polysilicon layer, to form not doped region, one first doped region and one second doped region;
Wherein, described not doped region is covered by the first area of described grid layer;
Wherein, described first doped region is covered by the second area of described grid layer;
Wherein, described second doped region is exposed to the second area outside of described grid layer;
Wherein, described first doped region is formed between described not doped region and described second doped region; And
Wherein, the doping content of described first doped region is less than the doping content of described second doped region.
2. the manufacture method of thin-film transistor as claimed in claim 1, wherein said substrate is a transparent insulation substrate or a substrate of glass.
3. the manufacture method of thin-film transistor as claimed in claim 1, a low temperature polycrystalline silicon operation is used in the making of wherein said polysilicon layer.
4. the manufacture method of thin-film transistor as claimed in claim 1, wherein said gate insulator is an one silica layer.
5. the manufacture method of thin-film transistor as claimed in claim 1, wherein said grid layer is a conductive layer, a metal level or a polysilicon layer.
6. the manufacture method of thin-film transistor as claimed in claim 1, wherein said photoresist layer is a convex character shape profile, it comprises a first area and two second areas, and described first area protrudes between described two second areas.
7. the manufacture method of thin-film transistor as claimed in claim 1, the manufacture method of wherein said photoresist layer uses a decrescendo to transfer photomask mutually to carry out a photo-mask process.
8. the manufacture method of thin-film transistor as claimed in claim 1, wherein after carrying out described second etching work procedure, described grid layer becomes a convex character shape profile, it comprises a first area and two second areas, and described first area protrudes between described two second areas.
9. the manufacture method of thin-film transistor as claimed in claim 1, wherein before making described polysilicon layer, other comprises a step: form a resilient coating in described substrate.
10. the manufacture method of a thin-film transistor comprises the following steps:
One substrate is provided, and it comprises the TFT regions of one first conductivity type and the TFT regions of one second conductivity type;
Form first, second polysilicon layer respectively on the TFT regions of first, second conductivity type of described substrate;
Form a gate insulator in described substrate, to cover described first, second polysilicon layer;
Form a grid layer on described gate insulator;
Form first, second photoresist layer respectively on the grid layer of the TFT regions of described first, second conductivity type,
Wherein, on the TFT regions of described first conductivity type, described first photoresist layer is a convex character shape profile, and it comprises a first area and a second area, and the thickness of described first area is greater than the thickness of described second area;
Wherein, on the TFT regions of described second conductivity type, described second photoresist layer is a rectangular shape profile;
Use described first, second photoresist layer as mask carrying out one first etching work procedure, first, second grid layer beyond described first, second photoresist layer is removed;
Carry out an ashing operation, with described first, second photoresist layer thinning, until the second area of removing described first photoresist layer fully;
The first area of using described first photoresist layer as mask to carry out one second etching work procedure, described first grid layer beyond the first area of described first photoresist layer is removed to a predetermined thickness, and then described first grid layer becomes a convex character shape profile;
Wherein said first grid layer comprises a first area and a second area, and the first area of wherein said first grid layer corresponds to the first area of described first photoresist layer;
The second area of described first grid layer corresponds to the second area of described first photoresist layer, and the thickness of the first area of described first grid layer is greater than the thickness of the second area of described first grid layer;
Remove described first, second photoresist layer; And
Use described first grid layer as mask carrying out an ion injecting process, in described first polysilicon layer, to form not doped region, one first doped region and one second doped region;
Wherein, described not doped region is covered by the first area of described first grid layer;
Wherein, described first doped region is covered by the second area of described first grid layer;
Wherein, described second doped region is exposed to the second area outside of described first grid layer;
Wherein, described first doped region is formed between described not doped region and described second doped region; And
Wherein, the doping content of described first doped region is less than the doping content of described second doped region.
11. the manufacture method of thin-film transistor as claimed in claim 10, wherein said substrate are a transparent insulation substrate or a substrate of glass.
12. the manufacture method of thin-film transistor as claimed in claim 10, the making of wherein said polysilicon layer are used a low temperature polycrystalline silicon operation.
13. the manufacture method of thin-film transistor as claimed in claim 10, wherein said gate insulator are one silica layer.
14. the manufacture method of thin-film transistor as claimed in claim 10, wherein said grid layer are a conductive layer, a metal level or a polysilicon layer.
15. the manufacture method of thin-film transistor as claimed in claim 10, the manufacture method of wherein said first photoresist layer use a decrescendo to transfer photomask mutually to carry out a photo-mask process.
16. the manufacture method of thin-film transistor as claimed in claim 10, before making described first, second polysilicon layer, other comprises a step: form a resilient coating in described substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100315243A CN1331202C (en) | 2004-03-19 | 2004-03-19 | Thin film transistor and its mfg. method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100315243A CN1331202C (en) | 2004-03-19 | 2004-03-19 | Thin film transistor and its mfg. method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1564313A true CN1564313A (en) | 2005-01-12 |
| CN1331202C CN1331202C (en) | 2007-08-08 |
Family
ID=34481263
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100315243A Expired - Fee Related CN1331202C (en) | 2004-03-19 | 2004-03-19 | Thin film transistor and its mfg. method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1331202C (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100452323C (en) * | 2005-10-12 | 2009-01-14 | 统宝光电股份有限公司 | Method for mfg. film transistor |
| CN1835190B (en) * | 2005-03-17 | 2010-09-29 | 海力士半导体有限公司 | Partial implantation method for semiconductor manufacturing |
| WO2013139148A1 (en) * | 2012-03-19 | 2013-09-26 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof, and display device |
| CN104900712A (en) * | 2015-06-09 | 2015-09-09 | 武汉华星光电技术有限公司 | TFT substrate structure manufacturing method and TFT substrate structure thereof |
| WO2016090694A1 (en) * | 2014-12-12 | 2016-06-16 | 深圳市华星光电技术有限公司 | Doping method and doping equipment for array substrate |
| WO2016090687A1 (en) * | 2014-12-11 | 2016-06-16 | 深圳市华星光电技术有限公司 | Array substrate and method for manufacturing same |
| CN105789325A (en) * | 2016-04-18 | 2016-07-20 | 深圳市华星光电技术有限公司 | Thin film transistor, preparation method thereof and CMOS device |
| WO2017156808A1 (en) * | 2016-03-15 | 2017-09-21 | 深圳市华星光电技术有限公司 | Method for manufacturing thin film transistor |
| WO2017201781A1 (en) * | 2016-05-26 | 2017-11-30 | 深圳市华星光电技术有限公司 | Thin film transistor, method for preparing thin film transistor, and cmos device |
| CN107819012A (en) * | 2017-10-10 | 2018-03-20 | 武汉华星光电半导体显示技术有限公司 | N-type TFT and preparation method thereof, OLED display panel and preparation method thereof |
| US10672912B2 (en) | 2017-10-10 | 2020-06-02 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | N-type thin film transistor, manufacturing method thereof and manufacturing method of an OLED display panel |
| CN116544243A (en) * | 2023-06-14 | 2023-08-04 | 深圳市华星光电半导体显示技术有限公司 | Driving substrate and display panel |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101436544B (en) * | 2007-11-16 | 2010-12-01 | 中华映管股份有限公司 | Method for manufacturing thin-film transistor |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08162403A (en) * | 1994-12-06 | 1996-06-21 | Semiconductor Energy Lab Co Ltd | Ashing method for organic mask |
| JPH09148266A (en) * | 1995-11-24 | 1997-06-06 | Semiconductor Energy Lab Co Ltd | Method for manufacturing semiconductor device |
| CN1151405C (en) * | 2000-07-25 | 2004-05-26 | 友达光电股份有限公司 | Thin-film transistor LCD and its manufacture |
-
2004
- 2004-03-19 CN CNB2004100315243A patent/CN1331202C/en not_active Expired - Fee Related
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1835190B (en) * | 2005-03-17 | 2010-09-29 | 海力士半导体有限公司 | Partial implantation method for semiconductor manufacturing |
| US7939418B2 (en) | 2005-03-17 | 2011-05-10 | Hynix Semiconductor Inc. | Partial implantation method for semiconductor manufacturing |
| CN100452323C (en) * | 2005-10-12 | 2009-01-14 | 统宝光电股份有限公司 | Method for mfg. film transistor |
| WO2013139148A1 (en) * | 2012-03-19 | 2013-09-26 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof, and display device |
| WO2016090687A1 (en) * | 2014-12-11 | 2016-06-16 | 深圳市华星光电技术有限公司 | Array substrate and method for manufacturing same |
| WO2016090694A1 (en) * | 2014-12-12 | 2016-06-16 | 深圳市华星光电技术有限公司 | Doping method and doping equipment for array substrate |
| CN104900712A (en) * | 2015-06-09 | 2015-09-09 | 武汉华星光电技术有限公司 | TFT substrate structure manufacturing method and TFT substrate structure thereof |
| WO2017156808A1 (en) * | 2016-03-15 | 2017-09-21 | 深圳市华星光电技术有限公司 | Method for manufacturing thin film transistor |
| CN105789325A (en) * | 2016-04-18 | 2016-07-20 | 深圳市华星光电技术有限公司 | Thin film transistor, preparation method thereof and CMOS device |
| WO2017181449A1 (en) * | 2016-04-18 | 2017-10-26 | 深圳市华星光电技术有限公司 | Thin film transistor, manufacturing method for thin film transistor, and cmos device |
| CN105789325B (en) * | 2016-04-18 | 2019-05-03 | 深圳市华星光电技术有限公司 | Thin film transistor (TFT), the preparation method of thin film transistor (TFT) and cmos device |
| WO2017201781A1 (en) * | 2016-05-26 | 2017-11-30 | 深圳市华星光电技术有限公司 | Thin film transistor, method for preparing thin film transistor, and cmos device |
| CN107819012A (en) * | 2017-10-10 | 2018-03-20 | 武汉华星光电半导体显示技术有限公司 | N-type TFT and preparation method thereof, OLED display panel and preparation method thereof |
| US10672912B2 (en) | 2017-10-10 | 2020-06-02 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | N-type thin film transistor, manufacturing method thereof and manufacturing method of an OLED display panel |
| CN116544243A (en) * | 2023-06-14 | 2023-08-04 | 深圳市华星光电半导体显示技术有限公司 | Driving substrate and display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1331202C (en) | 2007-08-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105552027B (en) | The production method and array substrate of array substrate | |
| JP2650543B2 (en) | Matrix circuit drive | |
| CN105470197A (en) | Production method of low temperature poly silicon array substrate | |
| CN105489552A (en) | Manufacturing method of LTPS array substrate | |
| CN1564313A (en) | Thin film transistor and its mfg. method | |
| CN1514469A (en) | Crystal mask, amorphous silicon crystallization method and method of manufacturing array base plate using same | |
| US20200321475A1 (en) | Manufacturing method for ltps tft substrate | |
| CN100339964C (en) | Method for making MOS having light doped drain electrode | |
| CN1265430C (en) | Low-temp. polycrystalline silicon film transistor and its polycrystalline silicon layer making method | |
| CN100358157C (en) | Thin film transistor and its manufacturing method | |
| US20050090045A1 (en) | Method for fomring a self-aligned ltps tft | |
| CN100583417C (en) | Making method for CMOS thin film transistor | |
| US11862642B2 (en) | Display panel, array substrate, and manufacturing method thereof | |
| US11469329B2 (en) | Active switch, manufacturing method thereof and display device | |
| CN104716092A (en) | Manufacturing method of array substrate and manufacturing device | |
| WO2016165223A1 (en) | Polycrystalline silicon thin-film transistor, manufacturing method therefor, and display device | |
| CN105355593A (en) | TFT substrate manufacturing method and TFT substrate | |
| CN105161458B (en) | The preparation method of TFT substrate | |
| CN1763975A (en) | Thin film transistor and producing method thereof | |
| CN101399273B (en) | Image display system and fabrication method thereof | |
| CN108878354B (en) | CMOS thin film transistor and manufacturing method of LTPS array substrate | |
| CN100397656C (en) | Thin film transistor of multi-grid structure and manufacturing method thereof | |
| JP2003031780A (en) | Method for manufacturing thin film transistor panel | |
| CN113113428B (en) | Array substrate and preparation method thereof | |
| CN1892995A (en) | Method for making low-temperature polycrystal silicon film transistor with low doped drain electrode structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20070808 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |