CN1195422A - 半导体元件的安装方法 - Google Patents
半导体元件的安装方法 Download PDFInfo
- Publication number
- CN1195422A CN1195422A CN97190666A CN97190666A CN1195422A CN 1195422 A CN1195422 A CN 1195422A CN 97190666 A CN97190666 A CN 97190666A CN 97190666 A CN97190666 A CN 97190666A CN 1195422 A CN1195422 A CN 1195422A
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- semiconductor element
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- electrode
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 160
- 238000000034 method Methods 0.000 title claims abstract description 95
- 239000000758 substrate Substances 0.000 claims abstract description 104
- 238000009434 installation Methods 0.000 claims description 53
- 229920003023 plastic Polymers 0.000 claims description 35
- 239000004033 plastic Substances 0.000 claims description 35
- 239000007767 bonding agent Substances 0.000 claims description 28
- 208000034189 Sclerosis Diseases 0.000 claims description 20
- 239000004593 Epoxy Substances 0.000 claims description 15
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 238000010438 heat treatment Methods 0.000 claims description 7
- 238000002156 mixing Methods 0.000 claims description 4
- 239000011347 resin Substances 0.000 abstract description 3
- 229920005989 resin Polymers 0.000 abstract description 3
- 238000003825 pressing Methods 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 16
- 238000004519 manufacturing process Methods 0.000 description 12
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 5
- 239000002313 adhesive film Substances 0.000 description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052799 carbon Inorganic materials 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 239000002245 particle Substances 0.000 description 4
- 238000010521 absorption reaction Methods 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 239000000843 powder Substances 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 229920000426 Microplastic Polymers 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000010923 batch production Methods 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 210000000988 bone and bone Anatomy 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 235000019628 coolness Nutrition 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000010791 quenching Methods 0.000 description 1
- 230000000171 quenching effect Effects 0.000 description 1
- 239000010979 ruby Substances 0.000 description 1
- 229910001750 ruby Inorganic materials 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/113—Via provided in pad; Pad over filled via
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Abstract
提供能够以高可靠性连接半导体元件的电极和电路基板的电路的半导体元件的安装方法。具有在形成于电路基板4的孔8内充填导电胶7,形成外部电极端子33的工序;把外部电极端子33和半导体元件1的电极2上所形成的凸起3进行定位的工序;按压半导体元件1,使得孔8内的导电胶7和凸起3相互接触,电气连接半导体元件1的电极2和电路基板4的外部电极端子33的工序。
Description
本发明涉及用于在半导体元件的电路基板上以高可靠性高密度安装倒装片型半导体元件的半导体元件的安装方法。
根据附图说明现有的半导体元件的安装方法。
(现有例1)
图16示出了现有例1中的在电路基板上安装了半导体元件的剖面图。
图16中,1是半导体元件,在半导体元件1上形成电极2,在电极2上,利用引线键合法形成由金、铜、铝、焊锡等构成的凸起(金属球形凸起)15。
4是由绝缘性基体材料构成的电路基板,在该电路基板4上形成作为布线的铜箔5,另外,在电路基板4上形成镀铜的外部电极端子6。为了得到电路基板内的导通,在形成于电路基板4内的孔8中,充填导电胶7。
22是使银、金、镍、碳等导电粉末均匀分布在苯酚和环氧系列树脂上的导电胶(导电粘接剂)。通过凸起15,把电路基板4的外部电极端子6和半导体元件1的电极2进行电气连接。在电路基板4和半导体元件1之间充填环氧系列树脂20。
下面,说明以上那样构成的半导体元件的安装方法。
利用复制法在形成于半导体元件1的各电极2上的凸起15上复制导电胶22,然后,进行装载,使得该凸起15与应该安装的电路基板4的外部电极端子6相一致,随后,进行加热硬化导电胶22。这样,使半导体元件1的电极2和电路基板4的外部电极端子6进行电气连接。而且,在连接以后,在半导体元件1和电路基板4的间隔之间充填环氧系列树脂20,利用其硬化收缩力,得到导电胶22的导电粉末的连续的接触,从而确保电气的、机械的可靠性。
(现有例2)
图17示出现有例2中的在电路基板上安装了半导体元件的剖面图。和上述图16的构成相同的构成标注相同的标号并且省略说明。
图17中,23是用电镀法在电极2上形成的金属凸起,在金属凸起23上,实施例如镀铜,然后在其上面实施镀金24。25是外部电极端子,16是保护半导体元件1的有源面的钝化膜。
下面,说明以上那样构成的半导体元件的安装方法。
利用复制法在形成于半导体元件1的各电极2上的凸起23上复制导电胶22,然后,进行装载,使得该凸起23与应该安装的电路基板4的外部电极端子25相一致,随后,进行加热硬化导电胶22。这样,把半导体元件1的电极2和电路基板4的外部电极端子25进行电气连接。而且,在连接以后,在半导体元件1和电路基板4的间隔之间充填环氧系列树脂20,利用其硬化收缩力,得到导电胶22的导电粉末的连续的接触,从而确保电气的、机械的可靠性。
(现有例3)
图18示出现有例3中的在电路基板上安装了半导体元件的剖面图。和上述图16、图17的构成相同的构成标注相同的符号并且省略说明。
图18中,3是用电镀法在电极2上形成的凸起(凸起电极),26是绝缘性粘接剂膜,在绝缘性粘接剂26内,均匀地分布由镍、焊锡、碳等构成的导电粒子27。
下面,说明以上那样构成的半导体元件的安装方法。
把绝缘性粘接剂膜26定位在由半导体元件1以及电路基板4的外部电极端子25所夹持的位置,然后,同时进行加热和加压。这样,粘接剂膜26溶解,在电极25间的空间中流动,由凸起3和外部电极端子25固定保持导电粒子27,凸起3和外部电极端子25导通。另一方面,在空间中,由于保持导电粒子27在粘接剂中分散的状态,因此确保了绝缘性。粘接剂膜26冷却后,就被硬化,把半导体元件1和电路基板4进行固定,确保连接可靠性。
然而,上述现有例1(或现有例2)的半导体元件的安装方法中,如图19所示,在用复制法把导电胶膜28复制到凸起15上,并且把凸起15接合到电路基板4的外部电极6上的时候,存在着难于控制复制导电胶22的数量,并且在导电胶22的数量稍微多一点的时候电极2之间由导电胶22相互连接,形成短路电路30这样的问题。还有,如果电路基板4稍微弯曲,半导体元件1的电极2和电路基板4的外部电极端子6就不会通过导电胶22相互接触,从而存在有在电极2和外部电极端子6之间变成为电气断开状态这样的问题。
另外,如图20所示,在把环氧系列树脂20充填到半导体元件1和电路基板4的间隙中时,存在着由于把封入到注射器31中的环氧系列树脂从半导体元件1的周围注入进去,需要十分钟以上的注入时间因而成为缩短半导体元件1的生产线的生产间隔时间的障碍这样的问题。
另外,在上述现有例3的半导体元件的安装方法中,由于通过把导电粒子27固定保持在半导体元件1的电极2和电路基板4的电极25之间使之导通,因此如图21所示,如果在电路基板4上边稍微有弯曲或起伏A,则在保持导电粒子27分散在粘接剂26中的原样不变的状态下,半导体元件1的凸起3和电路基板4的电极25相互不接触,其结果,存在有凸起3和电极25之间成为电气断开状态这样的问题。另外,现有例3的安装方法是以弯曲和起伏很少的玻璃基板为对象使用的,不能用于树脂基板上。
本发明的目的在于提供具有下述效果的半导体元件的安装方法,该方法具有不发生电极间的短路和断路这样的不良状态,能够进行电气可靠性高的安装,能够大幅度地削减密封工序的时间,能够缩短半导体元件生产线的生产间隔时间。
为了达到上述目的,本发明的半导体元件的安装方法的特征在于具有在把电路基板的电路和半导体元件的电极进行连接的上述电路基板的固定位置处形成孔的工序;在上述孔内充填导电胶形成外部电极端子的工序;在上述半导体元件的电极上形成凸起的工序;把在上述外部电极端子和半导体元件的电极上形成的凸起进行定位的工序;按压上述半导体元件,使得上述孔内的上述导电胶和上述凸起进行接触,把上述半导体元件的上述电极和上述电路基板的上述外部电极端子进行电气连接的工序。
采用上述半导体元件的安装方法,通过使电路基板的孔内所充填的导电胶和半导体元件的电极上形成的凸起相互接触,把上述半导体元件的电极和电路基板的外部电极端子进行电气连接,从而不发生电极之间的短路和断路这样的不良状态,其结果能够进行电气可靠性高的安装。
图1是本发明实施形态1中安装以后的半导体元件和电路基板的接合剖面图。
图2按顺序示出了本发明实施形态1中的安装工序。
图3是本发明实施形态1中安装以后的半导体元件和电路基板的接合剖面图。
图4是本发明实施形态1中安装以后的半导体元件和电路基板的接合剖面图。
图5顺序地示出了本发明实施形态2中的引线键合法的工序。
图6是用本发明实施形态2中的引线键合法形成的凸起的侧面图。
图7是用本发明实施形态2中的引线键合法形成的两级凸起形状的凸起的侧面图。
图8顺序地示出本发明实施形态2中的安装工序。
图9示出本发明实施形态3中的安装工序。
图10示出本发明实施形态4中的安装工序。
图11示出本发明实施形态5中的安装工序。
图12示出本发明实施形态6中的安装工序。
图13是本发明实施形态6中安装以后的半导体元件和电路基板的接合剖面图。
图14顺序地示出本发明实施形态7中的安装工序。
图15顺序地示出本发明实施形态3中的安装工序。
图16是使用现有的半导体元件的安装方法安装以后的半导体元件和电路基板的接合剖面图。
图17是使用现有的半导体元件的安装方法安装以后的半导体元件和电路基板的接合剖面图。
图18是使用现有的半导体元件的安装方法安装以后的半导体元件和电路基板的接合剖面图。
图19顺序地示出现有的安装工序。
图20说明现有的安装方法中的问题。
图21说明现有的安装方法中的问题。
本发明第1方面的半导体元件的安装方法是这样的方法,其特征在于具有在把电路基板的电路和半导体元件的电极进行连接的上述电路基板的固定位置处形成孔的工序;在上述孔内充填导电胶形成外部电极端子的工序;在上述半导体元件的电极上形成凸起的工序;把上述外部电极端子和在半导体元件的电极上形成的凸起进行定位的工序;按压上述半导体元件,使得上述孔内的上述导电胶和上述凸起进行接触,把上述半导体元件的上述电极和上述电路基板的上述外部电极端子进行电气连接的工序。采用该方法,由于凸起在电路基板的孔内接触到导电胶,进行电气的连接,所以具有不发生断路和短路的作用。
本发明的第2方面是这样的半导体元件的安装方法,其特征在于在方面1的半导体元件的安装方法中,形成在半导体元件电极上的凸起是使用引线键合法形成的金属球形凸起。与使用电镀法形成凸起时仅能形成最大25μm左右高度的低凸起相比,用上述方法的引线键合法能够形成50μm以上高度的高凸起,因此埋入到电路基板孔内的导电胶中的凸起的数量增大,具有能够进行更高可靠性安装的作用。
本发明的第3方面的半导体元件的安装方法的特征是,在第1方面和第2方面中记述的半导体元件的安装方法中,在按压半导体元件使得电路基板孔内的导电胶和半导体元件电极上的凸起接触以后,添加使用加热工具把上述半导体元件或电路基板的至少一方进行加热,进行上述导电胶的硬化的工序。通过硬化导电胶,更加强了半导体元件和电路基板的固定,能够进行可靠性更高的接合。现有导电胶的硬化是把模块放到烘箱中进行批量处理,与此相对,由于本发明的方法能够同时用同一个设备进行接合,因此具有能够缩短半导体元件生产线生产间隔时间(tact time)的作用。
本发明的第4方面的半导体元件的安装方法的特征是,在第1方面至第3方面的任一项中记述的半导体元件的安装方法中,在把半导体元件的电极和电路基板的外部电极端子进行连接以后,添加向上述半导体元件和上述电路基板之间的间隙流入环氧系列树脂并且进行密封的工序。由于使用环氧系列树脂保护半导体元件的有源面以及电极的表面,因此具有进一步增加连接的可靠性的作用。
本发明第5方面的半导体元件的安装方法的特征在于具有在连接电路基板的电路和半导体元件的电极的上述电路基板的固定位置处形成孔的工序;在上述孔内充填导电胶形成外部电极端子的工序;在上述半导体元件的电极上形成凸起的工序;在形成了上述外部电极端子的电路基板上或在上述半导体元件的凸起上,配置具有热硬化系列树脂或者热可塑系列树脂或者热硬化和热可塑的混合系列树脂的粘接剂薄片的工序;把上述外部电极端子和在半导体元件的电极上形成的凸起进行定位的工序;按压上述半导体元件,由上述凸起突破上述粘接剂薄片,使上述孔内的上述导电胶和上述凸起进行接触,电气连接上述半导体元件的上述电极和上述电路基板的上述外部电极的工序;使用加热工具,对上述半导体元件进行加热,溶解上述粘接剂薄片并且进行硬化的工序。在该方法中,由于在该粘接剂薄片溶解。硬化以后保护半导体元件的有源面以及电极的表面,因此增加了连接的可靠性。进而,使用了粘接剂薄片的情况下的加压硬化所需要的时间大约是30秒,而现有使用环氧系列树脂情况下的硬化时间大约是4个小时,从而,由于大幅度地缩短了本方法中的硬化时间,因此具有能够缩短半导体元件生产线的生产间隔时间的作用。
以下,根据附图说明本发明的实施形态。另外,和现有例的图16~图18的构成相同的构成部分标注相同的标号并且省略说明。
实施形态1
图1是已装配上本发明实施形态1中的半导体元件的电路基板的剖面图。
如图所示,形成在半导体元件1的电极2上的凸起3以埋入到充填于电路基板4的孔中的导电胶7内的状态进行接触并且电气连接电路基板4的外部电极端子6和半导体元件1的电极2。根据图2的工序图,说明本发明的半导体元件的安装方法。
首先,连接电路基板4的外部电极端子6和半导体元件1的电极2。在电路基板4的固定位置处形成孔8,如图2(a)所示,通过移动涂刷器9在上述电路基板4的孔8内印刷并且充填导电胶7,这样,形成电路基板4的外部电极端子33。
接着,如图2(b)所示,用吸附管嘴10吸附半导体元件1,进行凸起3和由充填到孔8内的导电胶7形成的电路基板4的外部电极端子33之间的位置对准。
接着,如图2(c)所示,用吸附管嘴10按压半导体元件1,如图2(d)所示,把凸起3埋入到充填于电路基板4的孔8内的导电胶7中。
其结果,在电路基板4的孔内半导体元件1的凸起3接触到导电胶7,进行电气连接。
另外,电路基板4既可以是如图3所示那样通过内部通孔取得基板内的层间的导通的多层基板,也可以是如图4所示那样通过贯通孔取得层间导通的多层基板。
若采用本实施形态1,则电极2上所形成的凸起3在电路基板4的孔8内埋入并且接触到导电胶7进行电气连接,因此不发生短路,另外扩大了对于电路基板4的弯曲以及起伏的允许范围,不发生断路,能够以高可靠性连接半导体元件1和电路基板4。
实施形态2
图5是示出使用本发明实施形态2中的引线键合法形成半导体元件电极上的凸起的形成方法的工序图,参照图5说明引线键合法。
首先,如图5(a)所示,把用金、铜、铝或者焊锡等制作的金属线11通过用陶瓷和红宝石制作的毛细管13,接着使已通过的金属线11的前端和被称为焊枪的电极14之间进行放电,形成金属球12。
接着,如图5(b)所示,把上述金属球12加到已被预热了的半导体元件1的电极2上,施加超声波振动。这样,借助于温度、压力、超声波振动的作用,把金属球12接合到电极2上。
接着,如图5(C)所示,使毛细管13向垂直方向上升,极力往上拉金属线11,形成图6所示那样的由金属球构成的凸起15。
接着,如同5(d)所示,在使毛细管13上升以后,不再往上拉金属丝11使毛细管13沿着横向滑动下降使金属线11接触到金属球12上,然后,借助于温度和压力、或温度、压力和超声振动的作用,把金属线11接合到金属球12上。
接着,如图5(e)所示,使毛细管13上升,极力往上拉金属线11,如图5(f)以及图7所示那样,形成由金属球构成的二级凸起形状的凸起15。
应用上述方法在半导体元件1的电极2上形成了由金属球构成的凸起15以后,应用图8所示的方法进行半导体元件1和电路基板4的接合。
图8的安装方法和上述实施形态1中说明的方法相同,省略说明。
本实施形态2中,除去实施形态1中的效果以外,还具有下面的效果。现有的用电镀法形成凸起的方法仅能够形成最大25μm左右高度的低凸起,与此相比,通过使用本实施形态的引线键合法能够形成50μm以上高度的高凸起,从而,如图8(e)所示,埋入到电路基板4的孔8内的导电胶7中的凸起5的数量增多,扩大了对于电路基板4的弯曲或者起伏的容许范围,其结果,能够进行更高可靠性的安装。
实施形态3
参照图9说明本发明实施形态3中的半导体元件的安装方法。
图9中,把半导体元件1吸附在吸附管嘴10上,把凸起3位置对准到由充填到孔8中的导电胶7所形成的电路基板4的外部电极端子上,然后,进行按压,把凸起3埋入到导电胶7中。这时,吸附管嘴10用安装在其内部的加热器17进行加热,并且在按压的同时进行导电胶7的硬化。
若采用本实施形态3,则除去上述实施形态1、2中的效果以外,通过硬化导电胶7,能够更牢固地进行半导体元件1和电路基板4的固定,能够进行更高可靠性的结合。还有,现有导电胶7的硬化是把模块放入到烘箱中进行批量处理,与此相对,本实施形态的方法由于在结合的同时用同一设备进行硬化,所以能够缩短半导体元件1生产线的生产间隔时间。
实施形态4
参照图10说明本发明实施形态4中的半导体元件的安装方法。
图10中,把半导体元件1吸附在吸附管嘴10上,把凸起3定位到由充填到孔8中的导电胶7所形成的电路基板4的外部电极端子上,然后,进行按压,把凸起3埋入到导电胶7中。这时,保持电路基板4的载物台18用装在内部的加热器17进行加热,通过在按压半导体元件1的同时进行加热,能够在按压的同时进行导电胶7的硬化。
若采用本实施形态4,则除去上述实施形态1、2的效果以外,通过硬化导电胶7,能够更牢固地进行半导体元件1和电路基板4的固定,能够进行更高可靠性的结合。另外,现有导电胶7的硬化是把模块放入到烘箱中进行批量处理,与此相对,本实施形态的方法由于在结合的同时用同一设备进行硬化,所以能够缩短半导体元件1生产线的生产间隔时间。
实施形态5
参照图11说明本发明实施形态5中的半导体元件的安装方法。
如图11所示,在实施形态5中,按压半导体元件1,并且使电路基板4的孔8内的导电胶7接触到半导体元件1的电极2上的凸起15以后,把模块(电路基板4以及半导体元件1)放到传送带32上,在移动的过程中用加热器19加热模块总体,进行导电胶7的硬化。
若采用本实施形态5,则除去上述实施形态1、2中的效果以外,由于使用把模块总体装到传送带32上一边移动一边加热的软溶方式进行导电胶7的硬化,从而还能够和安装一起在同一生产线上进行硬化。因此,不会对半导体元件1的生产线的生产间隔带来影响,能够更牢固地进行半导体元件1和电路基板4的固定,其结果,能够进行更高可靠性的结合。
实施形态6
参照图12说明本发明实施形态6中的半导体元件的安装方法。
如图12所示,在上述实施形态1~5的安装工序中,当把半导体元件1安装到电路基板4上以后,利用注射管31向半导体元件1和电路基板4之间的间隔内充填环氧系列树脂20。
若采用本实施形态6,则除去上述实施形态1~5中的效果以外,如图13所示,还通过环氧系列树脂20的充填,保护了半导体元件1的有源面以及电极2的表面。从而,例如即使模块暴露在高温高湿等的环境中,也能够防止电极2以及凸起3的腐蚀,能够进行更高可靠性的连接。
实施形态7
参照图14说明本发明实施形态7中的半导体元件的安装方法。
首先,如图14(a)所示,在电路基板4的孔8内充填导电胶7形成外部电极端子33以后,在电路基板4上配置具有热硬化系列树脂,或者热可塑系列树脂或者热硬化和热可塑的混合系列树脂的粘接剂薄片21。
另外,还能够使镍、焊锡、碳或者镀金塑料粒子等在粘接剂薄片21上均匀地分散。
接着,如图14(b)所示,用吸附管嘴10吸附半导体元件1,把凸起15位置对准在由充填到孔8内的导电胶7所形成的电路基板4的外部电极端子33上。
然后,如图14(e)所示,按压半导体元件1,用凸起15突破粘接剂薄片21,把凸起15埋入到导电胶7中。这时,吸附管嘴10用安装在内部的加热器17加热,在按压的同时进行粘接剂薄片21的溶解和硬化。
若采用本实施形态7,则除去上述实施形态1~2中的效果外,如图14(d)所示,由于溶解并且硬化粘接剂薄片21,保护了半导体元件1的有源面以及电极2的表面,更增强了连接的可靠性。另外,在使用了粘接剂薄片21的情况下,加压.硬化所需要的时间大约是30秒,而现有的使用了环氧系列树脂的硬化时间大约是4个小时,从而,本实施形态中的硬化时间大幅度地缩短,从而能够缩短半导体元件1生产线的生产间隔时间。
实施形态8
参照图15说明本发明实施形态8中的半导体元件的安装方法。
首先,如图15(a)所示,在半导体元件1的电极2上形成了凸起15以后,预先在凸起15上配置具有热硬化系列树脂,或者热可塑系列树脂或者热硬化和热可塑的混合系列树脂的粘接剂薄片21。另外,在粘接剂薄片21上可以先使镍、焊锡、碳或者镀金塑料粒子等均匀地分散好备用。
然后,如图15(b)所示,用吸附管嘴10吸附半导体元件1,把凸起15位置对准到由充填到孔8内的导电胶7形成的电路基板4的外部电极端子33上,然后进行按压,用凸起15突破粘接剂薄片21,把凸起15埋入到导电胶7中。这时,吸附管嘴10用安装在内部的加热器17进行加热,在按压的同时进行粘接剂薄片21的溶解和硬化。
若采用实施形态8,则除去上述实施形态1~2中的效果以外,和实施形态7一样,由于溶解并且硬化粘接剂薄片21,保护了半导体元件1的有源面以及电极2的表面,更增强了连接的可靠性。另外,在使用了粘接剂薄片21的情况下,加压。硬化所需要的时间大约是30秒,而现有的使用了环氧系列树脂的硬化时间大约是4个小时,从而,本实施形态中的硬化时间大幅度地缩短,从而能够缩短半导体元件1生产线的生产间隔时间。
如以上所述,如果采用本发明,通过使形成在半导体元件的电极上的凸起接触到电路基板的孔内的导电胶上,电气连接半导体元件的电极和电路基板的外部电极端子,能够避免电极间的短路,进而,由于扩大了对于电路基板的弯曲或者起伏的允许范围,能够避免电极间的断路,能够进行电气方面高可靠性的安装。
另外,由于预先把粘接剂薄片配置在电路基板上或者半导体元件的凸起上,在安装时,用凸起突破粘接剂薄片,使其接触到电路基板孔内的导电胶上,进行电气连接,同时,由于溶解,硬化粘接剂薄片,能够用粘接剂薄片保护半导体元件的有源面以及电极的表面,从而能够更增加连接的可靠性。另外,在使用了粘接剂薄片的情况下,加压、硬化所需要的时间大约是30秒,而现有的使用了环氧系列树脂情况下的硬化时间大约是4个小时,从而本实施形态中的硬化时间大幅度地缩短,因此能够大幅度地削减密封工序的时间,能够实现半导体元件生产线的生产间隔时间的缩短。
Claims (5)
1.一种半导体元件的安装方法,具有
在连接电路基板的电路和半导体元件的电极的上述电路基板的预定位置形成孔的工序;
在上述孔内充填导电胶,形成外部电极端子的工序;
在上述半导体元件的上述电极上形成凸起的工序;
把上述外部电极端子和上述半导体元件的上述电极上形成的上述凸起进行定位的工序;
按压上述半导体元件,使上述孔内的上述导电胶和上述凸起接触,电气连接上述半导体元件的上述电极和上述电路基板的上述外部电极端子的工序。
2.权利要求1所述的半导体元件的安装方法,特征在于:
上述半导体元件的上述电极上所形成的上述凸起是使用引线键合法形成的金属球形凸起。
3.权利要求1或2所述的半导体元件的安装方法,特征在于:
在按压上述半导体元件,使得充填到上述电路基板的上述孔内的上述导电胶和上述半导体元件的上述电极上的上述凸起相接触以后,添加了用加热工具把上述半导体元件以及上述电路基板中的至少一方进行加热,进行上述导电胶的硬化的工序。
4.权利要求1、2或者3所述的半导体元件的安装方法,特征在于:
在连接了上述半导体元件的上述电极和上述电路基板的上述外部电极端子以后,添加了在上述半导体元件和上述电路基板的间隙中流入环氧系列树脂进行密封的工序。
5.一种半导体元件的安装方法,具有
在连接电路基板的电路和半导体元件的电极的上述电路基板的预定位置形成孔的工序;
在上述孔内充填导电胶形成外部电极端子的工序;
在上述半导体元件的上述电极上形成凸起的工序;
在形成上述外部电极端子的上述电路基板上或者在上述半导体元件的上述凸起上配置具有热硬化系列树脂,或者热可塑系列树脂或者热硬化和热可塑的混合系列树脂的粘接剂薄片的工序;
把上述外部电极端子和上述半导体元件的上述电极上所形成的上述凸起进行定位的工序;
按压上述半导体元件,用上述凸起突破上述粘接剂薄片,使得上述孔内的上述导电胶和上述凸起相接触,电气连接上述半导体元件的上述电极和上述电路基板的上述外部电极端子的工序;用加热工具把上述半导体元件进行加热,溶解并且硬化上述粘接剂薄片的工序。
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1997
- 1997-06-06 WO PCT/JP1997/001971 patent/WO1997047031A1/ja not_active Application Discontinuation
- 1997-06-06 CN CN97190666A patent/CN1110078C/zh not_active Expired - Fee Related
- 1997-06-06 US US09/011,603 patent/US6051093A/en not_active Expired - Fee Related
- 1997-06-06 EP EP97925302A patent/EP0844657A4/en not_active Withdrawn
- 1997-06-06 KR KR10-1998-0700903A patent/KR100457609B1/ko not_active IP Right Cessation
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2000
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US7278564B2 (en) | 2003-05-27 | 2007-10-09 | Seiko Epson Corporation | Method of mounting electronic component, structure for mounting electronic component, electronic component module, and electronic apparatus |
CN100438008C (zh) * | 2006-03-01 | 2008-11-26 | 南茂科技股份有限公司 | 高频集成电路封装构造及其制造方法 |
CN101447443B (zh) * | 2006-08-15 | 2010-06-02 | 南茂科技股份有限公司 | 高频集成电路封装构造的制造方法 |
CN104517912A (zh) * | 2013-09-30 | 2015-04-15 | 南茂科技股份有限公司 | 薄膜覆晶封装结构 |
CN103682043A (zh) * | 2013-11-28 | 2014-03-26 | 天津金玛光电有限公司 | 一种水平式led芯片的固晶方法及采用该方法制备的led光源 |
CN111083879A (zh) * | 2019-07-26 | 2020-04-28 | 微智医疗器械有限公司 | 电子元件与电路板的连接方法、电路板组件及电子设备 |
CN111540722A (zh) * | 2020-07-07 | 2020-08-14 | 甬矽电子(宁波)股份有限公司 | 芯片封装结构及封装方法 |
CN111540722B (zh) * | 2020-07-07 | 2021-05-14 | 甬矽电子(宁波)股份有限公司 | 芯片封装结构及封装方法 |
Also Published As
Publication number | Publication date |
---|---|
KR100457609B1 (ko) | 2005-01-15 |
US6051093A (en) | 2000-04-18 |
CN1110078C (zh) | 2003-05-28 |
JP3610999B2 (ja) | 2005-01-19 |
WO1997047031A1 (en) | 1997-12-11 |
EP0844657A1 (en) | 1998-05-27 |
US6531022B1 (en) | 2003-03-11 |
EP0844657A4 (en) | 1999-04-14 |
JPH09326419A (ja) | 1997-12-16 |
KR19990036235A (ko) | 1999-05-25 |
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