CN118018011A - Locking detection circuit of adjustable delay phase-locked loop - Google Patents
Locking detection circuit of adjustable delay phase-locked loop Download PDFInfo
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Abstract
The invention relates to an adjustable delay phase-locked loop locking detection circuit, which comprises a phase detection module and a delay triggering module, wherein the phase detection module receives a reference clock signal and a feedback clock signal and detects the phase difference of the reference clock signal and the feedback clock signal, and is used for detecting the locking state of the phase-locked loop; the delay triggering module is connected with the phase detection module and is used for carrying out delay processing on the reference clock signal and the feedback clock signal and controlling the detection precision of the phase-locked loop locking detection circuit; the invention has the functions of adjustable locking precision and false triggering locking.
Description
Technical Field
The invention relates to the technical field of phase-locked loops, in particular to a locking detection circuit of an adjustable delay phase-locked loop.
Background
The phase-locked loop is a phase-locked loop, and utilizes an externally input reference signal to control the frequency and the phase of an internal oscillating signal of the loop, so as to realize the automatic tracking of the frequency of an output signal to the frequency of an input signal. The phase-locked loop is a necessary means for generating high-purity signals, has a very wide application range, is an indispensable component in a modern electronic system, such as the fields of radar system testing, satellite communication, navigation, quantum computation and the like, and has higher and higher demands for more reliable and higher-performance phase-locked loops along with the rapid development of the modern electronic technology.
The phase-locked loop is generally composed of a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator and a frequency divider, wherein an output signal of the voltage-controlled oscillator is divided by the frequency divider to generate a feedback clock signal, the phase detector compares a phase difference between a reference clock and the feedback clock, and then the charge pump and the follow-up phase difference are converted into control. When the frequency of the voltage-controlled oscillator changes, the control voltage output by the phase discriminator also changes, so that the frequency of the voltage-controlled oscillator is always locked on the reference frequency which is N times. The frequency range of the signal generated by the design mode is wide, the circuit structure is simple, the volume is small, but a certain problem exists in locking precision and false triggering locking.
Disclosure of Invention
The present invention aims to solve the above-mentioned problems by providing an adjustable delay phase locked loop lock detection circuit which overcomes the shortcomings of the prior art.
The invention is realized by adopting the following technical scheme:
An adjustable delay locked loop lock detection circuit comprising:
The phase detection module receives the reference clock signal and the feedback clock signal, detects the phase difference between the reference clock signal and the feedback clock signal and is used for detecting the locking state of the phase-locked loop;
The delay triggering module is connected with the phase detection module and is used for carrying out delay processing on the reference clock signal and the feedback clock signal and controlling the detection precision of the phase-locked loop locking detection circuit.
Further, the phase detection module comprises a first input unit and a second input unit;
The first input unit comprises a rising edge input signal and a feedback clock signal; the feedback clock signal is used for collecting rising edge input signals;
The second input unit includes a falling edge input signal and a reference clock signal; the reference clock signal is used for collecting a falling edge input signal.
Further, the phase detection module further comprises a plurality of inverters, a first D trigger, a second D trigger and a logic AND gate;
the rising edge input signal is connected with the input end of the phase inverter; the feedback clock signal is connected with the CLK end of the first D trigger through a plurality of inverters;
the falling edge input signal is connected with the input end of the phase inverter; the reference clock signal is connected with the CLK end of the second D flip-flop through a plurality of inverters;
the Q end of the first D trigger and the Q end of the second D trigger are connected with the input end of a logic AND gate in a decomposition mode, and the output end of the logic AND gate is connected with an output signal of the phase detection module in a locking mode.
Further, the delay triggering module comprises a first delay module and a second delay module;
The first delay module and the second delay module comprise N cascaded third D triggers with reset functions;
The locking output signal of the phase detection module is connected with the rst end of each third D trigger, the reference clock signal is connected with the CLK end of each third D trigger, and the Qb end of the third D trigger at the last cascade position is connected with the D end of the third D trigger at the first cascade position.
Further, the number of the inverters is six, the rising edge input signal is connected with the input end of the first inverter, and the output end of the first inverter is connected with the input end of the first delay module; the output end of the first delay module is connected with the D end of the first D trigger; the feedback clock signal is connected with the input end of a second inverter, the output end of the second inverter is connected with the input end of a third inverter, and the output end of the third inverter is connected with the CLK end of the first D trigger;
The falling edge input signal is connected with the input end of a fourth inverter, and the output end of the fourth inverter is connected with the input end of the second delay module; the output end of the second delay module is connected with the D end of the second D trigger; the falling edge input signal is connected with the input end of the fourth inverter, the reference clock signal is connected with the input end of the fifth inverter, the output end of the fifth inverter is connected with the input end of the sixth inverter, and the output end of the sixth inverter is connected with the CLK end of the first D trigger.
Further, the delay triggering module further comprises a fourth D trigger with a reset function;
The Q end of the third D trigger at the last cascade position is connected with the CLK end of the fourth D trigger, and the D end of the fourth D trigger is connected with the locking output signal of the phase detection module.
Compared with the prior art, the invention has the following beneficial technical effects:
The phase-locked loop locking detection circuit comprises a phase detection module and a delay trigger module, wherein the phase detection module is connected with the delay trigger module and is used for detecting a locking state by detecting the phase difference of a reference clock signal and a feedback clock signal, and the delay trigger module is used for controlling the detection precision of the phase-locked loop locking detection circuit by adjusting a first delay module and a second delay module; the delay triggering module has the function of preventing false touch.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of an adjustable delay phase-locked loop lock detection circuit according to an embodiment of the present invention;
Fig. 2 is a schematic diagram of a phase detection module according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a delay trigger module according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a lock detection waveform structure according to an embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
As shown in fig. 1-4, an embodiment of the present invention provides an adjustable delay phase locked loop lock detection circuit, including:
The phase detection module 100, the phase detection module 100 receives the reference clock signal 104 and the feedback clock signal 102, and detects a phase difference between the reference clock signal 104 and the feedback clock signal 102, for detecting a locked state of the phase-locked loop;
The delay trigger module 200 is connected with the phase detection module 100, and the delay trigger module 200 is used for performing delay processing on the reference clock signal 104 and the feedback clock signal 102 and controlling the detection precision of the phase-locked loop locking detection circuit.
As shown in fig. 2, the phase detection module 100 provided in the embodiment of the present invention includes a first input unit and a second input unit;
The first input unit comprises a rising edge input signal 101 and a feedback clock signal 102; the feedback clock signal 102 is used for collecting the rising edge input signal 101;
the second input unit comprises a falling edge input signal 103 and a reference clock signal 104; the reference clock signal 104 is used to collect the falling edge input signal 103.
As shown in fig. 2, the phase detection module 100 provided in the embodiment of the present invention further includes a plurality of inverters, a first D flip-flop 111, a second D flip-flop 112, and a logic and gate 113;
The rising edge input signal 101 is connected with the input end of the inverter; the feedback clock signal 102 is connected to the CLK terminal of the first D flip-flop 111 via a plurality of inverters;
The falling edge input signal 103 is connected with the input end of the inverter; the reference clock signal 104 is connected to the CLK terminal of the second D flip-flop 112 via a plurality of inverters;
The Q-terminal of the first D flip-flop 111 and the Q-terminal of the second D flip-flop 112 are respectively connected to the input terminal of the logic and gate 113, and the output terminal of the logic and gate 113 is connected to the output signal of the phase detection module 100 in a locked manner.
As shown in fig. 3, a delay trigger module 200 provided in an embodiment of the present invention includes a first delay module 201 and a second delay module 202;
The first delay module 201 and the second delay module 202 each comprise N cascaded third D flip-flops 203 with a reset function;
The locked output signal of the phase detection module 100 is used as an input signal of the anti-false touch delay module circuit to be connected with the rst end of each third D flip-flop 203, the reference clock signal 104 is connected with the CLK end of each third D flip-flop 203, and the Qb end of the third D flip-flop 203 at the last cascade position is connected with the D end of the third D flip-flop 203 at the first cascade position.
The following further describes the specific relationship between the phase detection module 100 and the delay trigger module 200 provided by the embodiments of the present invention with reference to the accompanying drawings.
Taking six inverters as an example, the rising edge input signal 101 is connected with the input end of the first inverter 105, and the output end of the first inverter 105 is connected with the input end of the first delay module 201; the output end of the first delay module 201 is connected with the D end of the first D trigger 111; the feedback clock signal 102 is connected with the input end of the second inverter 106, the output end of the second inverter 106 is connected with the input end of the third inverter 107, and the output end of the third inverter 107 is connected with the CLK end of the first D trigger 111; the falling edge input signal 103 is connected with the input end of the fourth inverter 108, and the output end of the fourth inverter 108 is connected with the input end of the second delay module 202; the output end of the second delay module 202 is connected with the D end of the second D trigger 112; the reference clock signal 104 is connected with the input end of the fifth inverter 109, the output end of the fifth inverter 109 is connected with the input end of the sixth inverter 110, and the output end of the sixth inverter 110 is connected with the CLK end of the second D flip-flop 112; the Q-terminal of the first D flip-flop 111 and the Q-terminal of the second D flip-flop 112 are connected to the input terminal of the logic and gate 113 in a split manner, and the output terminal of the logic and gate 113 is connected to the output signal of the phase detection module 100 in a locked manner.
The above-mentioned middle phase detection module 100 detects the locked state by detecting the phase difference between the reference clock signal 104 and the feedback clock signal 102, in which the phase difference between the reference clock signal 104 and the feedback clock signal 102 is approaching to infinity in the ideal locked state, but cannot be achieved in practice, the phase difference can only be made as small as possible, as shown in fig. 4, when the feedback clock signal 102 lags behind the reference clock signal 104, the current phase difference is T1, the phase difference between the rising edge actual sampling signal and the falling edge input signal is also T1, and the detection process is as follows, when the reference clock signal 104 and the feedback clock signal 102 have a certain phase difference, the feedback clock signal 102 is used to collect the phase information of the rising edge input signal 101, and the reference clock signal 104 is used to collect the phase information of the falling edge input signal 103. The accuracy of the output phase-locked loop locking detection signal can be controlled by adjusting the high-level phase difference of the rising edge of the delayed DN_delay signal relative to the rising edge input signal 101/the falling edge input signal 103;
In order to adapt to the application requirements of the phase-locked loop in different scenarios, as shown in fig. 4, the phase difference T2 between the rising edge of the feedback clock signal 102 and the falling edge input signal after delay is the static phase difference detection precision. The smaller T2, the smaller the phase difference between the reference clock signal 104 and the feedback clock signal 102 when the lock circuit outputs the lock instruction signal; by adjusting the first delay module 201 and the second delay module 202, the detection accuracy of the lock detection circuit can be controlled, when the phase-locked loop reaches the lock phase difference, as shown in fig. 2, the first D flip-flop 111 and the second D flip-flop 112 in the phase detection module 100 output a high level, the logic and gate 113 outputs a high level, and the lock signal becomes high.
Since the phase-locked loop always has the condition of neglected phase difference in the locking process, in order to prevent the situation of false triggering of the locking signal, as shown in fig. 3, the delay triggering module 200 further includes a fourth D trigger 204 with a reset function;
The Q terminal of the third D flip-flop 203 in the last cascade position is connected to the CLK of the fourth D flip-flop 204, the D terminal of the fourth D flip-flop 204 is connected to the lock output signal of the phase detection module 100, and the Q terminal of the fourth D flip-flop 204 is used as the final lock output signal.
When the locking signal is low, the module is reset and outputs low level; when the lock signal is high, the final lock output signal is determined by the CLK input of the fourth D flip-flop 204, the reference clock frequency of the fourth D flip-flop 204 is determined by the third D flip-flop cascaded in front, the frequency is the reference clock signal/N, and the specific size can be modified according to the requirement. After delay triggering, the locking indication can not be triggered by mistake, and the influence on the subsequent circuits is avoided.
It should be noted that, in the figure, the clk_ref clock SIGNAL is a reference clock SIGNAL, the clk_fb clock SIGNAL is a feedback clock SIGNAL processed by a frequency divider, the combination of the DN SIGNAL and the UP SIGNAL may represent a phase frequency difference between the clk_ref clock SIGNAL and the clk_fb clock SIGNAL, the UPB clock SIGNAL and the DNB clock SIGNAL are actual sampling SIGNALs, dn_delay is a delayed SIGNAL of the DN SIGNAL, and the LOCK SIGNAL is a LOCK SIGNAL, and the lock_signal is a final LOCK output SIGNAL.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.
The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.
Claims (3)
1. The utility model provides an adjustable delay phase-locked loop locking detection circuitry which characterized in that includes:
The phase detection module receives the reference clock signal and the feedback clock signal, detects the phase difference between the reference clock signal and the feedback clock signal and is used for detecting the locking state of the phase-locked loop;
The delay triggering module is connected with the phase detection module and is used for carrying out delay processing on the reference clock signal and the feedback clock signal and controlling the detection precision of the phase-locked loop locking detection circuit;
the phase detection module comprises a first input unit and a second input unit;
The first input unit comprises a rising edge input signal and a feedback clock signal; the feedback clock signal is used for collecting rising edge input signals;
The second input unit includes a falling edge input signal and a reference clock signal; the reference clock signal is used for collecting a falling edge input signal;
The phase detection module further comprises a plurality of inverters, a first D trigger, a second D trigger and a logic AND gate;
the rising edge input signal is connected with the input end of the phase inverter; the feedback clock signal is connected with the CLK end of the first D trigger through a plurality of inverters;
the falling edge input signal is connected with the input end of the phase inverter; the reference clock signal is connected with the CLK end of the second D flip-flop through a plurality of inverters;
the Q end of the first D trigger and the Q end of the second D trigger are connected with the input end of a logic AND gate in a decomposition mode, and the output end of the logic AND gate is connected with an output signal of the phase detection module in a locking mode;
the delay triggering module comprises a first delay module and a second delay module;
The first delay module and the second delay module comprise N cascaded third D triggers with reset functions;
The locking output signal of the phase detection module is connected with the rst end of each third D trigger, the reference clock signal is connected with the CLK end of each third D trigger, and the Qb end of the third D trigger at the last cascade position is connected with the D end of the third D trigger at the first cascade position.
2. The adjustable delay locked loop lock detection circuit of claim 1, wherein the number of inverters is six, the rising edge input signal is connected with a first inverter input terminal, and the first inverter output terminal is connected with a first delay module input terminal; the output end of the first delay module is connected with the D end of the first D trigger; the feedback clock signal is connected with the input end of a second inverter, the output end of the second inverter is connected with the input end of a third inverter, and the output end of the third inverter is connected with the CLK end of the first D trigger;
The falling edge input signal is connected with the input end of a fourth inverter, and the output end of the fourth inverter is connected with the input end of the second delay module; the output end of the second delay module is connected with the D end of the second D trigger; the reference clock signal is connected with the input end of a fifth inverter, the output end of the fifth inverter is connected with the input end of a sixth inverter, and the output end of the sixth inverter is connected with the CLK end of the second D trigger.
3. The adjustable delay locked loop lock detection circuit of claim 2, wherein the delay trigger module further comprises a fourth D flip-flop with a reset function;
the Q end of the third D trigger at the last cascade position is connected with the CLK of the fourth D trigger, and the D end of the fourth D trigger is connected with the locking output signal of the phase detection module.
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| CN202410420546.6A CN118018011B (en) | 2024-04-09 | 2024-04-09 | Locking detection circuit of adjustable delay phase-locked loop |
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| CN202410420546.6A CN118018011B (en) | 2024-04-09 | 2024-04-09 | Locking detection circuit of adjustable delay phase-locked loop |
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| US6150859A (en) * | 1998-03-02 | 2000-11-21 | Hyundai Electronics Industries Co., Ltd. | Digital delay-locked loop |
| US20040095197A1 (en) * | 2002-11-18 | 2004-05-20 | Wang David Y. | Lock detector circuit for phase locked loop |
| CN101789784A (en) * | 2009-12-15 | 2010-07-28 | 北京时代民芯科技有限公司 | Configurable phase discriminator for time-delay locking ring |
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| CN111464180A (en) * | 2020-04-09 | 2020-07-28 | 无锡中微亿芯有限公司 | Phase-locked loop circuit with locking detection function |
| CN113381753A (en) * | 2021-06-08 | 2021-09-10 | 天津大学 | Start-up circuit for delay locked loop |
-
2024
- 2024-04-09 CN CN202410420546.6A patent/CN118018011B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6150859A (en) * | 1998-03-02 | 2000-11-21 | Hyundai Electronics Industries Co., Ltd. | Digital delay-locked loop |
| US20040095197A1 (en) * | 2002-11-18 | 2004-05-20 | Wang David Y. | Lock detector circuit for phase locked loop |
| CN101789784A (en) * | 2009-12-15 | 2010-07-28 | 北京时代民芯科技有限公司 | Configurable phase discriminator for time-delay locking ring |
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| CN107562163A (en) * | 2017-08-28 | 2018-01-09 | 上海集成电路研发中心有限公司 | It is a kind of that there is the stable Digital Logical Circuits for resetting control |
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