CN113381753A - Start-up circuit for delay locked loop - Google Patents

Start-up circuit for delay locked loop Download PDF

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Publication number
CN113381753A
CN113381753A CN202110635789.8A CN202110635789A CN113381753A CN 113381753 A CN113381753 A CN 113381753A CN 202110635789 A CN202110635789 A CN 202110635789A CN 113381753 A CN113381753 A CN 113381753A
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vcdl
input
clk
output
pfd
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CN113381753B (en
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李锵
王泽清
聂凯明
高志远
徐江涛
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Tianjin University
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Tianjin University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop

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Abstract

The invention relates to the technical field of microelectronics, aims at the problem of harmonic locking of a DLL (delay locked loop), and aims to provide a starting circuit structure suitable for simulating the DLL. Therefore, the starting circuit for the delay locked loop adopts the technical scheme that the starting circuit for the delay locked loop comprises a DLL main body circuit and a DLL starting circuit; the DLL main body circuit comprises a phase frequency detector PFD, a charge pump CP (charge Pump), a low Pass filter LPF (Low Pass Filter) and a voltage-controlled delay chain VCDL; the VCDL is formed by cascading a plurality of delay units with adjustable delay, delay control ends of all the delay units are connected with an output end Vctrl of the low-pass filter, and the VCDL inputs the delay units. The invention is mainly applied to the design and manufacturing occasions of simulating the DLL.

Description

Start-up circuit for delay locked loop
Technical Field
The invention relates to the technical field of microelectronics, in particular to a delay phase-locked loop circuit and a starting circuit thereof.
Background
The development of Very Large Scale Integration (VLSI) has put higher demands on clock calibration between modules in a system. As the frequency of the clock signal increases, the total phase error of the clock increases if the jitter and skew of the clock signal remain constant. The increased phase error can severely affect the operation of the synchronization system, including the setup hold time, the read time of the data, and the accuracy of the internal control signals. To reduce clock skew, a simple fixed delay circuit may be used, but such a circuit delays different times for different Process, Voltage, and Temperature (PVT) conditions, and changes in system clock frequency may cause the delay to change. To eliminate the effect of PVT and clock frequency on Delay, a Delay Locked Loop (DLL) is often used to generate a fixed Delay clock.
Unlike a general Phase-Locked Loop (PLL), the DLL has a problem of harmonic locking. When the DLL starts to work, the DLL can be normally locked only when the Phase difference between two input signals of a Phase-Frequency Detector (PFD) is (-pi, pi), that is, a Voltage Controlled Delay Line (VCDL) of the DLL is normally locked to Delay exactly one input reference clock period. When the DLL is started, if the phase difference of two input signals of the PFD exceeds (-pi, pi), the delay of the VCDL is n (n >1) times of the reference clock period after the DLL enters a locked state. This phenomenon indicates that the DLL has harmonic locking. When the DLL is in harmonic locking, the delay of the VCDL is no longer one cycle of the reference clock signal, which can cause that each module in the system can not work normally, thereby causing the system to malfunction, so measures are taken to prevent the DLL from being in harmonic locking. In the prior art, one method is to design a start circuit of a DLL by using an exponential-to-Analog converter (DAC) and a Low Dropout Regulator (LDO), which has the advantage of a large range of preventing harmonic locking, but the start circuit is complicated in design because of using modules such as the DAC and the LDO. There is also a method of designing a DLL start circuit with a simple structure using D flip-flops, nand gates and not gates, but the DLL has a long time from start to correct lock.
Disclosure of Invention
Aiming at overcoming the defects of the prior art and aiming at the problem of harmonic locking of the DLL, the invention aims to provide a starting circuit structure suitable for simulating the DLL. The starting circuit provided by the invention is added into the DLL, so that the DLL can be prevented from being locked in a harmonic mode, and the DLL can be quickly enabled to enter a correct locking state. Therefore, the starting circuit for the delay locked loop adopts the technical scheme that the starting circuit for the delay locked loop comprises a DLL main body circuit and a DLL starting circuit; the DLL main body circuit comprises a phase frequency detector PFD, a charge pump CP (charge Pump), a low Pass filter LPF (Low Pass Filter) and a voltage-controlled delay chain VCDL; the VCDL is formed by cascading a plurality of delay units with adjustable delay, delay control ends of all the delay units are connected with an output end Vctrl of the low-pass filter, the input of the VCDL, namely the input of the first delay unit, is a reference clock signal clk _ ref, the output clk _ VCDL of the last delay unit is connected to one input end of the PFD, the other input end of the PFD is also the reference clock signal clk _ ref, and two output ends up and dn of the PFD are respectively connected with input ends up and dn corresponding to the charge pump; the output signal of the charge pump enters a second-order low-pass filter and is connected with a capacitor C2The upper level boards are connected; the second-order low-pass filter is composed of a resistor RPCapacitor CPAnd a capacitor C2Wherein R isPAnd CPIn series, RPHas an input terminal of Vctrl, an output terminal and CPUpper board connection of CPLower level plate of (C) is grounded2Is connected in parallel to RPAnd CPAt both ends, i.e. C2The upper plate of the transformer is Vctrl, and the lower plate is grounded; the output voltage Vctrl of the low-pass filter is connected with a delay control end of a delay unit in the VCDL;
the DLL starting circuit is arranged in front of the PFD in one part and the VCDL in the other part, and the structure of the part arranged in front of the PFD is as follows: the reference clock signal clk _ ref is connected to the 0 input of the 1-out-of-2 data selector MUX (multiplexer), the 1 input of the MUX is connected to the select input S of the MUX and grounded, the output of the MUX is connected to one input of the two-input nand gate after passing through an inverter, for two cascaded D flip-flops, the reset terminals Rst of the two D flip-flops are connected with a reset signal reset, the D input terminal of the first-stage D flip-flop is connected with a high level, the Q output terminal is used as the D input terminal of the second-stage D flip-flop, the output of the second-stage D flip-flop is used as the other input of the NAND gate, the output of the NAND gate enters the PFD from the IN1 end after passing through an inverter, the output clk _ VCDL and reset of VCDL are input into another two-input NAND gate, the output of the NAND gate is connected with the Clk ends of the two D flip-flops on one hand, and is connected with the IN2 end of the PFD after passing through an inverter on the other hand;
the structure of the front part of the VCDL is that the source of a p-Channel Metal Oxide semiconductor (PMOS) transistor is connected with a power supply, the drain of the transistor is connected with the Vctrl, a grid signal is reset, the reset is also an input selection signal of a 1-out-of-2 MUX1, the 0 input end of the MUX1 is grounded, the 1 input end is connected with clk _ ref, and the output of the MUX1 enters the VCDL from clkin after passing through an inverter.
Timing of the start-up circuit: at the beginning, the reset signal reset is low level, the Q output ends of the first stage D flip-flop and the second stage D flip-flop are reset to low level, the two NAND gates are closed, and the reference clock clk _ ref and the output signal clk _ vcdl of the voltage-controlled delay line cannot enter the PFD through the NAND gates; at the same time, the PMOS switch placed in the front of VCDL is turned on, the low pass filter is charged to the power voltage, the low level reset makes the 1-out-of-2 MUX1 gate the 0 input end, i.e. the inverter behind MUX1 inputs high level into VCDL, after the reset becomes high level, the PMOS switch is turned off, the high level reset makes MUX1 gate the 1 input end, then clk _ ref can be input into VCDL, at the same time, the first stage D flip-flop and the second stage D flip-flop stop resetting, clk _ VCDL enters PFD through nand gate, after two falling edges of clk _ VCDL pass through nand gate, the second stage D flip-flop makes the rsto signal become high level, then clk _ ref enters PFD through nand gate, because clk _ VCDL enters PFD first than clk _ ref, the output dn signal of PFD becomes higher than up, DLL lets the loop filter discharge to make the rising edges of clk _ vref align, gradually approach Vctrl at the correct lock timing, this prevents harmonic locking of the DLL.
The invention has the characteristics and beneficial effects that:
the DLL to which the start-up circuit is added can prevent the DLL from harmonic locking so that the DLL can be correctly locked. Meanwhile, the inverter switches a constant high level into the VCDL during the reset signal is at a low level. Thus, the VCDL can enter an operating state faster than if the clock signal was always switched into the VCDL, reducing the time for the DLL to lock from start-up.
Description of the drawings:
fig. 1 shows a basic circuit structure of a DLL.
Fig. 2 is a schematic diagram of the start-up circuit of the front part of the PFD.
Fig. 3 is a schematic diagram of the start-up circuit of the front part of the VCDL.
Fig. 4 is a timing diagram of the start-up circuit.
Fig. 5 is a complete block diagram of the DLL.
Detailed Description
The implementation mode of the invention is as follows:
(1) the first part is the design of the DLL body circuit. As shown in fig. 1, the core circuit of the DLL includes four parts, namely, a phase frequency detector PFD, a Charge Pump (CP), a Low Pass Filter (LPF), and a voltage controlled delay chain VCDL. The voltage-controlled delay chain is formed by connecting a plurality of delay units with adjustable delay in series, and delay control ends of all the delay units are connected with an output end Vctrl of the low-pass filter. The input of the VCDL, i.e. the input of the first delay unit, is the reference clock signal clk _ ref, and the output clk _ VCDL of the last delay unit is connected to one input of the PFD. The other input of the PFD is also the reference clock signal clk _ ref. The output terminals up and dn of the PFD are respectively connected with the corresponding input terminals up and dn of the charge pump. The output signal of the charge pump enters a second-order low-pass filter and is connected with a capacitor C2Is connected. The second-order low-pass filter is composed of a resistor RPCapacitor CPAnd a capacitor C2Wherein R isPAnd CPIn series, RPHas an input terminal of Vctrl, an output terminal and CPUpper board connection of CPThe lower plate of (2) is grounded. C2Is connected in parallel to RPAnd CPAt both ends, i.e. C2The upper board of (2) is Vctrl, and the lower board is grounded. Input of low-pass filterThe output voltage Vctrl is connected with a delay control end of a delay unit in the VCDL.
The basic operating principle of a DLL is that the PFD discriminates the phase difference of the two input signals clk _ ref and clk _ vcdl. When the phase of clk _ ref leads clk _ vcdl, the output up of the PFD first goes high, when the phase of clk _ vcdl leads clk _ ref, the dn of the PFD first outputs high, and when clk _ ref and clk _ vcdl are both high, both up and dn are reset low. For the charge pump and the low-pass filter, when up is high level and dn is low level, the charge pump charges the low-pass filter, the output voltage Vctrl of the filter rises, and when up is low level and dn is high level, the charge pump discharges the low-pass filter, and Vctrl falls. A raised Vctrl can reduce the delay of the voltage controlled delay line and a lowered Vctrl can increase the delay of the voltage controlled delay line. The DLL gradually adjusts the delay of the voltage controlled delay line by using a feedback mechanism, and enters a locked state when the rising edge of the output signal of the voltage controlled delay line is aligned with the rising edge of the input reference clock.
(2) The second part is the design of the DLL start circuit. Detailed schematic diagram of the start-up circuit as shown in fig. 2 and 3, a portion of the start-up circuit is placed before the PFD and another portion of the start-up circuit is placed before the VCDL. In fig. 2, the reference clock signal clk _ ref is coupled to the 0 input of the 1-out-of-2 MUX. The 1 input of the MUX and the select input S of the MUX are connected and grounded. The output of the MUX is connected with one input end of the two-input NAND gate after passing through one inverter. For two cascaded D flip-flops, the reset terminals Rst of both D flip-flops are connected to the reset signal reset. The D input end of the first-stage D trigger is connected with a high level, and the Q output end of the first-stage D trigger is used as the D input end of the second-stage D trigger. The output of the second stage D flip-flop is used as the other input of the NAND gate. The output of the nand gate goes through an inverter and enters the PFD from the IN1 terminal. The outputs Clk _ VCDL and reset of VCDL are input into another two-input NAND gate, the output of which is connected with the Clk ends of two D flip-flops on one hand and is connected with the IN2 end of PFD after passing through an inverter on the other hand. In fig. 3, the source of the PMOS transistor is connected to the power supply, the drain is connected to Vctrl, and the gate signal is reset. At the same time, reset is also the input select signal to the 1-out-of-2 MUX 1. The 0 input of MUX1 is connected to ground and the 1 input is connected to clk _ ref. The output of MUX1 goes from clkin to VCDL through an inverter.
Fig. 4 is a timing diagram of the start-up circuit, when the reset signal reset is low at the beginning, the Q output of the D flip-flop in fig. 2 is reset to low, the two nand gates are closed, and the reference clock clk _ ref and the output signal clk _ vcdl of the voltage-controlled delay line cannot enter the PFD through the nand gates. At the same time, the PMOS switch in fig. 3 is open and the low pass filter is charged to the supply voltage. The low reset causes the 1-out-of-2 MUX1 to gate the 0 input, i.e., the inverter after MUX1 inputs a high into the VCDL. After reset goes high, the PMOS switch is turned off. A high reset causes MUX1 to gate the 1 input so clk ref can be input into the VCDL. In fig. 2, the D flip-flop stops being reset, and clk _ vcdl may enter the PFD through the nand gate. When the two falling edges of clk _ vcdl pass through the nand gate, the D flip-flop makes the rsto signal high, and clk _ ref can then pass through the nand gate into the PFD. Since clk _ vcdl enters the PFD earlier than clk _ ref, the dn signal goes high earlier than up. The DLL, in order to align the rising edges of ro and vo, will discharge the loop filter, gradually approaching Vctrl when the DLL is properly locked, which prevents the DLL from harmonic locking. The complete circuit structure of the DLL is shown in fig. 5.
The present invention will be described in further detail with reference to the accompanying drawings and specific examples.
As shown in fig. 1, in order to avoid the mismatch of the PFD from causing ripples on the subsequent circuit, the PFD needs to ensure that the devices on the two branches up and dn are highly symmetrical. The output terminals up and dn of the PFD are connected to the input terminals up and dn of the charge pump, respectively. Thus, the charge pump can select whether to charge or discharge the LPF according to the phase relation of two input signals of the PFD. The output end Vctrl of the LPF is connected with a bias end for controlling the time delay of the time delay unit in the VCDL. Thus, the delay of the delay unit can be changed along with the change of the output voltage of the LPF. When the Vctrl is increased, the delay of the delay unit is reduced, and when the Vctrl is reduced, the delay of the delay unit is increased. Because the Vctrl is long in trace and sensitive to noise in an actual circuit, the length of the Vctrl is reduced as much as possible and noise shielding is performed in design. The load of the last stage delay unit in the VCDL is different from the load of the preceding stage, and different loads can cause a large difference between output signals of the delay units. The design of adding virtual load can be adopted, namely, a delay unit is added after the delay unit of the last stage to serve as a virtual delay unit, so that the difference of signals among the delay units is reduced.
The start-up circuit is constructed as shown in fig. 2 and 3, and the reset signal reset controls the reset of the D flip-flop, the switching of the nand gate, the switching of the PMOS, and the gating of the MUX 1. The two D triggers are connected in a cascade mode, and the output of the first-stage D trigger is used as the input of the second-stage D trigger. The output of the second stage D flip-flop is connected with the NAND gate. When in design, the MUX through which the reference clock signal clk _ ref passes needs to be set to be in a normally open state, and an inverter is connected behind the MUX in series. The output clk rb of the inverter is connected to the other input of the nand gate. The output signal clk1 of the nand gate goes from IN1 to the PFD through an inverter. The output signal clk _ VCDL of the VCDL passes through another nand gate and an inverter and is connected to the IN2 terminal of the PFD. The load of the clk node is two D flip-flops more than the load of the clk1 node, and in order to ensure the symmetry of clk _ ref and clk _ vcdl into the PFD path, a dummy load of appropriate size should be added at clk 1. In fig. 3, clk _ ref is coupled to the VCDL through a MUX1 and inverter. The MUX and inverter are added to the clk _ ref path in fig. 2 because of the presence of one MUX1 and one inverter in the input clock path of the VCDL in fig. 3. This counteracts the delay caused by the MUX1 and the inverter in fig. 3.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims (2)

1. A starting circuit for a delay locked loop is characterized by comprising a DLL main circuit and a DLL starting circuit; the DLL main body circuit comprises a phase frequency detector PFD, a charge pump CP (charge Pump), a low Pass filter LPF (Low Pass Filter) and a voltage-controlled delay chain VCDL; the VCDL is composed of multiple delay unit stages with adjustable delayThe delay control ends of all delay units are connected with the output end Vctrl of the low-pass filter, the input of VCDL, namely the input of the first delay unit, is a reference clock signal clk _ ref, the output clk _ VCDL of the last delay unit is connected to one input end of the PFD, the other input end of the PFD is also the reference clock signal clk _ ref, and two output ends up and dn of the PFD are respectively connected with the corresponding input ends up and dn of the charge pump; the output signal of the charge pump enters a second-order low-pass filter and is connected with a capacitor C2The upper level boards are connected; the second-order low-pass filter is composed of a resistor RPCapacitor CPAnd a capacitor C2Wherein R isPAnd CPIn series, RPHas an input terminal of Vctrl, an output terminal and CPUpper board connection of CPLower level plate of (C) is grounded2Is connected in parallel to RPAnd CPAt both ends, i.e. C2The upper plate of the transformer is Vctrl, and the lower plate is grounded; the output voltage Vctrl of the low-pass filter is connected with a delay control end of a delay unit in the VCDL;
the DLL starting circuit is arranged in front of the PFD in one part and the VCDL in the other part, and the structure of the part arranged in front of the PFD is as follows: the reference clock signal clk _ ref is connected to the 0 input of the 1-out-of-2 data selector MUX (multiplexer), the 1 input of the MUX is connected to the select input S of the MUX and grounded, the output of the MUX is connected to one input of the two-input nand gate after passing through an inverter, for two cascaded D flip-flops, the reset terminals Rst of the two D flip-flops are connected with a reset signal reset, the D input terminal of the first-stage D flip-flop is connected with a high level, the Q output terminal is used as the D input terminal of the second-stage D flip-flop, the output of the second-stage D flip-flop is used as the other input of the NAND gate, the output of the NAND gate enters the PFD from the IN1 end after passing through an inverter, the output clk _ VCDL and reset of VCDL are input into another two-input NAND gate, the output of the NAND gate is connected with the Clk ends of the two D flip-flops on one hand, and is connected with the IN2 end of the PFD after passing through an inverter on the other hand;
the structure of the front part of the VCDL is that the source of a p-Channel Metal Oxide semiconductor (PMOS) transistor is connected with a power supply, the drain of the transistor is connected with the Vctrl, a grid signal is reset, the reset is also an input selection signal of a 1-out-of-2 MUX1, the 0 input end of the MUX1 is grounded, the 1 input end is connected with clk _ ref, and the output of the MUX1 enters the VCDL from clkin after passing through an inverter.
2. The startup circuit for a delay locked loop according to claim 1, wherein the timing of the startup circuit: at the beginning, the reset signal reset is low level, the Q output ends of the first stage D flip-flop and the second stage D flip-flop are reset to low level, the two NAND gates are closed, and the reference clock clk _ ref and the output signal clk _ vcdl of the voltage-controlled delay line cannot enter the PFD through the NAND gates; at the same time, the PMOS switch placed in the front of VCDL is turned on, the low pass filter is charged to the power voltage, the low level reset makes the 1-out-of-2 MUX1 gate the 0 input end, i.e. the inverter behind MUX1 inputs high level into VCDL, after the reset becomes high level, the PMOS switch is turned off, the high level reset makes MUX1 gate the 1 input end, then clk _ ref can be input into VCDL, at the same time, the first stage D flip-flop and the second stage D flip-flop stop resetting, clk _ VCDL enters PFD through nand gate, after two falling edges of clk _ VCDL pass through nand gate, the second stage D flip-flop makes the rsto signal become high level, then clk _ ref enters PFD through nand gate, because clk _ VCDL enters PFD first than clk _ ref, the output dn signal of PFD becomes higher than up, DLL lets the loop filter discharge to make the rising edges of clk _ vref align, gradually approach Vctrl at the correct lock timing, this prevents harmonic locking of the DLL.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118018011A (en) * 2024-04-09 2024-05-10 西安航天民芯科技有限公司 Locking detection circuit of adjustable delay phase-locked loop

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Publication number Priority date Publication date Assignee Title
EP1835623A1 (en) * 2006-03-13 2007-09-19 Renesas Technology Corp. Delay locked loop circuit and semiconductor integrated circuit device
CN103001628A (en) * 2012-11-30 2013-03-27 清华大学深圳研究生院 Phase detection and starting circuit used in multiphase clock generating circuit of high-speed serial interface
CN103312317A (en) * 2013-06-14 2013-09-18 电子科技大学 Delay phase-lock loop capable of being locked quickly
CN105071799A (en) * 2015-08-21 2015-11-18 东南大学 Delay-locked loop adopting novel error lock detection circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1835623A1 (en) * 2006-03-13 2007-09-19 Renesas Technology Corp. Delay locked loop circuit and semiconductor integrated circuit device
CN103001628A (en) * 2012-11-30 2013-03-27 清华大学深圳研究生院 Phase detection and starting circuit used in multiphase clock generating circuit of high-speed serial interface
CN103312317A (en) * 2013-06-14 2013-09-18 电子科技大学 Delay phase-lock loop capable of being locked quickly
CN105071799A (en) * 2015-08-21 2015-11-18 东南大学 Delay-locked loop adopting novel error lock detection circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118018011A (en) * 2024-04-09 2024-05-10 西安航天民芯科技有限公司 Locking detection circuit of adjustable delay phase-locked loop

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