CN113922817A

CN113922817A - Pulse generator and clock frequency multiplier

Info

Publication number: CN113922817A
Application number: CN202010650389.XA
Authority: CN
Inventors: 郑旭强; 辛可为; 吴旦昱; 周磊; 武锦; 刘新宇
Original assignee: Institute of Microelectronics of CAS
Current assignee: Institute of Microelectronics of CAS
Priority date: 2020-07-08
Filing date: 2020-07-08
Publication date: 2022-01-11

Abstract

The application discloses pulse generator and clock multiplier, wherein, pulse generator includes: the delay circuit comprises a first AND gate, an adjustable delay unit group and a second AND gate; the output end of the first AND gate is connected with the input end of the adjustable delay unit group, and the output end of the adjustable delay unit group is connected with the input end of the second AND gate; the first AND gate, the adjustable delay unit group and the second AND gate are also connected with a power supply voltage; the input end of the adjustable delay unit group is also connected with the output end of the filter. The pulse generated by the pulse generator can adaptively adjust the pulse width at different PVT corners and keep a fixed proportion all the time, so that a clock frequency multiplication signal generated by the annular voltage-controlled oscillator is improved.

Description

Pulse generator and clock frequency multiplier

Technical Field

The application relates to the technical field of pulse generators, in particular to a pulse generator and a clock frequency multiplier.

Background

Clock multipliers continue to play an important role in modern wired communication systems. With the rapid increase of data rate per line and the integration of large-capacity interfaces, higher requirements are put on the clock multiplier, including high running speed, low jitter, small area occupation and low power consumption. Thanks to the development of Injection locking technology, Ring-Oscillator-based Pulse Injection-Locked Clock multipliers (RPILCMs) have become one of the most promising solutions for generating low-jitter clocks, and have greater advantages in terms of area occupation and power consumption. Its high power efficiency, compact circuit implementation and high robustness further make it particularly advantageous in the design of clock multipliers, clock recovery circuits and frequency synchronizers.

The main challenge of RPILCM is how to bring the free running frequency of the oscillator very close to the target frequency within the process, voltage and temperature (PVT) variation, thereby maintaining lock-in and achieving excellent spurs and phase noise performance. This frequency deviation is particularly important when the multiplication factor increases with the associated cumulative phase shift over one injection period as the multiplication factor increases linearly.

Another problem associated with RPILCM is how to select the pulse width and its effect of variation at different PVT angles. The frequency tracking problem has attracted a great deal of research interest, and although they all have some disadvantages, a number of techniques have been developed. Unlike the frequency tracking problem, pulse width modulation is an underscore problem and has not been of sufficient research interest in the past. However, the value of the pulse width and its variation can significantly affect the tracking bandwidth of a pulse Injection-Locked Oscillator (PILO).

In view of the foregoing, it is desirable to provide a pulse generator and a clock multiplier capable of adjusting the pulse width such that the pulse width and the injection period form a fixed ratio, thereby improving the performance of the tracking bandwidth of the pulse injection locked oscillator.

Disclosure of Invention

To solve the above problems, the present application proposes a pulse generator and a clock multiplier.

In one aspect, the present application provides a pulse generator comprising: the delay circuit comprises a first AND gate, an adjustable delay unit group and a second AND gate;

the output end of the first AND gate is connected with the input end of the adjustable delay unit group, and the output end of the adjustable delay unit group is connected with the input end of the second AND gate;

the first AND gate, the adjustable delay unit group and the second AND gate are also connected with a power supply voltage;

the input end of the adjustable delay unit group is also connected with the output end of the filter.

Preferably, the adjustable delay unit group includes: the circuit comprises a NOT gate, a transmission gate, three adjustable delay units and three transistors;

the three adjustable delay units comprise a first adjustable delay unit, a second adjustable delay unit and a third adjustable delay unit, wherein the positive input end of the first adjustable delay unit is connected with the output end of the NOT gate, the reverse input end of the first adjustable delay unit is connected with the output end of the transmission gate, the first adjustable delay unit, the second adjustable delay unit and the third adjustable delay unit are sequentially connected in series, the positive input end of each adjustable delay unit is connected with a corresponding grid electrode of the transistor, and the reverse output end of each adjustable delay unit is connected with the source electrode of the same transistor.

In a second aspect, the present application provides a clock multiplier, comprising: the pulse injection locking oscillation module and the tracking module are connected with each other;

the pulse injection locked oscillation module includes: a pulse generator and a ring voltage controlled oscillator as described above connected in series;

the tracking module includes: the system comprises a loop selection state machine, a phase measurement unit, a frequency and phase discrimination unit, a multiplexer and a filter; the input end of the multi-path selector is respectively connected with the output ends of the loop selection state machine, the phase measurement unit and the phase frequency and phase discrimination unit, and the output end of the multi-path selector is connected with the input end of the filter; the output end of the filter is connected with the pulse generator and the input end of the annular voltage-controlled oscillator; the input ends of the loop selection state machine, the phase measurement unit and the phase frequency and phase discrimination unit are all connected with the output end of the annular voltage-controlled oscillator; the input ends of the loop selection state machine and the phase frequency and phase detection unit are also connected with a reference input signal, and the input end of the phase detection unit is also connected with the output end of the pulse generator.

Preferably, the phase measurement unit includes: the phase measurer and the first charge pump are connected in sequence;

the phase measurer comprises a plurality of first transistors and a second transistor, wherein the first transistors are used for comparing the phases of a reference input signal and a pulse generated by the pulse injection locking oscillation module, generating a phase output signal and sending the phase output signal to the first charge pump;

the first charge pump includes a plurality of second transistors and a comparator for converting the phase output signal into a current.

Preferably, the phase measurement unit further comprises a polarity detector connected to the first charge pump.

Preferably, the phase frequency detecting unit includes: the frequency divider, the phase frequency detector and the second charge pump are connected in sequence;

the frequency divider is used for dividing the frequency of the clock frequency multiplication signal output by the pulse injection locking oscillation module to obtain the frequency-divided clock frequency multiplication signal and sending the frequency-divided clock frequency multiplication signal to the phase frequency detector;

the phase frequency detector is used for comparing the frequency and the phase of the frequency-divided clock frequency-multiplication signal and the reference input signal, determining an error signal and sending the error signal to the second charge pump;

and the second charge pump is used for converting the error signal into current and sending the current to the multiplexer.

Preferably, the loop selection state machine includes: a frequency lock detector and a loop selector;

the frequency lock detector includes: two D flip-flops and a first XOR gate; the output ends of the two D triggers are respectively connected with the two input ends of the first exclusive-OR gate;

the loop selector includes: a second exclusive or gate, an edge counter and a timer; the output end of the second exclusive-or gate is connected with the input end of the edge counter, and the output end of the timer is connected with the input end of the edge counter.

Preferably, the pulse generator generates a pulse according to a reference input signal, a power supply voltage and a control voltage generated by the tracking module;

the annular voltage-controlled oscillator generates a clock frequency multiplication signal according to the power supply voltage; or generating a clock frequency multiplication signal according to the power supply voltage and the control voltage; or generating a clock frequency multiplication signal according to the power supply voltage, the pulse and the control voltage.

Preferably, the tracking module includes two loops, one of the two loops is a phase-locked loop, and the other loop is a timing adjustment loop;

the loop selection state machine selects one of the two loops according to the frequency of the reference input signal, the frequency of a clock frequency doubling signal generated by the annular voltage-controlled oscillator and the currently running loop, generates a loop control signal and sends the loop control signal to the multiplexer;

the phase measurement unit determines a first current according to the pulse and the clock frequency multiplication signal and sends the first current to the multiplexer;

the frequency and phase discrimination unit determines a second current according to the reference input signal and the clock frequency multiplication signal and sends the second current to the multiplexer;

the multiplexer starts the timing adjusting loop according to the loop control signal, outputs the first current or starts the phase-locked loop, and outputs the second current;

the filter filters the first current or the second current to obtain a control voltage, and the control voltage is sent to the pulse injection locking oscillation module.

The application has the advantages that: the pulse width of the pulse generated by the pulse generator can be adaptively adjusted at different PVT corners, and a fixed proportion is always kept, so that the clock frequency multiplication signal generated by the annular voltage-controlled oscillator is improved.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating preferred embodiments and are not to be construed as limiting the application. Also, like reference numerals are used to denote like parts throughout the drawings. In the drawings:

FIG. 1 is a schematic circuit diagram of a pulse generator provided herein;

FIG. 2 is a schematic circuit diagram of an adjustable delay cell group in a pulse generator provided herein;

FIG. 3 is a schematic diagram of a clock multiplier provided herein;

FIG. 4 is a detailed schematic diagram of a clock multiplier provided herein;

FIG. 5 is a schematic circuit diagram of a ring-shaped voltage controlled oscillator of a clock multiplier provided herein;

FIG. 6 is a circuit schematic of a conventional pulse generator;

FIG. 7 is a schematic circuit diagram of a delay unit in a ring-shaped voltage-controlled oscillator of a clock multiplier according to the present application;

FIG. 8 is a schematic circuit diagram of a phase measurement unit of a clock multiplier according to the present application;

FIG. 9 is an equivalent logic diagram of a phase measurer of a clock multiplier provided in the present application;

FIG. 10 is a schematic diagram of the equivalent logic and polarity selection of a phase measurer for a clock multiplier according to the present application;

FIG. 11 is a schematic diagram of a polarity detector of a clock multiplier provided herein;

FIG. 12(a) is a schematic diagram of a lock condition of a clock multiplier provided herein;

FIG. 12(b) is a schematic diagram of another lock condition for a clock multiplier provided herein;

FIG. 13 is a circuit schematic of a loop selection state machine of a clock multiplier as provided herein;

FIG. 14(a) is a signal level diagram of target harmonic locking for frequency tracking of a clock multiplier as provided herein;

FIG. 14(b) is a signal level diagram of the harmonic loss of lock of frequency tracking of a clock multiplier provided herein;

FIG. 14(c) signal level diagram of conventional frequency deviation;

fig. 15 is a schematic circuit diagram of a filter of a clock multiplier according to the present application.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

According to an embodiment of the present application, there is provided a pulse generator, as shown in fig. 1, including: a first and gate G1, an adjustable delay cell group RDCs and a second and gate G2. The output end of the first AND gate is connected with the input end of the adjustable delay unit group, the output end of the adjustable delay unit group is connected with the input end of the second AND gate, the first AND gate, the adjustable delay unit group and the second AND gate are further connected with a power supply voltage, and the input end of the adjustable delay unit group is further connected with the output end of the filter.

As shown in fig. 2, the adjustable delay unit group includes: the circuit comprises a NOT gate, a transmission gate, three adjustable delay units and three transistors. The three adjustable delay units comprise a first adjustable delay unit RDC1, a second adjustable delay unit RDC2 and a third adjustable delay unit RDC3, wherein a positive input end of the first adjustable delay unit is connected with an output end of the NOT gate, an inverted input end of the first adjustable delay unit is connected with an output end of the transmission gate, the first adjustable delay unit, the second adjustable delay unit and the third adjustable delay unit are sequentially connected in series, a positive input end of each adjustable delay unit is connected with a grid electrode of a corresponding transistor, and an inverted output end of each adjustable delay unit is connected with a source electrode of the same transistor.

According to an embodiment of the present application, there is also provided a clock multiplier, as shown in fig. 3, including: a pulse injection locked oscillation module 101 and a tracking module 102 connected to each other.

As shown in fig. 4, the pulse injection locked oscillation module includes: a Pulse Generator (Pulse Generator) and a Ring Voltage Controlled Oscillator (RVCO) proposed in the present embodiment connected in series;

A phase measurement unit comprising: the phase measurer and the first charge pump are connected in sequence.

And the phase measurer comprises a plurality of first transistors and is used for comparing the phases of the reference input signal and the pulse generated by the pulse injection locking oscillation module, generating a phase output signal and sending the phase output signal to the first charge pump.

A first charge pump including a plurality of second transistors and a comparator for converting the phase output signal into a current.

The phase measurement unit further includes a Polarity Detector (Polarity Detector) connected to the first charge pump.

The phase frequency detection unit includes: the frequency divider, the phase frequency detector and the second charge pump are connected in sequence.

And the frequency divider is used for dividing the frequency of the clock frequency multiplication signal output by the pulse injection locking oscillation module to obtain the frequency-divided clock frequency multiplication signal and sending the frequency-divided clock frequency multiplication signal to the phase frequency detector.

And the phase frequency detector is used for comparing the frequency and the phase of the frequency-divided clock frequency-multiplication signal and the reference input signal, determining an error signal and sending the error signal to the second charge pump.

A loop selection state machine comprising: a frequency lock detector and a loop selector.

The frequency lock detector includes: two D flip-flops and a first XOR gate; the output ends of the two D flip-flops are respectively connected with the two input ends of the first exclusive-OR gate.

And a Pulse generator for generating a Pulse (Pulse) based on the reference input signal, the power supply voltage and the control voltage generated by the tracking module.

The annular voltage-controlled oscillator can directly generate a clock frequency multiplication signal according to the power supply voltage. Generating a clock frequency multiplication signal according to a power supply voltage and a control voltage; or generating a clock frequency doubling signal according to the power supply voltage, the pulse and the control voltage, and adjusting and outputting the generated clock frequency doubling signal according to the power supply voltage and the control voltage or according to the power supply voltage, the control voltage and the pulse.

The tracking module comprises two loops, wherein one loop is a phase-locked loop, and the other loop is a timing adjusting loop.

And the loop selection state machine selects one of the two loops according to the frequency of the reference input signal, the frequency of the clock frequency doubling signal generated by the annular voltage-controlled oscillator and the currently running loop, generates a loop control signal and sends the loop control signal to the multiplexer.

The phase measurement unit determines a first current according to the pulse and the clock frequency multiplication signal and sends the first current to the multiplexer.

And the frequency and phase discrimination unit determines a second current according to the reference input signal and the clock frequency multiplication signal and sends the second current to the multiplexer.

The multiplexer starts a timing adjusting loop according to the loop control signal and outputs a first current or starts a phase-locked loop and outputs a second current.

And the pulse generator is started along with the starting of the timing adjusting loop and is closed along with the starting of the phase-locked loop.

And the frequency locking detector is used for comparing the frequency of the reference input signal with the frequency of the clock frequency doubling signal, determining whether the frequency deviation times exceed a threshold value, and if so, sending a first control signal to the loop selector.

And the loop selector is used for determining a loop control signal according to the first control signal, sending the loop control signal to the multiplexer, starting the timer, and generating a second control signal serving as the loop control signal to be sent to the multiplexer if the timer runs to reach a time threshold.

The phase output signal is an error signal obtained by comparing the reference input signal with the phase of the pulse.

The first control signal is used for starting the phase-locked loop, and the second control signal is used for starting the timing adjustment loop.

Next, examples of the present application will be further described, as shown in fig. 4.

The pulse injection locked oscillation module includes: a ring voltage controlled oscillator and a pulse generator. The tracking module is a mixed frequency tracking loop and comprises two loops, one loop is a timing adjustment loop passing through a phase measurement unit, a multiplexer and a filter, and the other loop is a phase-locked loop passing through a phase frequency and phase discrimination unit, the multiplexer and the filter. The phase frequency and phase detecting unit works intermittently, and the pulse generator works along with the work of the phase measuring unit.

The control voltage is used for controlling the annular voltage-controlled oscillator and the pulse generator to perform pulse width adjustment and frequency adjustment, so that the width of the pulse and the oscillation period are kept in a proper proportion. The control voltages of the ring voltage controlled oscillator and the pulse generator are adaptively adjusted by the tracking module so that the free running frequency of the ring voltage controlled oscillator tracks the target output frequency and the pulse width of the injection signal (injected pulse) is close to a certain proportion of the oscillation period.

When the device is powered on, the pulse generator and the phase measurement unit do not work, and the annular voltage-controlled oscillator directly generates a clock frequency multiplication signal according to the power supply voltage. Because the frequency difference between the frequency of the reference input signal (Fref) and the frequency of the clock frequency multiplication signal (Fout) is overlarge, the loop selection state machine controls the multi-path selector to open the phase-locked loop according to the frequency difference between the frequency of the reference input signal and the frequency of the clock frequency multiplication signal, at the moment, the frequency and phase discrimination unit works, and the timer starts to time. And the frequency and phase discrimination unit determines a second current according to the reference input signal and the clock frequency multiplication signal and sends the second current to the multiplexer. And the second current passes through the multiplexer, is filtered by the filter to obtain a control voltage, and is input to the annular voltage-controlled oscillator. And the annular voltage-controlled oscillator generates a clock frequency multiplication signal according to the control voltage and the power supply voltage. When the working time of the phase frequency and phase detection unit reaches a time threshold, the loop selection state machine controls the multiplexer to open the timing adjustment loop. The pulse generator generates pulses according to the reference input signal, the power supply voltage and the control voltage, and sends the pulses to the phase measurer and the annular voltage-controlled oscillator. The annular voltage-controlled oscillator generates a clock frequency multiplication signal according to the pulse, the control voltage and the power supply voltage. The phase measurer determines a first current according to the pulse and the clock frequency multiplication signal, and inputs the first current to the filter through the multiplexer. The filter filters the first current to obtain a control voltage, the control voltage is input to the pulse generator and the annular voltage-controlled oscillator, and the annular voltage-controlled oscillator generates a clock frequency multiplication signal according to the pulse, the power supply voltage and the control voltage. And the loop selection state machine determines a loop to be operated according to the frequency of the reference input signal and the clock frequency multiplication signal, the frequency of the clock frequency multiplication signal and the currently operated loop, generates a loop control signal and sends the loop control signal to the multiplexer. If the frequency deviation times of the reference input signal and the clock frequency doubling signal do not exceed the threshold value, continuously controlling the multi-path selector to enable the timing adjustment loop to be conducted; if the frequency deviation times of the reference input signal and the clock frequency doubling signal exceed a threshold value, the multi-channel selector is controlled to conduct the phase-locked loop, and meanwhile, the frequency and phase discrimination unit operates, and the timer starts to time.

As shown in fig. 1, the two input terminals of the first and gate G1 of the pulse generator respectively input the reference input signal and the enable signal, and meanwhile, the power supply voltage is also connected. The output end of the first and gate G1 is connected to the adjustable delay cell group RDCs, and the adjustable delay cell group RDCs also inputs the control voltage and the power supply voltage. Two output signals of the adjustable delay cell group RDCs are respectively connected with the input end and the inverted input end of the second and gate G2, and output a pulse INJ.

Fig. 2 is a schematic circuit diagram of an adjustable delay unit group in a pulse generator according to an embodiment of the present application. Wherein, adjustable delay unit group includes: the circuit comprises a NOT gate, a transmission gate, three adjustable delay units and three transistors. The signal is divided into two paths, and the two paths of signals are input to the input end of the first adjustable delay unit RDC1 after passing through a not gate and a transmission gate respectively, wherein the output end of the not gate is connected with the positive input end of the first adjustable delay unit RDC1, and the output end of the transmission gate is connected with the reverse input end of the adjustable delay unit RDC 1. The input end of each adjustable delay unit is connected with a transistor, specifically, the positive input end of the first adjustable delay unit RDC1 is connected with the gate of the transistor T31, the inverting input end of the first adjustable delay unit RDC1 is connected with the source of the transistor T31, and the gate stages of the transistors T31, T32 and T33 are all grounded. An inverting output terminal of first adjustable delay cell RDC1 is connected to a positive input terminal of second adjustable delay cell RDC2 and to a gate of transistor T32, and a positive output terminal of first adjustable delay cell RDC1 is connected to an inverting input terminal of second adjustable delay cell RDC2 and to a source of transistor T32. An inverting output terminal of second adjustable delay unit RDC2 is connected to a positive input terminal of third adjustable delay unit RDC3 and to a gate of transistor T33, and a positive output terminal of second adjustable delay unit RDC2 is connected to an inverting input terminal of third adjustable delay unit RDC3 and to a source of transistor T33. Each adjustable delay unit also inputs a supply voltage. One positive output BP1 of the first adjustable delay unit RDC1 and one reverse output BPN3 of the third adjustable delay unit RDC3 are used as two outputs of the adjustable delay unit group and are respectively input to two input ends of the second and gate.

As shown in fig. 1, the delay between two signals arriving at the following and gate is generated by a group of adjustable delay cells. As shown in fig. 2, the reference input signal is first converted into a differential signal, reaches the first adjustable delay unit RDC1, and then is fed to the last two cascaded adjustable delay units. The positive output of the first adjustable delay unit RDC1 and the inverted output of the third adjustable delay unit RDC3 generate and operate on two signals BP1 and BN3, respectively. Accordingly, the pulse width of the pulse injected into the ring-shaped voltage controlled oscillator (injection pulse) should be equal to twice the delay time of the adjustable delay cell group. The pulse generator can adaptively adjust the pulse width at different PVT corners by sharing the same supply voltage VPVCO and control voltage VCTRL with the ring-shaped voltage-controlled oscillator. In embodiments of the present application, the corner point changes can be accommodated by manually changing the configuration of the low dropout regulator, and the temperature changes are automatically tracked by the control voltage adjusted in time.

As shown in fig. 5, is a ring voltage controlled oscillator for pulse locking. The annular voltage-controlled oscillator comprises four delay units and four transistors.

As shown in fig. 6, a conventional pulse generator includes two and gates and a delay cell unit DU. The outputs of the third and gate G3 are connected to the inputs of the delay cell group DU and the fourth and gate G4, respectively, and the inverted output of the delay cell group DU is connected to the other input of the fourth and gate G4.

The delay unit in the ring voltage-controlled oscillator and the delay unit group in the traditional pulse generator have the same purpose, and the specific internal structure can be the same or different.

As shown in fig. 5, the pulse INJ injected into the ring vco is applied to one of the four delay cells (DC 3 as shown), while the other injection transistors (T41, T42, and T44) connected to the delay cells are connected to ground to avoid interrupting the injection. The free running frequency of the annular voltage-controlled oscillator is adjusted by a power supply voltage VPVCO and a control voltage VCTRL together, the power supply voltage is adjusted to cover different process angles, and the control voltage carries out self-adaptive adjustment on the annular voltage-controlled oscillator to track temperature change.

Fig. 7 is a schematic circuit diagram of a delay unit in a ring-shaped voltage-controlled oscillator. The circuit comprises four NOT gates (G5, G6, G7 and G8), two transmission gates and two voltage-controlled capacitors (C1 and C2).

As shown in fig. 8, a circuit diagram of the phase measurement unit is shown, which includes a first charge pump and a phase measurer. Wherein the first charge pump further comprises a switching circuit. As shown in fig. 8, the phase measuring unit includes 26 transistors and a comparator, the transistor in the phase measurer is a first transistor, and the transistor in the first charge pump is a second transistor. The transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, and T10 are P-channel transistors, and the transistors T11, T12, T13, T14, T15, T16, T17, T18, T19, T20, T21, T22, T23, T24, T25, and T26 are N-channel transistors. The first charge pump uses large thick oxide transistors operating in the 2.5V power domain to achieve high matching accuracy, and the phase measurer uses 1.2V transistors to support high operating speeds.

Wherein the switch circuit in the first charge pump comprises transistors T9, T10, T15, T16 and a comparator. The positive input terminal of the comparator is connected to the drain of the transistor T10 and the drain of the transistor T16 at a point C, where the current iCP is obtained. The output end of the comparator is connected with the drain electrode of the transistor T19 and the drain electrode of the transistor T15 at a point D, and the negative input end of the comparator is also connected with the output end of the comparator. The sources of the transistors T9 and T10 are connected at point E, and the sources of the transistors T15 and T16 are connected at point F. The gate of T9 and the gate of T16 are connected to EN _ P, and the gate of T10 and the gate of T15 are connected to EN _ N.

The source of the transistor T1, the source of the transistor T3, the source of the transistor T5 and the source of the transistor T7 in the first charge pump are all connected to a power supply. The gate of T1 is connected to the gate of T7 and the current is amplified by β times, and the gate of T17 is connected to the gate of T18 and the current is amplified by β times. The gate of T3 and the gate of T5 are connected to P, and the drain of T13, the drain of T14 and the drain of T4 are also connected to P. The gates of T4 and T6 are connected to VBP, and the gates of T12 and T13 are connected to PO _ N. The gate of T2, the gate of T4, the gate of T6 and the gate of T8 are connected to VBP, and the gate of T11 and the gate of T14 are connected to PO _ P. The drain of T1 is connected to the source of T2, the drain of T2 is connected to the gate of T1, the drain of T11 and the drain of T12 at point N. The drain of T3 is connected to the source of T4, the drain of T5 is connected to the source of T6, the drain of T6 is connected to the drain of T17 and the gate of T17, and the source of T17 is grounded. The drain of T7 is connected to the source of T8, the source of T8 is connected to point E, the drain of T18 is connected to point F, and the source of T18 is connected to ground. The source of T11 and the source of T13 are connected to point A, and the source of T12 and the source of T14 are connected to point B.

Fig. 9 is an equivalent logic diagram of the phase measurer, wherein the point a is connected to one end of the switch S1, and the other end of S1 is connected to the PS _ P end and the ground, respectively. The node B is connected to one end of the switch S2, and the other end of the switch S1 is connected to the PS _ N terminal and the ground, respectively.

Fig. 10 is a schematic diagram showing equivalent logic and polarity selection of the phase measurer, wherein the point N is connected to one end of the switch S3, and the other end of the switch S3 is connected to the PSP _ P end and the ground, respectively. The point P is connected to one end of the switch S4, and the other end of S4 is connected to the PSP _ N terminal and the ground, respectively. The input current of the portion where N and P are connected to the switches S3 and S4 is Icp, which is equal to the current Icp.

In the phase measuring device, the drain of the transistor T19 and the drain of the transistor T20 are connected to a point a, and the drain of the transistor T23 and the drain of the transistor T24 are connected to a point B. The source of T19 is connected to the drain of T21, and the source of T21 is grounded. The source of T20 is connected to the drain of T22, and the source of T22 is grounded. The source of T23 is connected to the drain of T25, and the source of T25 is grounded. The source of T24 is connected to the drain of T26, and the source of T26 is grounded.

The phase measurement unit further comprises a polarity detector, which is introduced to maintain an edge independent output. As shown in fig. 11, the polarity detector includes two D flip-flops, D1 and D2. The clock multiplied signal is divided into CLK _ P and CLK _ N, where CLK _ P and pulses are input to D1, the PO _ P signal is output, CLK _ N and pulses are input to D2, and the PO _ N signal is output. The pulses Pulse (i.e., Pulse INJ) are all input to the clock input terminal of the D flip-flop.

Fig. 12(a) is a schematic diagram showing a lock condition. Fig. 12(b) is a schematic view showing another lock condition. The phase measurement unit first divides the injected pulse into two parts by the crossing point of the complementary clocks:

and

this difference in width is then converted into a current by the following first charge pump, wherein the instantaneous current is determined by the threshold voltage of the polarity selection transistor and the equivalent on-resistance of the phase detection transistor. As shown in the two lock-in conditions shown in fig. 12(a) and 12(b), both the rising and falling edges of the ring-shaped voltage-controlled oscillator (the rising and falling edges of CLK _ P, and the rising and falling edges of CLK _ N) can be locked to the injection pulse. This causes the detected phase difference (i.e. the difference in the widths of the two pulses in PS _ P and PS _ N) to show signs of marginalization. To solve this problem, polarity detectors have been introduced to distinguish the edge type at the moment of injection. In particular, when the injection position is swapped between two lock-out conditions, the connection of the detected pulses of PS _ P and PS _ N will be swapped by the polarity selection signals of PO _ P and PO _ N. Therefore, for both conditions shown in fig. 12(a) and 12(b), equivalent pulses of the same PSP _ P and PSP _ N can be obtained, and thus both edge-related output and positive feedback can be avoided.

As shown in fig. 13, a schematic diagram of a loop selection state machine includes: a Frequency Lock Detector (FLD) and a Loop Selector (LS). The frequency LOCK detector is used for inputting a clock frequency multiplication signal (DIV4_90) after being divided by 4 and a reference input signal (REF _ CLK), and outputting a first control signal (FRE _ LOCK) to the loop selector. The loop selector determines a loop control signal based on the first control signal and the INJ _ LOCK signal. The loop control signals include the TPD _ EN signal that controls the timing adjustment loop to be on and the PFD _ EN signal that controls the phase locked loop to be on. The INJ _ LOCK signal is derived from a delay of the PO _ P signal generated by the polarity detector.

As shown in fig. 13, the frequency lock detector includes two D flip-flops, D3 and D4, and one exclusive or gate XOR 1. The 4-divided clock multiplier signal is input to the D input terminal of D3, the clock input terminal of D4, the reference input signal is input to the clock input terminal of D3, and the reference input signal is input to the D input terminal of D4. The output signals FD1 and FD2 of D3 and D4 are both input to an exclusive or gate XOR1, and the output signal of the exclusive or gate XOR1 is a first control signal and is input to the loop selector.

The loop selector includes an exclusive or gate XOR2, a Saturation Edge Counter (SEC), and a timer. The two input ends of the exclusive or gate XOR2 respectively input the INJ _ LOCK signal and the first control signal, and the output end of the exclusive or gate XOR2 is connected to the saturation edge counter to input the output signal IND _ LOCK signal into the saturation edge counter. The saturation edge counter determines the loop control signal based on the IND _ LOCK signal and the reset signal RST. And the second loop control signal is a control signal which is generated when the timer runs to reach a time threshold and is used for controlling the multiplexer to start the timing adjustment loop. The saturation edge counter is also connected to a timer including three inverters (G21, G22, and G23), two transistors (T51 and T52), a capacitor C11, and a resistor R11 for starting timing according to the PFD _ EN signal. Taking 60ns as an example, when the timer reaches the time threshold of 60ns, the reset signal RST is generated and sent to the saturation edge counter.

As shown in fig. 14(a), it can be seen that injection locking of the ring voltage controlled oscillator is achieved when the clock rising edge of REF _ CLK and the clock low level of DIV4_90 and the FD1 signal, as well as the distance between the clock high level of REF _ CLK and FD2, remain at a fixed ratio throughout. As shown in fig. 14(b), when the ratio cannot be held fixed, the lock is lost. The frequency lock detector can quickly indicate false harmonic lock or a large frequency deviation by generating an edge jump, but as the frequency difference becomes smaller, as shown in fig. 14(c), it takes more time for the conventional frequency deviation to generate a cycle slip. To speed up LOCK loss detection, INJ _ LOCK (i.e., a delayed version of PO _ P generated by the polarity detector) is also applied to the loop selector. The total edge transition of the INJ _ LOCK and FRE _ LOCK signals is recorded by a saturation counter in the loop selector. In the loop selector, the edge transitions on the INJ _ LOCK and FRE _ LOCK signals are first xored and then recorded by the saturation counter. Once the number reaches a specified value, the loop selector controls the multiplexer to switch the loop from the timing adjustment loop to the phase locked loop to initiate the lock acquisition process. At the same time, a timer with a time constant of about 60ns is started to charge node a in fig. 13. When the voltage rises to the threshold of the inverter, the loop selector will reset, switching the phase locked loop back to the timing adjustment loop to enable injection locking. If the ring voltage controlled oscillator is successfully locked to the injection signal at the target frequency, then both INJ _ LOCK and FRE _ LOCK will remain quiescent, as will the loop selector, which is the LOCK loss detection and LOCK recovery process. Otherwise, the lock loss detection and lock recovery process will be repeated until injection locking is achieved. During initial startup, an injection lock may be obtained by repeating the lock loss detection and lock recovery process. During normal operation, a lock loss may be detected in time to activate a lock loss detection and lock recovery process. Since there are no signal transitions in the loop selection state machine during injection lock mode, the power cost in such lock loss detection and lock recovery is negligible.

Fig. 15 is a schematic circuit diagram of the filter. The filter comprises a switch S1, three capacitors (C21, C22 and C23) and two resistors (R21 and R22), the switch S1 being closed when the timing adjustment loop is open.

The pulse generator of the present application can automatically track PVT variations and keep the pulse width around twice the delay cell. The control voltage output by the timing adjusting loop controls the pulse generator and the annular voltage-controlled oscillator, so that self-adaptive pulse width adjustment can be realized, the pulse change from 9.32ps to 1.47ps can be optimized, and the tracking bandwidth can show good stability. The compact and compact signal connection adopted by the circuit in the phase measurement unit enables the circuit to support high operation speed with low power consumption; the circuit improves the matching precision and the working allowance of each current mirror, thereby optimizing the current matching precision; the race condition between injection locking and frequency tracking loop locking in conventional designs is eliminated in this design. The lock loss detection and lock recovery process of the loop selection state machine improves the lock acquisition capability, such that start failures and possible injection lock losses are completely resolved.

In the embodiment of the application, the pulse width of the pulse generated by the pulse generator can be adaptively adjusted at different PVT corners, and a fixed proportion is always kept, so that the clock frequency multiplier is always in the best performance state; the loop is determined by the loop selection state machine according to the reference input signal and the clock frequency multiplication signal, the control voltage is output by the phase measurement unit, the pulse generator in the pulse injection locking oscillation module can be controlled to adjust the width of the pulse according to the power supply voltage and the control voltage, the tracking bandwidth of the pulse injection locking oscillator is improved, and therefore the clock frequency multiplication signal generated by the annular voltage-controlled oscillator is improved. The implementation mode of the application can also effectively prevent the mutual pulling problem in the traditional injection locking and phase-locked loop, and simultaneously keeps the good in-band noise suppression performance and the higher working robustness, so that the implementation mode becomes a competitive choice in practical application. Detecting frequency deviation through a phase measurer closely combined with a first charge pump with good matching to generate a control voltage; the pulse generator and the annular voltage-controlled oscillator are controlled by the control voltage output by the timing adjusting loop, so that self-adaptive pulse width adjustment can be realized, and the specific pulse width of a PVT angle is kept; the lock loss detection and the lock recovery process are carried out in real time through the loop selection state machine, the lock loss detection can be carried out quickly, the lock recovery process can be started quickly, and the lock capture capacity is improved.

The above description is only for the preferred embodiment of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A pulse generator, comprising: the delay circuit comprises a first AND gate, an adjustable delay unit group and a second AND gate;

2. The pulse generator of claim 1, wherein the set of adjustable delay cells comprises: the circuit comprises a NOT gate, a transmission gate, three adjustable delay units and three transistors;

3. A clock multiplier, comprising: the pulse injection locking oscillation module and the tracking module are connected with each other;

the pulse injection locked oscillation module includes: a pulse generator according to claim 1 or2 and a ring voltage controlled oscillator connected in series;

4. The clock multiplier of claim 3, wherein the phase measurement unit comprises: the phase measurer and the first charge pump are connected in sequence;

5. The clock multiplier of claim 3, wherein the phase measurement unit further comprises a polarity detector connected to the first charge pump.

6. The clock multiplier of claim 3, wherein the phase frequency and phase detection unit comprises: the frequency divider, the phase frequency detector and the second charge pump are connected in sequence;

7. The clock multiplier of claim 3, wherein the loop selection state machine comprises: a frequency lock detector and a loop selector;

8. The clock multiplier of claim 3,

the pulse generator generates pulses according to a reference input signal, a power supply voltage and a control voltage generated by the tracking module;

9. The clock multiplier of claim 3, wherein the tracking module comprises two loops, one of which is a phase-locked loop and the other of which is a timing adjustment loop;