CN117855280A - 超结碳化硅mosfet及其制备方法、芯片 - Google Patents
超结碳化硅mosfet及其制备方法、芯片 Download PDFInfo
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 72
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 71
- 238000002360 preparation method Methods 0.000 title claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 239000003989 dielectric material Substances 0.000 claims abstract description 12
- 238000003892 spreading Methods 0.000 claims description 36
- 150000002500 ions Chemical class 0.000 claims description 32
- 229920005591 polysilicon Polymers 0.000 claims description 25
- 238000005530 etching Methods 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 11
- 230000005684 electric field Effects 0.000 abstract description 7
- 239000002019 doping agent Substances 0.000 description 11
- 239000000463 material Substances 0.000 description 11
- 239000004065 semiconductor Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000000779 depleting effect Effects 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
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Abstract
本申请属于功率器件技术领域,提供了一种超结碳化硅MOSFET及其制备方法、芯片,通过在源极层下方形成与栅极层连接的P型多晶硅层,实现从源极层、P型多晶硅层、电流扩展层、N型漂移区、碳化硅衬底到漏极层的续流通道,使得器件的导通电阻大大低于其体二极管,提高了器件的第三象限性能。并通过在P柱的一侧设置高K介质层可以提升器件的击穿电压,并在P柱的另一侧形成N型漂移区,P柱的引入可以辅助耗尽N型漂移区,如此可以降低高K介质层所需的介质材料的介电常数,由高K介质层吸引N型漂移区的大部分电场线,并且在P柱和N型漂移区之间存在电荷不平衡的情况下也可以避免降低器件的性能。
Description
技术领域
本申请属于功率器件技术领域,尤其涉及一种超结碳化硅MOSFET及其制备方法、芯片。
背景技术
碳化硅(SiC)作为第三代半导体材料的典型代表,也是目前晶体生产技术和器件制造水平最成熟,应用最广泛的宽禁带半导体材料之一。目前,SiC已经形成了全球的材料、器件和应用产业链。SiC金氧半场效晶管(Metal-Oxide- SemiconductorField-EffectTransistor,MOSFET)属于新型的功率半导体器件,由于碳化硅材料具有较高的击穿电场,较高的饱和漂移速度,因此,碳化硅MOSFET具有高击穿电压和高频特性。
碳化硅MOSFET目前所采用的传统的超结结构容易受电荷不平衡的影响而降低器件的击穿电压(BV),为了缓解电荷不平衡的影响,可以在器件内采用介电常数高于200的高K介质层代替器件内的P柱结构,然而,介电常数高于200的高K介质材料存在成本高、数量稀缺的问题。
发明内容
为了解决上述技术问题,本申请实施例提供了一种超结碳化硅MOSFET及其制备方法、芯片,可以在解决目前的常规结构的超结碳化硅MOSFET中需要采用介电常数高于200的高K介质材料所存在的成本高、数量稀缺的问题。
本申请实施例第一方面提供了一种超结碳化硅MOSFET,所述超结碳化硅MOSFET包括:
碳化硅衬底和漏极层,所述漏极层形成于所述碳化硅衬底的背面;
高K介质层、P柱以及N型漂移区,分别形成于所述碳化硅衬底的正面,其中,所述P柱形成于所述高K介质层和所述N型漂移区之间;
第一P型掺杂区和P型多晶硅层,所述第一P型掺杂区形成于所述P型多晶硅层和所述P柱之间,且所述P型多晶硅层与所述高K介质层接触;
电流扩展层和第二P型掺杂区,形成于所述N型漂移区上;
P型基区,形成于所述电流扩展层上;
栅极介质层,形成于所述第二P型掺杂区上;
P型源极区和N型源极区,形成于所述P型基区上,且所述N型源极区与所述栅极介质层接触;
栅极层,形成于所述栅极介质层上;其中,所述栅极介质层隔离所述栅极层与所述P型基区;
源极层,形成于所述P型多晶硅层、所述P型源极区以及所述N型源极区上。
在一些实施例中,所述P柱的宽度与所述第一P型掺杂区的宽度相同。
在一些实施例中,所述高K介质层的宽度大于所述P柱的宽度,且所述高K介质层的宽度小于所述N型漂移区的宽度。
在一些实施例中,所述P型多晶硅层的高度大于所述电流扩展层与所述P型基区之和,且所述P型多晶硅层分别与所述电流扩展层、所述P型基区以及所述P型源极区接触。
在一些实施例中,所述电流扩展层的厚度大于所述第二P型掺杂区的厚度。
在一些实施例中,所述高K介质层的介电常数大于30。
在一些实施例中,所述栅极介质层为氧化硅或者氮化硅。
在一些实施例中,所述电流扩展层的掺杂浓度大于所述N型漂移区的掺杂浓度。
本申请实施例第二方面还提供了一种超结碳化硅MOSFET的制备方法,所述超结碳化硅MOSFET的制备方法包括:
在碳化硅衬底的正面依次注入N型掺杂离子形成N型漂移区和电流扩展层;
对所述电流扩展层和所述N型漂移区进行刻蚀,在所述碳化硅衬底上形成第一深槽,在所述电流扩展层上形成第二深槽,并在所述第一深槽的侧壁注入P型掺杂离子形成P柱;其中,所述电流扩展层为L形结构;
对所述P柱进行刻蚀,以使所述P柱的高度小于或者等于所述N型漂移区的高度;
在所述P柱上注入P型掺杂离子形成第一P型掺杂区,在所述电流扩展层的水平部的部分区域注入P型掺杂离子形成第二P型掺杂区,在所述电流扩展层的垂直部依次注入P型掺杂离子和N型掺杂离子形成P型基区、P型源极区和N型源极区;
在所述第一深槽内填充高K介质材料形成高K介质层,并在所述第一P型掺杂区和所述高K介质层上形成P型多晶硅层;其中,所述高K介质层与所述电流扩展层之间形成异质结结构;
在所述第二深槽内形成栅极介质层以及栅极层,并在所述P型多晶硅层上形成源极层,在所述碳化硅衬底的背面形成漏极层;且所述栅极介质层隔离所述栅极层与所述P型基区。
本申请实施例第三方面还提供了一种芯片,包括如上述任一项实施例所述的超结碳化硅MOSFET;或者包括如上述任一项实施例所述的制备方法制备的超结碳化硅MOSFET。
本申请实施例的有益效果:通过在源极层下方形成与栅极层连接的P型多晶硅层,实现从源极层、P型多晶硅层、电流扩展层、N型漂移区、碳化硅衬底到漏极层的续流通道,使得器件的导通电阻大大低于其体二极管,提高了器件的第三象限性能。并通过在P柱的一侧设置高K介质层可以提升器件的击穿电压,并在P柱的另一侧形成N型漂移区,P柱的引入可以辅助耗尽N型漂移区,如此可以降低高K介质层所需的介质材料的介电常数,由高K介质层吸引N型漂移区的大部分电场线,并且在P柱和N型漂移区之间存在电荷不平衡的情况下也可以避免降低器件的性能。
附图说明
图1是本申请实施例提供的超结碳化硅MOSFET的结构示意图;
图2是本申请实施例提供的超结碳化硅MOSFET的制备方法的流程示意图;
图3是本申请实施例提供的形成N型漂移区和电流扩展层后的示意图;
图4是本申请实施例提供的形成第一深槽后的示意图;
图5是本申请实施例提供的对P柱和电流扩展层刻蚀后的示意图;
图6是本申请实施例提供的形成P型基区、P型源极区和N型源极区后的示意图;
图7是本申请实施例提供的形成P型多晶硅、栅极介质层、栅极层后的示意图。
具体实施方式
为了使本申请所要解决的技术问题、技术方案及有益效果更加清楚明白,以下结合附图及实施例,对本申请进行进一步详细说明。应当理解,此处所描述的具体实施例仅仅用以解释本申请,并不用于限定本申请。
碳化硅MOSFET目前所采用的传统的超结结构容易受电荷不平衡的影响而降低器件的击穿电压(BV),为了缓解电荷不平衡的影响,可以在器件内采用介电常数高于200的高K介质层代替器件内的P柱结构,然而,介电常数高于200的高K介质材料存在成本高、数量稀缺的问题。
为了解决上述技术问题,本申请实施例提供了一种超结碳化硅MOSFET,参见图1所示,超结碳化硅MOSFET包括:碳化硅衬底100、漏极层510、高K介质层210、P柱220、N型漂移区230、第一P型掺杂区240、P型多晶硅层310、电流扩展层320、第二P型掺杂区360、P型基区330、栅极介质层410、P型源极区340、N型源极区350、栅极层420、源极层520,其中,漏极层510形成于碳化硅衬底100的背面,高K介质层210、P柱220、N型漂移区230分别形成于碳化硅衬底100的正面,P柱220形成于高K介质层210和N型漂移区230之间。第一P型掺杂区240形成于P型多晶硅层310和P柱220之间,且P型多晶硅层310与高K介质层210接触,电流扩展层320和第二P型掺杂区360形成于N型漂移区230上;P型基区330形成于电流扩展层320上。栅极介质层410形成于第二P型掺杂区360上。P型源极区340和N型源极区350形成于P型基区330上,且N型源极区350与栅极介质层410接触。栅极层420形成于栅极介质层410上,其中,栅极介质层410隔离栅极层420与P型基区330。源极层520形成于P型多晶硅层310、P型源极区340以及N型源极区350上。
在本实施例中,通过在源极层520下方形成与栅极层420连接的P型多晶硅层310,实现从源极层520、P型多晶硅层310、电流扩展层320、N型漂移区230、碳化硅衬底100到漏极层510的续流通道,使得器件的导通电阻大大低于其体二极管,提高了器件的第三象限性能。并通过在P柱220的一侧设置高K介质层210可以提升器件的击穿电压,并在P柱220的另一侧形成N型漂移区230,P柱220的引入可以辅助耗尽N型漂移区230,如此可以降低高K介质层210所需的介质材料的介电常数,由高K介质层210吸引N型漂移区230的大部分电场线,并且在P柱220和N型漂移区230之间存在电荷不平衡的情况下也可以避免降低器件的性能。
在一些实施例中,结合图1所示,P柱220的宽度与第一P型掺杂区240的宽度相同。
在本实施例中,P柱220形成于高K介质层210和N型漂移区230之间,P柱220分别与其左侧的高K介质层210和其右侧的N型漂移区230接触,此时,P柱220与N型漂移区230之间会形成PN结,P柱220上方的第一P型掺杂区240与N型漂移区230之间形成PN结,第一P型掺杂区240形成于高K介质层210和N型漂移区230之间,并且第一P型掺杂区240分别与其左侧的高K介质层210和其右侧的N型漂移区230接触,从而将传统的N型柱/P型柱超级结构优化为本实施例中的高K介质层210/P柱220/N型漂移区230的超结结构,通过引入在高K介质层210和N型漂移区230之间引入P柱220可以辅助耗尽N型漂移区230,大大降低高K介质层210的介电常数,此时利用高K介质层210可以吸引N型漂移区230的大部分电场线,即使在P柱220和N型漂移区230之间存在电荷不平衡的情况下也可以避免降低器件的性能。
在一些实施例中,N型漂移区230可以通过在外延生长的碳化硅材料中注入N型掺杂离子形成,P柱220可以通过在N型漂移区230的一侧注入P型掺杂离子形成。
在一些实施例中,第一P型掺杂区240内的P型掺杂离子的掺杂浓度大于P柱220内的P型掺杂离子的掺杂浓度。
在一些实施例中,结合图1所示,高K介质层210的宽度大于P柱220的宽度,且高K介质层210的宽度小于N型漂移区230的宽度。
在一些实施例中,结合图1所示,P型多晶硅层310的高度大于电流扩展层320与P型基区330之和,且P型多晶硅层310分别与电流扩展层320、P型基区330以及P型源极区340接触。
在本实施例中,P型多晶硅层310形成于源极层520与高K介质层210之间,以及源极层520与第一P型掺杂区240之间,P型多晶硅层310与电流扩展层320之间形成异质结,通过引入P型多晶硅层310,实现从源极层520、P型多晶硅层310、电流扩展层320、N型漂移区230、碳化硅衬底100以及漏极层510的续流通道,使得器件的导通电阻低于其内部的体二极管的电阻,提高器件的第三象限性能,改善器件的双极退化。
在一些实施例中,结合图1所示,电流扩展层320的厚度大于第二P型掺杂区360的厚度。
在一些实施例中,高K介质层210的介电常数大于30。
在本实施例中,通过在P柱220的一侧设置高K介质层210可以提升器件的击穿电压,并在P柱220的另一侧形成N型漂移区230,P柱220的引入可以辅助耗尽N型漂移区230,如此可以大大缓解超结器件内的P柱220和N柱电荷不平衡导致的击穿电压下降的问题,并且通过P柱220的引入辅助耗尽N型漂移区230,使得高K介质层210所需的介质材料的介电常数只需要大于30即可,在传统的超结MOSFET器件中,其高K介质材料的介电常数需要200以上才能达到同样的效果。
在一些实施例中,栅极介质层410为氧化硅或者氮化硅。
在一些实施例中,源极层520和漏极层510可以为金属电极材料,例如金、银、铜等金属电极材料,栅极介质层410包裹栅极层420,栅极介质层410可以隔离源极层520与栅极层420,栅极层420可以为多晶硅材料,该多晶硅材料通过栅极介质层410上的通孔与外部的栅极电极连接,可以通过对栅极电极施加栅极电压控制器件的工作状态。
在一些实施例中,电流扩展层320的掺杂浓度大于N型漂移区230的掺杂浓度。
在本实施例中,电流扩展层320(CSL层)是半导体器件中的一种材料层,其全称为“超晶格抑制层”(Superlattice SuppressionLayer),通常用于控制半导体器件中的载流子注入和提高器件的性能,可以通过在N型漂移区230上注入浓度更高的N型掺杂离子形成。
本申请实施例还提供了一种超结碳化硅MOSFET的制备方法,参见图2所示,本实施例中的超结碳化硅MOSFET的制备方法包括步骤S100至步骤S600。
在步骤S100中,在碳化硅衬底的正面依次注入N型掺杂离子形成N型漂移区230和电流扩展层320。
在本实施例中,参见图3所示,可以通过在碳化硅衬底的正面外延生长碳化硅材料,并在碳化硅材料中注入N型掺杂离子形成N型漂移区230,然后再N型漂移区230的正面注入浓度更高的N型掺杂离子形成电流扩展层320。
在一些实施例中,电流扩展层320的掺杂浓度至少为N型漂移区230的掺杂浓度的10倍。
在一些实施例中,电流扩展层320的厚度小于N型漂移区230的厚度。
在步骤S200中,对电流扩展层320和N型漂移区230进行刻蚀,在碳化硅衬底上形成第一深槽201,在电流扩展层320上形成第二深槽202,并在第一深槽201的侧壁注入P型掺杂离子形成P柱220;其中,电流扩展层320为L形结构。
在本实施例中,参见图4所示,对碳化硅衬底的一侧进行刻蚀,刻蚀深入至碳化硅衬底,从而形成第一深槽201。在第一深槽201的侧壁注入P型掺杂离子形成P柱220,如图4所示。对电流扩展层320进行刻蚀,在电流扩展层320上形成第二深槽202,使得电流扩展层320的形状为L形,如图5所示。
在步骤S300中,对P柱220进行刻蚀,以使P柱220的高度小于或者等于N型漂移区230的高度。
在本实施例中,如图5所示,对P柱220进行刻蚀,以使P柱220的高度小于或者等于N型漂移区230的高度,P柱220的上表面至少低于电流扩展层320的底面。
在步骤S400中,在P柱220上注入P型掺杂离子形成第一P型掺杂区240,在电流扩展层320的水平部的部分区域注入P型掺杂离子形成第二P型掺杂区360,在电流扩展层320的垂直部依次注入P型掺杂离子和N型掺杂离子形成P型基区330、P型源极区340和N型源极区350。
在本实施例中,如图6所示,在P柱220上注入P型掺杂离子形成第一P型掺杂区240,并在电流扩展层320的部分区域的水平部的部分区域注入P型掺杂离子形成第二P型掺杂区360,在电流扩展层320的垂直部依次注入P型掺杂离子形成P型基区330,在P型基区330上依次注入P型掺杂离子和N型掺杂离子形成P型源极区340和N型源极区350,P型源极区340的掺杂浓度大于P型基区330的掺杂浓度,P型源极区340与N型源极区350之间形成PN结,P型基区330与N型源极区350之间形成PN结。
在步骤S500中,在第一深槽201内填充高K介质材料形成高K介质层210,并在所述第一P型掺杂区240和所述高K介质层210上形成P型多晶硅层310。
在本实施例中,高K介质层210与所述电流扩展层320之间形成异质结结构。
在本实施例中,如图7所示,通过多晶硅材料沉积工艺在第一深槽201内沉积多晶硅材料,并注入P型掺杂离子形成P型多晶硅层310。
在步骤S600中,在第二深槽202内形成栅极介质层410以及栅极层420,并在P型多晶硅层310上形成源极层520,在碳化硅衬底的背面形成漏极层510;且栅极介质层410隔离栅极层420与P型基区330。
本申请实施例还提供了一种芯片,包括如上述任一项实施例所述的超结碳化硅MOSFET。
在本实施例中,芯片包括芯片碳化硅衬底,碳化硅衬底上设置有一个或者多个超结碳化硅MOSFET,该超结碳化硅MOSFET可以由上述任一项实施例中的制备方法制备,也可以在芯片碳化硅衬底上设置上述任一项实施例中的超结碳化硅MOSFET。
在一个具体应用实施例中,芯片碳化硅衬底上还可以集成其他相关的半导体器件,以和超结碳化硅MOSFET组成集成电路。
在一个具体应用实施例中,该芯片可以为开关芯片或者驱动芯片。
本申请实施例的有益效果:通过在源极层下方形成与栅极层连接的P型多晶硅层,实现从源极层、P型多晶硅层、电流扩展层、N型漂移区、碳化硅衬底到漏极层的续流通道,使得器件的导通电阻大大低于其体二极管,提高了器件的第三象限性能。并通过在P柱的一侧设置高K介质层可以提升器件的击穿电压,并在P柱的另一侧形成N型漂移区,P柱的引入可以辅助耗尽N型漂移区,如此可以降低高K介质层所需的介质材料的介电常数,由高K介质层吸引N型漂移区的大部分电场线,并且在P柱和N型漂移区之间存在电荷不平衡的情况下也可以避免降低器件的性能。
所属领域的技术人员可以清楚地了解到,为了描述的方便和简洁,仅以上述各掺杂区、器件的划分进行举例说明,实际应用中,可以根据需要而将上述功能分配由不同的掺杂区、器件完成,即将器件置的内部结构划分成不同的掺杂区,以完成以上描述的全部或者部分功能。实施例中的各掺杂区、器件可以集成在一个单元中,也可以是各个单元单独物理存在,也可以两个或两个以上单元集成在一个单元中。
另外,各掺杂区、器件的具体名称也只是为了便于相互区分,并不用于限制本申请的保护范围。
在上述实施例中,对各个实施例的描述都各有侧重,某个实施例中没有详述或记载的部分,可以参见其它实施例的相关描述。
另外,在本申请各个实施例中的各掺杂区可以集成在一个单元中,也可以是各个单元单独物理存在,也可以两个或两个以上单元集成在一个单元中。
以上实施例仅用以说明本申请的技术方案,而非对其限制;尽管参照前述实施例对本申请进行了详细的说明,本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围,均应包含在本申请的保护范围之内。
Claims (10)
1.一种超结碳化硅MOSFET,其特征在于,所述超结碳化硅MOSFET包括:
碳化硅衬底和漏极层,所述漏极层形成于所述碳化硅衬底的背面;
高K介质层、P柱以及N型漂移区,分别形成于所述碳化硅衬底的正面,其中,所述P柱形成于所述高K介质层和所述N型漂移区之间;
第一P型掺杂区和P型多晶硅层,所述第一P型掺杂区形成于所述P型多晶硅层和所述P柱之间,且所述P型多晶硅层与所述高K介质层接触;
电流扩展层和第二P型掺杂区,形成于所述N型漂移区上;
P型基区,形成于所述电流扩展层上;
栅极介质层,形成于所述第二P型掺杂区上;
P型源极区和N型源极区,形成于所述P型基区上,且所述N型源极区与所述栅极介质层接触;
栅极层,形成于所述栅极介质层上;其中,所述栅极介质层隔离所述栅极层与所述P型基区;
源极层,形成于所述P型多晶硅层、所述P型源极区以及所述N型源极区上。
2.如权利要求1所述的超结碳化硅MOSFET,其特征在于,所述P柱的宽度与所述第一P型掺杂区的宽度相同。
3.如权利要求2所述的超结碳化硅MOSFET,其特征在于,所述高K介质层的宽度大于所述P柱的宽度,且所述高K介质层的宽度小于所述N型漂移区的宽度。
4.如权利要求1所述的超结碳化硅MOSFET,其特征在于,所述P型多晶硅层的高度大于所述电流扩展层与所述P型基区之和,且所述P型多晶硅层分别与所述电流扩展层、所述P型基区以及所述P型源极区接触。
5.如权利要求1所述的超结碳化硅MOSFET,其特征在于,所述电流扩展层的厚度大于所述第二P型掺杂区的厚度。
6.如权利要求1所述的超结碳化硅MOSFET,其特征在于,所述高K介质层的介电常数大于30。
7.如权利要求1-6任一项所述的超结碳化硅MOSFET,其特征在于,所述栅极介质层为氧化硅或者氮化硅。
8.如权利要求1-6任一项所述的超结碳化硅MOSFET,其特征在于,所述电流扩展层的掺杂浓度大于所述N型漂移区的掺杂浓度。
9.一种超结碳化硅MOSFET的制备方法,其特征在于,所述超结碳化硅MOSFET的制备方法包括:
在碳化硅衬底的正面依次注入N型掺杂离子形成N型漂移区和电流扩展层;
对所述电流扩展层和所述N型漂移区进行刻蚀,在所述碳化硅衬底上形成第一深槽,在所述电流扩展层上形成第二深槽,并在所述第一深槽的侧壁注入P型掺杂离子形成P柱;其中,所述电流扩展层为L形结构;
对所述P柱进行刻蚀,以使所述P柱的高度小于或者等于所述N型漂移区的高度;
在所述P柱上注入P型掺杂离子形成第一P型掺杂区,在所述电流扩展层的水平部的部分区域注入P型掺杂离子形成第二P型掺杂区,在所述电流扩展层的垂直部依次注入P型掺杂离子和N型掺杂离子形成P型基区、P型源极区和N型源极区;
在所述第一深槽内填充高K介质材料形成高K介质层,并在所述第一P型掺杂区和所述高K介质层上形成P型多晶硅层;其中,所述高K介质层与所述电流扩展层之间形成异质结结构;
在所述第二深槽内形成栅极介质层以及栅极层,并在所述P型多晶硅层上形成源极层,在所述碳化硅衬底的背面形成漏极层;且所述栅极介质层隔离所述栅极层与所述P型基区。
10.一种芯片,其特征在于,包括如权利要求1-8任一项所述的超结碳化硅MOSFET;或者包括如权利要求9所述的制备方法制备的超结碳化硅MOSFET。
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