CN117352597A - Preparation method of solar cell, solar cell and electric equipment - Google Patents

Preparation method of solar cell, solar cell and electric equipment Download PDF

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CN117352597A
CN117352597A CN202311648231.9A CN202311648231A CN117352597A CN 117352597 A CN117352597 A CN 117352597A CN 202311648231 A CN202311648231 A CN 202311648231A CN 117352597 A CN117352597 A CN 117352597A
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silicon wafer
boron
target
target silicon
solar cell
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CN117352597B (en
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徐宸
闫用用
吴新荣
蔡伦
刘向东
洪成浩
申品文
蒋兆鹏
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Yidao New Energy Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0236—Special surface textures
    • H01L31/02363—Special surface textures of the semiconductor body itself, e.g. textured active layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
    • H01L31/1864—Annealing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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Abstract

The invention provides a preparation method of a solar cell, the solar cell and electric equipment, and relates to the technical field of new energy. The method comprises the following steps: obtaining a target silicon wafer; the target silicon wafer comprises a first surface with a suede structure; carrying out laser grooving treatment on the first surface to obtain a grooved surface; performing boron diffusion treatment on the grooved surface to obtain a target silicon wafer subjected to boron diffusion; the target silicon wafer after boron expansion comprises an emitter layer covered on the surface of the notch; annealing the target silicon wafer subjected to boron expansion to obtain an annealed target silicon wafer; performing secondary boron diffusion treatment on the annealed target silicon wafer to obtain a target silicon wafer subjected to secondary boron diffusion; and preparing the target solar cell based on the target silicon wafer subjected to secondary boron expansion. The embodiment of the invention can reduce the damage degree of laser grooving treatment to the texture structure on the surface of the silicon wafer, reduce the surface reflectivity of the target silicon wafer after secondary boron expansion and improve the photoelectric conversion efficiency of the target solar cell.

Description

Preparation method of solar cell, solar cell and electric equipment
Technical Field
The invention relates to the technical field of new energy, in particular to a preparation method of a solar cell, the solar cell and electric equipment.
Background
A selective emitter (selective emitter, SE) solar cell is a cell in which heavily doping is performed at the contact portion of the electrode and the silicon wafer, and lightly doping is performed between the electrodes. The doping mode of the selective emitter solar cell can reduce the recombination of diffusion layers, reduce the contact resistance between the electrode and the silicon wafer, and improve the photoelectric conversion efficiency of the cell.
At present, the method for preparing the selective emitter solar cell mainly comprises the steps of carrying out laser grooving on the basis of one-time light expansion, so that an emitter region forms a heavy expansion region, other regions form light expansion regions, and finally oxidizing a silicon wafer subjected to laser grooving to form a PN junction.
However, in the related art, the textured structure on the surface of the silicon wafer is damaged during the laser grooving process, which results in an increase in reflectivity of the silicon wafer and further results in a decrease in photoelectric conversion efficiency of the solar cell.
Disclosure of Invention
The invention provides a preparation method of a solar cell, the solar cell and electric equipment, and aims to solve the problems of increased silicon wafer reflectivity and reduced photoelectric conversion efficiency of the solar cell in the process of preparing a selective emitter solar cell in the related technology.
In order to solve the problems, the technical scheme of the invention is realized as follows:
The embodiment of the invention provides a preparation method of a solar cell, which comprises the following steps:
obtaining a target silicon wafer; the target silicon wafer is an N-type silicon wafer and comprises a first surface with a suede structure;
carrying out laser grooving treatment on the first surface to obtain a grooved surface;
performing boron diffusion treatment on the grooved surface to obtain a target silicon wafer subjected to boron diffusion; the boron-amplified target silicon wafer comprises an emitter layer covered on the surface of the notch, wherein the emitter layer comprises a P-type heavy doping region and a P-type light doping region;
annealing the target silicon wafer subjected to boron expansion to obtain an annealed target silicon wafer;
performing secondary boron diffusion treatment on the annealed target silicon wafer to obtain a target silicon wafer subjected to secondary boron diffusion; the target silicon wafer subjected to secondary boron expansion comprises an oxide layer covered on the surface of the notch;
and preparing the target solar cell based on the target silicon wafer subjected to secondary boron expansion.
Optionally, the performing boron diffusion treatment on the grooved surface to obtain a target silicon wafer after boron diffusion includes:
performing boron diffusion treatment on the grooved surface by utilizing a boron source at a first temperature to obtain a target silicon wafer subjected to boron diffusion;
Wherein the first temperature is 880-920 ℃, the diffusion duration of the boron diffusion treatment is 650-750 s, and the gas flow of the boron source is 550-750 sccm.
Alternatively, the laser grooving process has a grooving width of 70 μm to 90 μm.
Optionally, the annealing treatment is performed on the target silicon wafer after boron expansion to obtain an annealed target silicon wafer, which comprises the following steps:
reducing the temperature of the target silicon wafer subjected to boron expansion from the first temperature to the second temperature according to the target cooling rate to obtain an annealed target silicon wafer;
wherein the second temperature is 680-720 ℃, and the target cooling rate is 7-13 ℃/min.
Optionally, the third temperature of the secondary boron diffusion treatment is 950 ℃ to 1100 ℃, the diffusion duration of the secondary boron diffusion treatment is 59min to 61min, and the oxygen inflow rate of the secondary boron diffusion treatment is 1500sccm to 2500sccm.
Optionally, the oxide layer has a thickness of 90nm to 110nm.
Optionally, the square resistance of the target silicon wafer after boron expansion is 90 Ω to 130 Ω, and the square resistance of the target silicon wafer after secondary boron expansion is 200 Ω to 240 Ω.
Optionally, the surface concentration of the target silicon wafer after secondary boron expansion is To->The junction depth of the target silicon wafer after secondary boron expansion is 0.6-0.7 mu m.
The embodiment of the invention also provides a solar cell, which is prepared by adopting the preparation method of the solar cell.
The embodiment of the invention also provides electric equipment, which comprises the solar battery, wherein the solar battery is used as a power supply of the electric equipment.
According to the preparation method of the solar cell, firstly, grooving treatment is carried out on the first surface with the suede structure in the target silicon wafer to obtain a grooved surface, and then boron diffusion treatment is carried out on the grooved surface to obtain the boron-expanded target silicon wafer comprising the emitter layer; and then, annealing the target silicon wafer subjected to boron expansion to repair the crystal lattice of the texture structure damaged in the grooving process, so that the damage degree of laser grooving to the texture structure on the first surface is reduced. And finally, preparing the target solar cell based on the target silicon wafer subjected to secondary boron expansion obtained by annealing treatment and secondary boron diffusion treatment, so that the damage degree of laser grooving treatment to the textured structure of the surface of the silicon wafer can be reduced while good ohmic contact between the printing electrode and the P-type heavily doped region is ensured, the surface reflectivity of the target silicon wafer subjected to secondary boron expansion is reduced, and the photoelectric conversion efficiency of the target solar cell is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments of the present invention will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 shows a flow chart of steps of a method for manufacturing a solar cell according to an embodiment of the present invention;
FIG. 2 shows a schematic structural diagram of a target silicon wafer according to an embodiment of the present invention;
fig. 3 is a flowchart illustrating steps of another method for manufacturing a solar cell according to an embodiment of the present invention;
fig. 4 shows a schematic preparation flow chart of a preparation method of a solar cell according to an embodiment of the invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, there is shown a step flow chart of a method for manufacturing a solar cell according to an embodiment of the present invention, the method including steps S110 to S160:
step S110, obtaining a target silicon wafer; the target silicon wafer is an N-type silicon wafer and comprises a first surface with a textured structure.
The target silicon wafer is a silicon wafer obtained by texturing an N-type original silicon wafer. The target silicon wafer includes a first surface and a second surface opposite the first surface. The first surface and the second surface of the target silicon wafer may be both surfaces with a textured structure, or only the first surface may be a surface with a textured structure. The first surface is the front surface (light incident surface) of the target solar cell, and the second surface is the back surface (backlight surface) of the target solar cell.
In the embodiment of the invention, the suede structure is prepared on the first surface of the N-type original silicon wafer, so that the reflection loss of the front surface of the target solar cell obtained in the step S160 can be reduced, and the photoelectric conversion efficiency of the target solar cell can be improved. It can be understood that the suede structure of the first surface is a pyramid structure, and light refraction can occur when external light enters the first surface of the pyramid structure, so that the light absorptivity of the silicon wafer can be improved compared with the first surface of the planar structure, and further the photoelectric conversion efficiency of the target solar cell is improved.
Specifically, a groove type texturing mode can be adopted, and texturing treatment is carried out on the first surface and the second surface of the original silicon wafer by utilizing a texturing solution, so that the first surface and the second surface can have a textured structure; and a single-sided texturing mode can be adopted, and texturing solution is utilized to carry out texturing treatment on the first surface of the original silicon wafer, so that the first surface of the target silicon wafer has a textured structure.
Wherein, the texturing solution can be sodium hydroxide solution or sodium hydroxide solution, the ratio of the sodium hydroxide solution or sodium hydroxide in the texturing solution is 1 to 3 percent, and the ratio of the texturing additive is 0.45 to 0.65 percent. The texturing additive comprises deionized water, a surfactant, sodium polystyrene sulfonate, a defoaming agent and other chemical components, wherein the proportion of the deionized water in the texturing additive is 84%, the proportion of the surfactant in the texturing additive is 4%, the proportion of the sodium polystyrene sulfonate in the texturing additive is 5%, the proportion of the defoaming agent in the texturing additive is 2%, and the proportion of the other chemical components in the texturing additive is 5%. It should be noted that, in the embodiment of the present invention, the duty ratio may be a mass duty ratio or a volume duty ratio, which is not particularly limited in the embodiment of the present invention.
And step S120, carrying out laser grooving treatment on the first surface to obtain a grooved surface.
Wherein the grooved surface includes a grooved region and an ungrooved region. The grooving region is a groove region formed by laser cladding on the first surface in the grooving process, and the grooving depth of the grooving region can be 1.4 mu m; the un-grooved region is a region outside the grooved region in the grooved surface, and the un-grooved region retains the suede structure of the first surface, but in the laser grooving process, the suede structure of the un-grooved region is damaged to some extent, so that the reflectivity of the un-grooved region is higher than that of the first surface.
Specifically, the number of grooves and the width of grooves formed in the first surface by laser grooving treatment can be determined according to the number of grid lines and the width of the grid lines of the thin grid in the target solar cell, wherein the number of groove data is the same as the number of the grid lines, and the groove areas obtained after laser grooving correspond to the thin grid one by one; the width of the notch can be larger than that of the grid line, so that conductive paste corresponding to the fine grid can smoothly fall into and fill into the notch area in the screen printing process, and good ohmic contact is formed.
Referring to fig. 2, a schematic structural diagram of a target silicon wafer according to an embodiment of the present invention is shown. The target wafer 10 includes a grooved surface 11 and a second surface 12 opposite the grooved surface 11, the grooved surface 11 including a grooved region 111 and an ungrooved region 112. The grooved surface 11 is obtained by performing laser grooving on the first surface of the target silicon wafer 10.
Illustratively, for a tunnel oxide passivation contact solar cell (Tunnel Oxide Passivated Contact solar cell, TOPcon), the number of thin gate lines is 148, the gate line width is 40 μm, the number of grooves for laser grooving the first surface by step S120 is 148, and the groove width is 80 μm.
Step S130, performing boron diffusion treatment on the grooved surface to obtain a target silicon wafer subjected to boron diffusion; the boron-amplified target silicon wafer comprises an emitter layer covered on the surface of the notch, and the emitter layer comprises a P-type heavy doping region and a P-type light doping region.
In the embodiment of the invention, first, a first surface of a target silicon wafer is subjected to laser grooving treatment in step S120, and then, a grooved surface of the laser grooving treatment is subjected to boron diffusion treatment in step S130, so as to obtain a boron-expanded target silicon wafer including an emitter layer.
It should be noted that, by the boron expansion processing in step S130, an emitter layer is formed on the grooved surface, where the emitter layer includes a P-type heavily doped region covering the grooved region on the grooved surface and a P-type lightly doped region covering the non-grooved region on the grooved surface.
Specifically, a target silicon wafer comprising a grooved surface can be subjected to boron diffusion treatment in a diffusion furnace, a diffusion furnace chamber is in a vacuum environment, and a boron source is introduced into the diffusion furnace chamber, so that boron (B) element in the boron source is taken as a doping element to enter the surface layer of the grooved surface, and the surface layer of the grooved surface is converted into an emitter layer, so that the target silicon wafer after boron expansion is obtained.
And performing boron diffusion treatment on the grooved surface to obtain an emitter layer covering the grooved surface, and simultaneously, winding and expanding a boron source to a second surface of the target silicon wafer and forming a winding and expanding emitter layer on the second surface. The wrap-around emitter layer may be removed by a polishing process, which is not described in detail herein.
And step 140, annealing the target silicon wafer subjected to boron expansion to obtain an annealed target silicon wafer.
In the embodiment of the invention, after the target silicon wafer after boron expansion is obtained in step S130, the texture structure in the grooved surface can be repaired to a certain extent by annealing the target silicon wafer after boron expansion, so that the reflectivity of the grooved surface is reduced.
Specifically, the laser grooving process in step S120 may damage the textured structure on the first surface, and in the high temperature diffusion process in step S130, many defects, such as vacancies, interstitial atoms, dislocations, stacking faults, impurity induced defects, etc., may be further formed in the target silicon wafer, in the annealing process in step S140, the textured structure with damaged grooved surface may have a higher surface activity, and may also perform lattice repair by itself in the annealing process, and after the annealing process, the textured structure on the grooved surface may obtain a repair effect of about 50%, and the reflectivity of the grooved surface is reduced.
In the related art, the reflectivity of the first surface of the silicon wafer after the light expansion and the laser grooving treatment is about 12%, and the reflectivity of the first surface of the annealed target silicon wafer obtained after the annealing treatment in the step S140 in the embodiment of the invention can be reduced to 10%.
Step S150, performing secondary boron diffusion treatment on the annealed target silicon wafer to obtain a target silicon wafer subjected to secondary boron diffusion; the target silicon wafer after secondary boron expansion comprises an oxide layer covered on the surface of the notch.
The oxide layer is an oxide layer obtained after the emitter layer is oxidized in the secondary boron diffusion treatment process, and specifically, the oxide layer may be a borosilicate glass layer (BSG). The oxide layer covering the grooved surface may serve to protect the suede structure on the grooved surface from corrosion during the polishing process of the second surface.
Specifically, in the process of performing secondary boron diffusion treatment on the annealed target silicon wafer, air can be introduced into a furnace body in which the annealed target silicon wafer is placed, and the annealed target silicon wafer is subjected to secondary boron diffusion treatment in a certain temperature range, so that an emitter layer reacts with oxygen at a high temperature to generate an oxide layer to cover the surface of the notch.
In the process of performing the secondary boron diffusion treatment on the annealed target silicon wafer, oxygen reacts with the emitter layer to form an oxide layer, and simultaneously reacts with the second surface around-diffusion emitter layer to form a around-diffusion oxide layer. The surrounding oxide layer may be removed by a polishing process, which is not described in detail herein.
And step 160, preparing a target solar cell based on the target silicon wafer subjected to the secondary boron expansion.
In an embodiment of the invention, the target solar cell is a selective emitter (selective emitter, SE) solar cell.
Specifically, the preparing a target solar cell based on the target silicon wafer after the secondary boron expansion in step S160 may include steps S161 to S168:
and step 161, polishing the second surface of the target silicon wafer subjected to secondary boron expansion to obtain a polished second surface.
The polishing treatment is performed on the second surface of the target silicon wafer subjected to secondary boron expansion, so that the surrounding and expanding oxide layer and/or the suede structure on the second surface are removed.
In the process of polishing the second surface, the second surface may be polished with the first alkaline polishing solution to remove the pad oxide layer and/or the textured structure on the second surface. The first alkali polishing solution may include potassium hydroxide, an alkali polishing additive, and deionized water, wherein the ratio of the potassium hydroxide to the first alkali polishing solution is 4% to 6%, the ratio of the alkali polishing additive to the first alkali polishing solution is 1% to 2%, the ratio of the deionized water to the first alkali polishing solution is 90% to 95%, and the sum of the ratios of the potassium hydroxide, the alkali polishing additive, and the deionized water to the first alkali polishing solution is 100%.
It will be appreciated that the temperature and duration of the polishing treatment may be appropriately adjusted based on the ratio of the sodium hydroxide potassium and the alkali polishing additive in the first alkali polishing solution, and the polishing effect of the pad oxide layer and the pad structure on the second surface, so as to remove the pad oxide layer and the pad structure on the second surface. Illustratively, the temperature of the polishing process may be 60 ℃ to 80 ℃, and the duration of the polishing process may be 350s to 500s.
In an embodiment of the invention, the square of the microscopic topography of the polished second surface under the microscope is 6 μm to 8 μm in size.
Step S162, sequentially laminating and preparing a polycrystalline silicon oxide layer and a doped amorphous silicon layer on the polished second surface.
Specifically, a low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD) technique may be used to first prepare a polysilicon oxide layer on the polished second surface, and then prepare a doped amorphous silicon layer on the surface of the polysilicon oxide layer.
The polycrystalline silicon oxide layer and the doped amorphous silicon layer jointly form a passivation contact structure of the second surface in the target silicon wafer, so that the problems of surface recombination and metal contact recombination in the target solar cell are avoided.
And step S163, performing phosphorus diffusion treatment on the doped silicon layer to obtain a phosphorus-diffused target silicon wafer, wherein the phosphorus-diffused target silicon wafer comprises a phosphorus-doped amorphous silicon layer.
The phosphorus doped amorphous silicon layer is obtained by diffusing phosphorus elements into the doped amorphous silicon layer in the phosphorus diffusion treatment process.
Illustratively, the temperature of phosphorus diffusion may be 800 ℃ to 1000 ℃ and the duration of phosphorus diffusion may be 5min to 10min.
In the embodiment of the invention, phosphorus oxychloride can be heated and decomposed in tubular high-temperature heating equipment) And diffusing the phosphorus atoms into the doped amorphous silicon layer to form the phosphorus doped amorphous silicon layer. Under the phosphorus diffusion process condition (the phosphorus diffusion temperature is 800-1000 ℃, the phosphorus diffusion time is 5-10 min), phosphorus atoms are diffused in the doped amorphous silicon layer, and the phosphorus doped amorphous silicon layer is formed.
Wherein, the sheet resistance of the phosphorus doped amorphous silicon layer is 50Ω, and the surface concentration is(grams per cubic centimeter).
After the phosphorus diffusion treatment is performed on the doped silicon layer to obtain the phosphorus doped amorphous silicon layer, a phosphosilicate glass (Phospho Silicate Glass, PSG) layer is also formed on the surface of the phosphorus doped amorphous silicon layer, and needs to be removed by a cleaning operation corresponding to step S164.
Step S164, BOE cleaning is carried out on the target silicon wafer after phosphorus expansion to obtain a cleaned target silicon wafer, wherein the cleaned target silicon wafer comprises a cleaned phosphorus doped amorphous silicon layer and a cleaned grooved surface.
In the embodiment of the invention, BOE (Buffered Oxide Etch, buffer oxide etching liquid) cleaning is carried out on the target silicon wafer after phosphorus expansion, so that a phosphorus-doped amorphous silicon layer, a phosphorus-silicon glass layer and an oxide layer covered on the surface of the etching groove can be removed.
The cleaning solution used to perform the BOE cleaning includes, among other things, potassium hydroxide, a cleaning additive (e.g., BP 65), and deionized water. Wherein the potassium hydroxide is present in the cleaning solution at a ratio of 3.5% to 4.5%, the cleaning additive is present in the cleaning solution at a ratio of 0.4% to 0.5%, the deionized water is present in the cleaning solution at a ratio of 93% to 96%, and the sum of the potassium hydroxide, the cleaning additive, and the deionized water is present in the cleaning solution at a ratio of 100%.
And step S165, performing coating treatment on the cleaned emitter layer to obtain a target silicon wafer after coating treatment, wherein the target silicon wafer after coating treatment comprises an alumina film covered on the surface of the notch after cleaning.
In the embodiment of the invention, an atomic layer deposition (atomic layer deposition, ALD) technology can be adopted to plate a layer of aluminum oxide film on the surface of the cleaned emitter layer. The thickness of the aluminum oxide film is 2nm to 3nm, and the aluminum oxide film can provide negative charge surface field passivation for the target solar cell, so that the photoelectric conversion efficiency of the target solar cell is improved by about 0.3%.
And S166, performing secondary coating treatment on the target silicon wafer subjected to the coating treatment to obtain a target silicon wafer subjected to secondary coating, wherein the target silicon wafer subjected to secondary coating comprises a first silicon nitride film covered on the surface of the aluminum oxide film and a second silicon nitride film covered on the surface of the cleaned phosphorus doped amorphous silicon layer.
Wherein the first silicon nitride film has a thickness of 70nm, a refractive index of 2.09, and the second silicon nitride film has a thickness of 80nm, and a refractive index of 2.12.
Step S167, screen printing is carried out on the target silicon wafer after the secondary coating to obtain a target silicon wafer after the electrode printing, wherein the target silicon wafer after the electrode printing comprises a first electrode printed on the surface of the first silicon nitride film and a second electrode printed on the surface of the second silicon nitride film.
The first electrode and the second electrode may be silver electrodes, and the first electrode and the second electrode are used for collecting current.
Specifically, the first electrode is the positive electrode of the target solar cell, and in the process of printing the first electrode on the surface of the first silicon nitride film, the first electrode needs to be printed on the surface of the first silicon nitride film corresponding to the grooving region in the grooving surface, so that the first electrode can form good ohmic contact with the P-type heavy doping region in the target silicon wafer. The second electrode is used as a cathode of the target solar cell, and in the process of printing the second electrode on the surface of the second silicon nitride film, the second electrode needs to be in contact with the surface of the phosphorus doped amorphous silicon layer.
And step S168, sintering the target silicon wafer after the electrode is printed to obtain the target solar cell.
In the embodiment of the invention, the target silicon wafer after the electrode is printed is sintered, so that silver paste corresponding to the first electrode and the second electrode printed in the step S167 is solidified to form a solidified first electrode and a solidified second electrode.
It should be noted that, after the target silicon wafer after the secondary boron expansion is obtained in step S150, other existing methods for preparing a selective emitter solar cell may be further adopted to prepare the target solar cell based on the target silicon wafer after the secondary boron expansion, which is not particularly limited in the embodiment of the present invention.
In the related art, in the process of preparing a selective emitter solar cell, a textured structure on the surface of a silicon wafer is damaged in the process of laser grooving, so that the reflectivity of the silicon wafer is increased, and the photoelectric conversion efficiency of the solar cell is reduced. In the preparation method of the solar cell provided by the embodiment of the invention, the first surface with the suede structure in the target silicon wafer is firstly grooved to obtain the grooved surface, and then the grooved surface is subjected to boron diffusion treatment to obtain the boron-diffused target silicon wafer comprising the emitter layer; and then, annealing the target silicon wafer subjected to boron expansion to repair the crystal lattice of the texture structure damaged in the grooving process, so that the damage degree of laser grooving to the texture structure on the first surface is reduced. And finally, preparing the target solar cell based on the target silicon wafer subjected to secondary boron expansion obtained by annealing treatment and secondary boron diffusion treatment, so that the damage degree of laser grooving treatment to the textured structure of the surface of the silicon wafer can be reduced while good ohmic contact between the printing electrode and the P-type heavily doped region is ensured, the surface reflectivity of the target silicon wafer subjected to secondary boron expansion is reduced, and the photoelectric conversion efficiency of the target solar cell is improved.
Compared with the related art, the photoelectric conversion efficiency of the target solar cell prepared by the preparation method of the solar cell provided by the embodiment of the invention can be improved by 0.03%, and the current is improved by about 15 mA.
Referring to fig. 3, a step flow chart of another method for manufacturing a solar cell according to an embodiment of the present invention is shown, where the method includes steps S210 to S260:
step S210, obtaining a target silicon wafer; the target silicon wafer is an N-type silicon wafer and comprises a first surface with a textured structure.
In the embodiment of the present invention, the step S210 may correspond to the related description of the step S110, and is not repeated here.
And step S220, carrying out laser grooving treatment on the first surface to obtain a grooved surface.
In the embodiment of the present invention, the step S220 may correspond to the related description of the step S120, and is not repeated here.
Alternatively, the laser grooving process has a grooving width of 70 μm to 90 μm.
In the embodiment of the present invention, the groove width is the width of the groove region in the groove surface.
And step S230, performing boron diffusion treatment on the grooved surface by utilizing a boron source at a first temperature to obtain a target silicon wafer subjected to boron diffusion.
The target silicon wafer after boron expansion comprises an emitter layer covered on the surface of the notch, wherein the emitter layer comprises a P-type heavily doped region and a P-type lightly doped region. The first temperature is 880-920 ℃, the diffusion duration of the boron diffusion treatment is 650-750 s, and the gas flow rate of the boron source is 550-750 sccm (Standard Cubic Centimeter per Minute, standard milliliters per minute).
In the embodiment of the invention, in the process of carrying out boron diffusion treatment on the grooved surface, a boron source is introduced into a diffusion furnace chamber in which a target silicon wafer comprising the grooved surface is placed, the target silicon wafer comprising the grooved surface is maintained at a first temperature, and the boron diffusion treatment is carried out on the grooved surface by utilizing the boron source at the first temperature, so that the target silicon wafer after boron diffusion is obtained.
It will be appreciated that in the case of a boron source gas flow determination, a suitable first temperature may be determined from 880 c to 920 c and a suitable diffusion period from 650s to 750s to achieve the desired boron diffusion effect. Illustratively, in the case where the first temperature is 880 ℃, the diffusion duration may be 750s, which is not particularly limited in the embodiments of the present invention.
And step S240, reducing the temperature of the target silicon wafer subjected to boron expansion from the first temperature to the second temperature according to the target cooling rate to obtain an annealed target silicon wafer.
Wherein the second temperature is 680-720 ℃, and the target cooling rate is 7-13 ℃/min.
In the embodiment of the present invention, after the boron diffusion treatment is performed on the grooved surface by using the boron source at the first temperature in step S230 to obtain the target silicon wafer after the boron diffusion, step S240 may be continuously performed, and the temperature of the target silicon wafer after the boron diffusion is reduced from the first temperature to the second temperature according to the target cooling rate, so as to implement the annealing treatment on the target silicon wafer after the boron diffusion.
Optionally, in the process of annealing the target silicon wafer after boron expansion, the temperature of the target silicon wafer after boron expansion can be reduced from the first temperature to the second temperature within the target cooling time, so that the annealing treatment of the target silicon wafer after boron expansion is realized. The target cooling time period can be any time period between 17min and 23 min.
In the embodiment of the present invention, after the annealed target silicon wafer is obtained in step S240, before the annealed target silicon wafer is subjected to the secondary boron diffusion treatment in step S250, the door of the diffusion furnace may be controlled to be opened, and the annealed target silicon wafer in the diffusion furnace may be taken out, so that the annealed target silicon wafer taken out from the diffusion furnace is subjected to the secondary boron diffusion treatment in step S250.
And S250, performing secondary boron diffusion treatment on the annealed target silicon wafer to obtain the target silicon wafer subjected to secondary boron diffusion.
In the embodiment of the present invention, step S250 may correspond to the related description of step S150, and is not repeated here.
Optionally, the third temperature of the secondary boron diffusion treatment is 950 ℃ to 1100 ℃, the diffusion duration of the secondary boron diffusion treatment is 59min to 61min, and the oxygen inflow rate of the secondary boron diffusion treatment is 1500sccm to 2500sccm.
In the embodiment of the invention, in the process of carrying out secondary boron diffusion treatment on the annealed target silicon wafer, oxygen can be introduced into an oxidation furnace chamber in which the annealed target silicon wafer is placed, the annealed target silicon wafer is maintained at a third temperature, and the target silicon wafer annealed by oxygen is subjected to secondary boron diffusion treatment at the third temperature to obtain the target silicon wafer subjected to secondary boron diffusion.
It can be appreciated that in the embodiment of the present invention, the appropriate second temperature, the diffusion duration of the secondary boron diffusion treatment, and the oxygen gas inflow rate may be determined according to the thickness of the emitter layer covering the grooved surface, respectively. For example, in the case where the thickness of the emitter layer is thicker, the oxygen inflow rate may be appropriately increased, and/or the second temperature may be increased, and/or the diffusion period of the secondary boron diffusion treatment may be prolonged, which is not particularly limited in the embodiment of the present invention.
Optionally, the oxide layer has a thickness of 90nm to 110nm.
The thickness of the oxide layer is the thickness of the oxide layer obtained by oxidizing the emitter layer in step 250, and the thickness of the oxide layer is the same as or similar to the thickness of the emitter layer.
And step S260, preparing a target solar cell based on the target silicon wafer subjected to the secondary boron expansion.
In the embodiment of the present invention, the step S260 may correspond to the related description of the aforementioned step S160, and the description thereof is omitted herein for avoiding repetition.
Optionally, the square resistance of the target silicon wafer after boron expansion is 90 Ω to 130 Ω, and the square resistance of the target silicon wafer after secondary boron expansion is 200 Ω to 240 Ω.
The square resistance is square resistance and refers to the resistance between the edges of the square thin film conductive material.
Optionally, the surface concentration of the target silicon wafer after secondary boron expansion isTo->The junction depth of the target silicon wafer after secondary boron expansion is 0.6-0.7 mu m.
Wherein, the surface concentration (surface concentration) is the concentration of boron element on the grooved surface of the target silicon wafer. The surface concentration of the target silicon wafer after secondary boron expansion isTo->Arbitrary surface concentration in between.
The junction depth of the target silicon wafer after secondary boron expansion is the sum of the thicknesses between the grooved surface of the target silicon wafer and the oxide layer, and is generally measured in units of μm.
Referring to fig. 4, a schematic preparation flow chart of a preparation method of a further solar cell according to an embodiment of the present invention is shown, where the method includes steps S301 to S313:
step S301, obtaining an N-type raw silicon wafer, and performing texturing treatment on the raw silicon wafer to obtain a target silicon wafer; the target silicon wafer is an N-type silicon wafer and comprises a first surface with a suede structure.
Wherein the size of the N-type raw silicon wafer is 182mm multiplied by 183.75mm.
Specifically, a groove type texturing mode is adopted, texturing is carried out on the first surface and the second surface of the original silicon wafer by using a texturing solution, so that the first surface and the second surface can have a textured structure, the temperature of the texturing is 82 ℃, the duration of the texturing is 420s, and the texturing solution comprises sodium hydroxide with the volume ratio of 1.9%, a texturing additive with the volume ratio of 0.58% and deionized water.
Wherein "1" represents a pile structure in the first surface and the second surface.
And step S302, carrying out SE laser grooving treatment on the first surface to obtain a grooved surface.
Wherein the groove depth of the laser groove treatment is 1.4 μm and the groove width of the laser groove treatment is 70 μm to 90 μm.
Wherein "1+2" represents a grooved surface obtained by subjecting the first surface to laser grooving treatment.
In the embodiment of the present invention, step S302 may correspond to the description of step S120, and is not repeated here.
And step S303, performing boron diffusion treatment on the grooved surface to obtain the target silicon wafer after boron diffusion.
The target silicon wafer after boron expansion comprises an emitter layer covered on the surface of the notch, wherein the emitter layer comprises a P-type heavily doped region and a P-type lightly doped region.
Specifically, boron diffusion treatment can be performed on the grooved surface at a first temperature by utilizing a boron source, so as to obtain the target silicon wafer after boron diffusion. Wherein the first temperature is 880-920 ℃, the diffusion duration of the boron diffusion treatment is 650-750 s, and the gas flow of the boron source is 550-750 sccm.
Wherein "3" denotes an emitter layer overlying the grooved surface and a wrap-around emitter layer overlying the textured structure of the second surface.
In the embodiment of the present invention, step S303 may correspond to the descriptions related to step S130 and step S230, and are not repeated here.
And step S304, annealing the target silicon wafer subjected to boron expansion to obtain an annealed target silicon wafer.
Specifically, the temperature of the target silicon wafer subjected to boron expansion is reduced from the first temperature to the second temperature according to the target cooling rate, and the annealed target silicon wafer is obtained. Wherein the second temperature is 680-720 ℃, and the target cooling rate is 7-13 ℃/min.
In the embodiment of the invention, the target silicon wafer after boron expansion is annealed, so that the suede structure in the grooved surface can be repaired to a certain extent, the reflectivity of the grooved surface is reduced, and the light absorptivity of the grooved surface is improved.
In the embodiment of the present invention, step S304 may correspond to the descriptions related to step S140 and step S240, and is not repeated here.
And step S305, performing secondary boron diffusion treatment on the annealed target silicon wafer to obtain the target silicon wafer subjected to secondary boron diffusion.
The target silicon wafer after secondary boron expansion comprises an oxide layer '3+5' covering the surface of the notch groove, which means an oxide layer covering the surface of the notch groove and a surrounding expansion oxide layer covering the suede structure of the second surface.
The third temperature of the secondary boron diffusion treatment is 950-1100 ℃, the diffusion duration of the secondary boron diffusion treatment is 59-61 min, and the oxygen inlet flow rate of the secondary boron diffusion treatment is 1500-2500 sccm.
The thickness of the oxide layer is 90nm to 110nm.
The square resistance of the target silicon wafer after boron expansion is 90 to 130 omega, and the square resistance of the target silicon wafer after secondary boron expansion is 200 to 240 omega.
The surface concentration of the target silicon wafer after secondary boron expansion is To->The junction depth of the target silicon wafer after secondary boron expansion is 0.6-0.7 mu m.
In the embodiment of the present invention, the step S305 may correspond to the descriptions related to the steps S150 and S250, and will not be repeated here.
And step S306, polishing the second surface of the target silicon wafer subjected to secondary boron expansion to obtain a polished second surface.
Specifically, the second surface may be polished with the first alkaline polishing solution at a polishing temperature of 70 ℃ for a polishing period of 420s to remove the pad-around oxide layer and the textured structure on the second surface. The first alkali polishing solution may include potassium hydroxide, an alkali polishing additive and deionized water, wherein the ratio of the potassium hydroxide to the first alkali polishing solution is 5.6%, the ratio of the alkali polishing additive to the first alkali polishing solution is 1.2%, and the deionized water.
In the embodiment of the present invention, step S306 may correspond to the description of step S161, and is not repeated here.
Step S307, sequentially laminating and preparing a polycrystalline silicon oxide layer and a doped amorphous silicon layer on the polished second surface.
Where "6" represents a polycrystalline silicon oxide layer and "7" represents a doped amorphous silicon layer.
In the embodiment of the present invention, step S307 may correspond to the related description of step S162, and is not repeated here for avoiding repetition.
And step 308, performing phosphorus diffusion treatment on the doped silicon layer to obtain a phosphorus-diffused target silicon wafer, wherein the phosphorus-diffused target silicon wafer comprises a phosphorus-doped amorphous silicon layer.
Wherein the phosphorus diffusion temperature is 850 ℃, and the phosphorus diffusion time is 7min. The sheet resistance of the phosphorus doped amorphous silicon layer is 50Ω, and the surface concentration is。
The phosphorus doped amorphous silicon layer is obtained by diffusing phosphorus elements into the doped amorphous silicon layer in the phosphorus diffusion treatment process.
After the phosphorus diffusion treatment is performed on the doped silicon layer to obtain the phosphorus doped amorphous silicon layer, a phosphosilicate glass layer is further formed on the surface of the phosphorus doped amorphous silicon layer, and the phosphosilicate glass layer needs to be removed through a cleaning operation corresponding to step S309.
"7" means a phosphorus doped amorphous silicon layer and "8" means a phosphosilicate glass layer.
In the embodiment of the present invention, step S308 may correspond to the related description of step S163, and is not repeated here.
Step S309, BOE cleaning is carried out on the target silicon wafer after phosphorus expansion to obtain a cleaned target silicon wafer, wherein the cleaned target silicon wafer comprises a cleaned phosphorus doped amorphous silicon layer and a cleaned grooved surface.
Specifically, BOE cleaning can be performed on the target silicon wafer after phosphorus expansion by adopting a cleaning solution with the temperature of 80 ℃ for 280 seconds. Wherein the cleaning solution may include potassium hydroxide, a cleaning additive, and deionized water, wherein the potassium hydroxide is present in the cleaning solution at a ratio of 4.1%, the alkaline polishing additive is present in the cleaning solution at a ratio of 0.45%, and deionized water.
In the embodiment of the present invention, step S309 may correspond to the related description of step S164, and is not repeated here.
And step S310, performing coating treatment on the cleaned emitter layer to obtain a target silicon wafer after coating treatment, wherein the target silicon wafer after coating treatment comprises an alumina film covered on the surface of the notch after cleaning.
Wherein "9" represents an alumina thin film.
In the embodiment of the present invention, step S310 may correspond to the related description of step S165, and is not repeated here.
And step S311, performing secondary coating treatment on the target silicon wafer subjected to the coating treatment to obtain a target silicon wafer subjected to secondary coating, wherein the target silicon wafer subjected to secondary coating comprises a first silicon nitride film covered on the surface of the aluminum oxide film and a second silicon nitride film covered on the surface of the cleaned phosphorus doped amorphous silicon layer.
Wherein "10" represents a first silicon nitride film covering the surface of the aluminum oxide film and a second silicon nitride film covering the surface of the phosphorus-doped amorphous silicon layer after cleaning.
In the embodiment of the present invention, step S311 may correspond to the related description of step S166, and is not repeated here.
And step S312, performing screen printing on the target silicon wafer after the secondary coating to obtain a target silicon wafer after the electrode printing, wherein the target silicon wafer after the electrode printing comprises a first electrode printed on the surface of the first silicon nitride film and a second electrode printed on the surface of the second silicon nitride film.
Wherein "11" represents a first electrode printed on the surface of the first silicon nitride film and a second electrode printed on the surface of the second silicon nitride film.
In the embodiment of the present invention, step S312 may correspond to the related description of step S167, and is not repeated here for avoiding repetition.
And step S313, sintering the target silicon wafer after the electrode is printed to obtain the target solar cell.
In the embodiment of the invention, the target silicon wafer after the electrode is printed is sintered, so that silver paste corresponding to the first electrode and the second electrode printed in the step S167 is solidified to form a solidified first electrode and a solidified second electrode.
In the embodiment of the present invention, step S313 may correspond to the related description of step S168, and is not repeated here for avoiding repetition.
In summary, in the method for manufacturing a solar cell provided by the embodiment of the present invention, a first surface having a textured structure in a target silicon wafer is first grooved to obtain a grooved surface, and then boron diffusion treatment is performed on the grooved surface to obtain a boron-expanded target silicon wafer including an emitter layer; and then, annealing the target silicon wafer subjected to boron expansion to repair the crystal lattice of the texture structure damaged in the grooving process, so that the damage degree of laser grooving to the texture structure on the first surface is reduced. And finally, preparing the target solar cell based on the target silicon wafer subjected to secondary boron expansion obtained by annealing treatment and secondary boron diffusion treatment, so that the damage degree of laser grooving treatment to the textured structure of the surface of the silicon wafer can be reduced while good ohmic contact between the printing electrode and the P-type heavily doped region is ensured, the surface reflectivity of the target silicon wafer subjected to secondary boron expansion is reduced, and the photoelectric conversion efficiency of the target solar cell is improved. Compared with the related art, the photoelectric conversion efficiency of the target solar cell prepared by the preparation method of the solar cell provided by the embodiment of the invention can be improved by 0.03%, and the current is improved by about 15 mA.
The embodiment of the invention also provides a solar cell, which is prepared by adopting the preparation method of the solar cell.
The embodiment of the invention also provides electric equipment, which comprises the solar battery, wherein the solar battery is used as a power supply of the electric equipment.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) comprising instructions for causing a terminal (which may be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to perform the method according to the embodiments of the present invention.
The embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present invention and the scope of the claims, which are to be protected by the present invention.

Claims (10)

1. A method of manufacturing a solar cell, the method comprising:
obtaining a target silicon wafer; the target silicon wafer is an N-type silicon wafer and comprises a first surface with a suede structure;
carrying out laser grooving treatment on the first surface to obtain a grooved surface;
performing boron diffusion treatment on the grooved surface to obtain a target silicon wafer subjected to boron diffusion; the boron-amplified target silicon wafer comprises an emitter layer covered on the surface of the notch, wherein the emitter layer comprises a P-type heavy doping region and a P-type light doping region;
annealing the target silicon wafer subjected to boron expansion to obtain an annealed target silicon wafer;
performing secondary boron diffusion treatment on the annealed target silicon wafer to obtain a target silicon wafer subjected to secondary boron diffusion; the target silicon wafer subjected to secondary boron expansion comprises an oxide layer covered on the surface of the notch;
And preparing the target solar cell based on the target silicon wafer subjected to secondary boron expansion.
2. The method of claim 1, wherein the performing boron diffusion treatment on the grooved surface to obtain a target silicon wafer after boron diffusion comprises:
performing boron diffusion treatment on the grooved surface by utilizing a boron source at a first temperature to obtain a target silicon wafer subjected to boron diffusion;
wherein the first temperature is 880-920 ℃, the diffusion duration of the boron diffusion treatment is 650-750 s, and the gas flow of the boron source is 550-750 sccm.
3. The method according to claim 1, wherein the laser grooving process has a grooving width of 70 μm to 90 μm.
4. The method of claim 1, wherein the annealing the boron-amplified target silicon wafer to obtain an annealed target silicon wafer comprises:
reducing the temperature of the target silicon wafer subjected to boron expansion from the first temperature to the second temperature according to the target cooling rate to obtain an annealed target silicon wafer;
wherein the second temperature is 680-720 ℃, and the target cooling rate is 7-13 ℃/min.
5. The method according to claim 1, wherein the third temperature of the secondary boron diffusion treatment is 950 ℃ to 1100 ℃, the diffusion duration of the secondary boron diffusion treatment is 59min to 61min, and the oxygen inflow rate of the secondary boron diffusion treatment is 1500sccm to 2500sccm.
6. The method of claim 1, wherein the oxide layer has a thickness of 90nm to 110nm.
7. The method of claim 1, wherein the target silicon wafer after boron expansion has a sheet resistance of 90 Ω to 130 Ω, and the target silicon wafer after secondary boron expansion has a sheet resistance of 200 Ω to 240 Ω.
8. The method according to claim 1, wherein the surface concentration of the target silicon wafer after the secondary boron expansion isTo->The junction depth of the target silicon wafer after secondary boron expansion is 0.6-0.7 mu m.
9. A solar cell, characterized in that the solar cell is produced by the production method of the solar cell according to any one of claims 1 to 8.
10. A powered device comprising the solar cell of claim 9 as a power supply for the powered device.
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