CN115036391A - Preparation method of N-type solar cell with selective emitter and cell - Google Patents
Preparation method of N-type solar cell with selective emitter and cell Download PDFInfo
- Publication number
- CN115036391A CN115036391A CN202210729584.0A CN202210729584A CN115036391A CN 115036391 A CN115036391 A CN 115036391A CN 202210729584 A CN202210729584 A CN 202210729584A CN 115036391 A CN115036391 A CN 115036391A
- Authority
- CN
- China
- Prior art keywords
- layer
- silicon wafer
- diffusion
- boron
- front surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 76
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 76
- 239000010703 silicon Substances 0.000 claims abstract description 76
- 238000009792 diffusion process Methods 0.000 claims abstract description 71
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 41
- 229910052796 boron Inorganic materials 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 claims abstract description 36
- 238000000151 deposition Methods 0.000 claims abstract description 35
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 29
- 238000004140 cleaning Methods 0.000 claims abstract description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 17
- 230000005641 tunneling Effects 0.000 claims abstract description 17
- 229920005591 polysilicon Polymers 0.000 claims abstract description 10
- 238000002161 passivation Methods 0.000 claims description 20
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 16
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 14
- ILAHWRKJUDSMFH-UHFFFAOYSA-N boron tribromide Chemical compound BrB(Br)Br ILAHWRKJUDSMFH-UHFFFAOYSA-N 0.000 claims description 12
- 230000008021 deposition Effects 0.000 claims description 12
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 9
- 230000003647 oxidation Effects 0.000 claims description 9
- 238000007254 oxidation reaction Methods 0.000 claims description 9
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 claims description 6
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 3
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 3
- 229910020286 SiOxNy Inorganic materials 0.000 claims description 3
- 229910017604 nitric acid Inorganic materials 0.000 claims description 3
- 239000003054 catalyst Substances 0.000 claims description 2
- 238000007781 pre-processing Methods 0.000 claims description 2
- 238000000137 annealing Methods 0.000 abstract description 8
- 238000002425 crystallisation Methods 0.000 abstract description 6
- 230000008025 crystallization Effects 0.000 abstract description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- 229910004205 SiNX Inorganic materials 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- 230000000052 comparative effect Effects 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 238000011065 in-situ storage Methods 0.000 description 5
- 238000005498 polishing Methods 0.000 description 5
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000005215 recombination Methods 0.000 description 3
- 230000006798 recombination Effects 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 239000005388 borosilicate glass Substances 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- VZSRBBMJRBPUNF-UHFFFAOYSA-N 2-(2,3-dihydro-1H-inden-2-ylamino)-N-[3-oxo-3-(2,4,6,7-tetrahydrotriazolo[4,5-c]pyridin-5-yl)propyl]pyrimidine-5-carboxamide Chemical compound C1C(CC2=CC=CC=C12)NC1=NC=C(C=N1)C(=O)NCCC(N1CC2=C(CC1)NN=N2)=O VZSRBBMJRBPUNF-UHFFFAOYSA-N 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000011056 performance test Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000004804 winding Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
- H01L31/182—Special manufacturing methods for polycrystalline Si, e.g. Si ribbon, poly Si ingots, thin films of polycrystalline Si
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
- H01L31/1872—Recrystallisation
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Life Sciences & Earth Sciences (AREA)
- Sustainable Development (AREA)
- Photovoltaic Devices (AREA)
Abstract
The invention relates to a preparation method of an N-type solar cell with a selective emitter and a cell, wherein the method comprises the following steps: (1) pre-treating; (2) carrying out first boron diffusion on the front surface of the silicon wafer to form a whole-surface re-diffusion area; (3) growing a tunneling oxide layer, depositing a heavily doped amorphous silicon layer and a mask layer on the back of the silicon wafer in sequence; (4) removing the polysilicon wound and plated on the front surface, and reserving a BSG layer with a preset thickness; (5) laser grooving is carried out on the non-grid line area on the front side of the silicon wafer, and the non-grid line area re-expansion area is removed; (6) performing laser grooving, cleaning and texturing on the front side of the silicon wafer; (7) performing secondary boron diffusion on the front surface of the silicon wafer, forming a light diffusion area at the laser grooving position, and simultaneously realizing crystallization of the amorphous silicon layer; (8) removing the BSG layer and the back mask layer on the front side and the back side of the silicon wafer; wherein the junction depth of the heavy expansion region is greater than that of the light expansion region, and the sheet resistance of the heavy expansion region is less than that of the light expansion region. The method provided by the invention does not need to prepare a mask on the front side, and the amorphous silicon layer is crystallized without high-temperature annealing, thereby simplifying the process flow.
Description
Technical Field
The invention belongs to the field of solar cells, and particularly relates to a preparation method of an N-type solar cell with a selective emitter and a cell.
Background
The selective emitter is a structure which can ensure contact and reduce recombination to the maximum extent by heavily doping in an electrode contact area and lightly doping between electrodes, so that the efficiency of the solar cell is greatly improved. At present, the preparation method of the boron selective emitter for the N-type battery mainly comprises the following steps: (1) laser SE method: after diffusion, laser propulsion is directly carried out on the corresponding area of the electrode to realize heavy doping, and the area without laser is not used to realize light doping. Because the BSG layer is thick enough after diffusion, the promotion of boron in BSG is difficult to control by laser, and the silicon wafer is damaged greatly by overhigh laser energy; (2) according to the secondary boron diffusion and mask method, light doping is firstly carried out, a mask needs to be added to protect a light doping area, then a place needing heavy doping is damaged through laser, then secondary boron diffusion is carried out for heavy doping, a mask layer needs to be additionally added, the related processes are more, and the production cost is higher.
Disclosure of Invention
The invention aims to provide a preparation method of an N-type solar cell with a selective emitter and the cell, which maximally simplifies the process flow and reduces the production cost compared with the existing process of a secondary boron diffusion and mask method.
In order to achieve the purpose, the invention adopts the technical scheme that:
a preparation method of an N-type solar cell with a selective emitter comprises the following steps:
(1) preprocessing an N-type silicon wafer;
(2) performing first boron diffusion on the front surface of the silicon wafer to form a whole-surface re-diffusion area;
(3) growing a tunneling oxide layer, depositing a heavily doped amorphous silicon layer and a mask layer on the back of the silicon wafer in sequence;
(4) removing the polysilicon wound and plated on the front surface, and reserving a BSG layer with a preset thickness;
(5) carrying out laser grooving on a non-grid line region on the front side of the silicon wafer, and removing a re-expansion region of the non-grid line region;
(6) cleaning and texturing the laser grooving position on the front side of the silicon wafer;
(7) performing boron diffusion on the front side of the silicon wafer for the second time, forming a light diffusion area at the laser grooving position, and simultaneously realizing crystallization of the amorphous silicon layer to obtain a doped polycrystalline silicon layer;
(8) removing the BSG layer on the front surface and the back surface of the silicon wafer and the mask layer on the back surface;
in the step (7), the junction depth of the heavy expansion region is greater than that of the light expansion region, and the sheet resistance of the heavy expansion region is less than that of the light expansion region.
Preferably, in the step (2), the boron source for the first boron diffusion is boron tribromide or boron trichloride, the diffusion temperature is 950-.
Preferably, in the step (2), after the first boron diffusion, the thickness of the BSG layer is 80-300 nm.
Preferably, in the step (2), the predetermined thickness of the BSG layer remained is 50 to 200 nm.
Preferably, in the step (7), the boron source for the second boron diffusion is boron tribromide or boron trichloride, the diffusion temperature is 850-.
Preferably, in the step (3), when the amorphous silicon layer is deposited: the deposition temperature is 350-500 ℃, and the intrinsic layer is SiH 4 The flow rate of (1) is 500-2500 sccm, and a heavily doped layer SiH 4 The flow rate of (2) is 500-2500 sccm, PH 3 The flow rate of the catalyst is 500sccm to 4000 sccm.
Preferably, in the step (3), the mask layer is made of SiO 2 、SiN X Combinations of one or more of SiOxNy; the thickness of the mask layer is 30-150 nm; the preparation method of the tunneling oxide layer comprises a high-temperature thermal oxidation method, a PECVD (plasma enhanced chemical vapor deposition), a thermal nitric acid oxidation method or an ozone oxidation method; the preparation methods of the amorphous silicon layer and the mask layer are both PECVD.
Preferably, after the step (8), the following steps are further included:
(9) depositing a front passivation layer on the front surface of the silicon wafer; depositing a back passivation layer on the back of the silicon wafer;
(10) and preparing metal electrodes on the front surface and the back surface of the silicon wafer.
Another object of the present invention is to provide a solar cell prepared by the above preparation method.
Due to the application of the technical scheme, compared with the prior art, the invention has the following advantages: according to the preparation method of the N-type solar cell with the selective emitter, provided by the invention, a mask is not required to be prepared on the front surface, a high-temperature annealing step is not required for crystallization of the amorphous silicon layer, a heavy expansion region is formed firstly, then a light expansion region is formed, and an SE structure is realized through laser and secondary boron expansion; the N-type solar cell with the selective emitter prepared by the preparation method provided by the invention has deep junction of the re-expansion region, low sheet resistance and low contact resistance, namely, the metal semiconductor can form better contact; the light diffusion region has shallow junction, high sheet resistance, low recombination rate and good short-wave response, and shows that the open-circuit voltage, the short-circuit current and the filling factor of the battery are all improved, and finally the conversion efficiency of the battery is improved.
Drawings
Fig. 1 is a schematic diagram of the cell structure of the N-type solar cell with a selective emitter according to the present invention after the preparation step (1);
fig. 2 is a schematic diagram of the cell structure after the step (2) of preparing the N-type solar cell with the selective emitter according to the present invention;
fig. 3 is a schematic diagram of the cell structure after the step (3) of manufacturing the N-type solar cell with the selective emitter according to the present invention;
fig. 4 is a schematic diagram of the cell structure after the step (7) of manufacturing the N-type solar cell with selective emitter according to the present invention;
fig. 5 is a schematic diagram of the cell structure after the step (9) of manufacturing the N-type solar cell with selective emitter according to the present invention;
fig. 6 is a schematic diagram of the cell structure after the step (10) of manufacturing the N-type solar cell with the selective emitter according to the present invention.
In the above drawings:
the manufacturing method comprises the following steps of 1-N type silicon chip, 21-emitter heavily-doped region, 22-emitter lightly-doped region, 3-tunneling oxide layer, 4-doped polycrystalline silicon layer, 5-mask layer, 61-aluminum oxide layer, 62-silicon nitride layer, 7-back passivation layer, 8-front metal electrode and 9-back metal electrode.
Detailed Description
The invention will be further described with reference to examples of embodiments shown in the drawings to which the invention is attached.
A method for preparing an N-type solar cell with a selective emitter, comprising the following steps:
(1) pretreating an N-type silicon wafer 1, wherein the pretreatment comprises cleaning and texturing, and the N-type silicon wafer 1 is shown in figure 1;
(2) performing primary boron diffusion on the surface of one side of the silicon wafer 1 to serve as the front surface of a silicon substrate to form whole-surface re-diffusion, wherein the boron source of the primary boron diffusion is boron tribromide or boron trichloride, the diffusion temperature is 950-1100 ℃, the junction depth after diffusion is 0.8-2.5 mu m, and the sheet resistance is 50-180 omega/sqr;
(3) growing an ultrathin tunneling oxide layer 3, depositing a heavily doped amorphous silicon layer and a mask layer 5 on the back surface of a silicon wafer 1 in sequence, specifically, etching and polishing the back surface of the silicon wafer 1, growing the ultrathin tunneling oxide layer 3 in situ by PECVD, and depositing the heavily doped amorphous silicon layer and the mask layer 5, wherein the deposition temperature is 350-500 ℃, and the deposition temperature is SiH of an intrinsic layer 4 The flow rate of (1) is 500-2500 sccm, and a heavily doped layer SiH 4 The flow rate of (2) is 500-2500 sccm, and the pH value is 3 The flow rate of (2) is 500 to 4000 sccm. The mask layer 5 is used for protecting the tunneling oxide layer 3 and the heavily doped amorphous silicon layer.
The tunneling oxide layer 3 is made of SiO 2 The preparation method of the tunneling oxide layer 3 includes a high-temperature thermal oxidation method, a PECVD, a thermal nitric acid oxidation method, or an ozone oxidation method. The mask layer is made of SiO 2 、SiN X And SiOxNy, the amorphous silicon layer and the mask layer are prepared by PECVD, and the thickness of the mask layer is 30-150 nm.
(4) Removing the polysilicon on the front surface in the winding plating process, and reserving a BSG layer with a preset thickness, namely not completely clearing the BSG layer, wherein the purpose of reserving part of the BSG layer is to protect a re-expansion area at the grid line in the cleaning process of the following step (6);
(5) carrying out laser grooving on a non-grid line region on the front surface of the silicon wafer 1, and removing a re-expansion region of the non-grid line region, wherein the laser wavelength in the laser grooving is 532 nm;
(6) cleaning and texturing the laser grooving position on the front side of the silicon wafer 1;
(7) performing second boron diffusion on the front surface of the silicon wafer 1 to form a light diffusion area at the laser grooving position, wherein in the second boron diffusion, a boron source is boron tribromide or boron trichloride, the diffusion temperature is 850-1000 ℃, the junction depth after diffusion is 0.3-0.6 mu m, and the sheet resistance is 150-300 omega/sqr; in the second boron diffusion process, the crystallization of amorphous silicon is realized at the same time, and a doped polycrystalline silicon layer 4 is formed;
(8) removing the BSG layer and the mask layer on the front side and the back side of the silicon wafer 1;
(9) depositing a front passivation layer on the front surface of the silicon wafer 1, and depositing a back passivation layer on the back surface of the silicon wafer 1, wherein the front passivation layer is a dielectric layer formed by stacking one or more of a silicon dioxide layer, an aluminum oxide layer and a silicon nitride layer, and when the number of the front passivation layer is multiple, two or three of the silicon oxide layer, the aluminum oxide layer and the silicon nitride layer are stacked, and the stacking has no sequential requirement; the front passivation layer is a dielectric layer formed by stacking one or more of a silicon dioxide layer, an aluminum oxide layer and a silicon nitride layer, and when the number of the layers is multiple, two or three of the silicon oxide layer, the aluminum oxide layer and the silicon nitride layer are stacked, so that the stacking has no sequential requirement.
(10) And preparing metal electrodes on the front surface and the back surface of the silicon wafer 1.
In this example, the junction depth of the heavy expansion region in the step (2) is greater than that of the light expansion region in the step (7), and the sheet resistance of the heavy expansion region in the step (2) is less than that of the light expansion region in the step (7).
In this example, in the step (2), the front surface of the silicon wafer is heavily doped first, so that a front surface amount and a mask are not needed, and the heavily doped BSG layer can be used as the mask, namely, the step of adding the mask layer on the front surface is reduced; in the step (7), the light doping cannot be continuously promoted in the heavily doped region due to the lower temperature, so that the heavily doped region is not influenced.
In the existing secondary boron diffusion and mask method, a structure of a tunneling oxide layer and a polycrystalline silicon layer is required to be obtained on the back surface of a silicon wafer, the polycrystalline silicon layer is converted into a polycrystalline silicon layer through deposition of an amorphous silicon layer and then annealing, and an additional step of high-temperature annealing is required in the conversion process, namely, the high-temperature annealing is performed after the deposition of the tunneling oxide layer and the amorphous silicon layer is finished. In this embodiment, in the step (7), the crystallization of the amorphous silicon is simultaneously realized in the secondary boron diffusion process to form the doped polysilicon layer 4, so that a high-temperature annealing step can be omitted.
The preparation method of the N-type solar cell with the selective emitter provided by the embodiment has the advantages that a mask layer is not required to be arranged on the front surface, a high-temperature annealing step is omitted, the SE structure is realized through laser and secondary boron diffusion, and compared with the existing process of the secondary boron diffusion and the mask method, the process flow is simplified to the greatest extent.
The above scheme is further illustrated below with reference to specific examples and comparative examples:
example 1
Step 1: cleaning and texturing an N-type silicon wafer 1;
step 2: performing primary boron diffusion on the surface of one side of the silicon wafer 1 to form the whole-surface re-diffusion, wherein the diffusion temperature is 1050 ℃, the diffusion junction depth is 1.1 mu m, the sheet resistance is 130 omega/sqr, and the thickness of a BSG layer is 150 nm;
and step 3: etching and polishing the back of a silicon wafer 1, growing an ultrathin tunneling oxide layer 3 in situ by PECVD, and depositing a heavily doped amorphous silicon layer and SiO 2 A mask layer, wherein the deposition temperature for depositing the amorphous silicon layer is 450 deg.C, and the intrinsic layer is SiH 4 The flow rate of (1) is 1500sccm, and a layer SiH is heavily doped 4 At a flow rate of 2000sccm, PH 3 The flow rate is 3000 sccm; SiO 2 2 The thickness of the mask layer is 100 nm;
and 4, step 4: cleaning and removing the polysilicon wound and plated on the front surface, and reserving the BSG layer on the front surface for 100 nm;
and 5: carrying out laser grooving on the non-grid line region on the front surface of the silicon wafer 1, wherein the laser wavelength is 532nm, and removing the re-expansion region of the non-grid line region;
step 6: carrying out secondary cleaning and texturing on the laser grooving position;
and 7: performing secondary boron diffusion on the front surface of the silicon wafer 1, forming light diffusion at a laser grooving position, wherein the diffusion temperature is 930 ℃, the diffusion junction depth is 0.6 mu m, and the sheet resistance is 220 omega/sqr, so as to obtain an emitter heavily-doped region 21 and an emitter lightly-doped region 22;
and 8: cleaning, and removing BSG (borosilicate glass layer) and mask layers on the front surface and the back surface of the silicon wafer 1;
and step 9: depositing on the front surface of the silicon wafer 1Alumina layer 61 (Al) 2 O 3 ) And a silicon nitride layer 62 (SiNx); depositing a back passivation layer 7 on the back surface of the silicon wafer 1, wherein the back passivation layer 7 is made of SiNx;
step 10: a front metal electrode 8 and a back metal electrode 9 are prepared on the front and back, respectively.
Example 2
Step 1: cleaning and texturing an N-type silicon wafer 1;
and 2, step: performing primary boron diffusion on the surface of one side of the silicon wafer 1 to form a whole-surface re-diffusion, wherein the diffusion temperature is 1000 ℃, the diffusion junction depth is 1.0 mu m, the sheet resistance is 150 omega/sqr, and the thickness of a BSG layer is 100 nm;
and step 3: firstly, etching and polishing the back of a silicon wafer 1; then, an ultrathin tunneling oxide layer 3 is grown in situ through PECVD, and an amorphous silicon layer and SiO are deposited 2 And (5) masking the layer. The deposition temperature of the amorphous silicon layer is 400 ℃, and the deposition temperature of the intrinsic layer is SiH 4 Flow rate of 2000sccm, heavily doped layer SiH 4 Flow rate 2000sccm, PH 3 The flow rate was 2000 sccm. SiO 2 2 The thickness of the mask layer is 100 nm;
and 4, step 4: cleaning to remove the polysilicon on the front surface, and reserving the BSG layer on the front surface for 50 nm;
and 5: carrying out laser grooving on the non-grid line area on the front side of the silicon wafer 1, wherein the laser wavelength is 532nm, and removing the re-expansion area of the non-grid line area;
step 6: carrying out secondary cleaning and texturing on the laser grooving position;
and 7: performing secondary boron diffusion on the front surface of the silicon wafer 1, forming light diffusion at a laser grooving position, wherein the diffusion temperature is 910 ℃, the diffusion junction depth is 0.5 mu m, and the sheet resistance is 230 omega/sqr, so as to obtain an emitter heavily-doped region 21 and an emitter lightly-doped region 22;
and step 8: cleaning, and removing BSG (borosilicate glass layer) and mask layers on the front surface and the back surface of the silicon wafer 1;
and step 9: depositing an alumina layer 61 (Al) on the front surface of the silicon wafer 1 2 O 3 ) And a silicon nitride layer 62 (SiNx); depositing a back passivation layer 7 on the back surface of the silicon wafer 1, wherein the back passivation layer 7 is made of SiNx;
step 10: a front metal electrode 8 and a back metal electrode 9 are prepared on the front and back sides, respectively.
Example 3
Step 1: cleaning and texturing an N-type 1 silicon wafer 1;
step 2: performing primary boron diffusion on the surface of one side of the silicon wafer 1 to form the whole-surface re-diffusion, wherein the diffusion temperature is 1000 ℃, the diffusion junction depth is 1.0 mu m, the sheet resistance is 150 omega/sqr, and the thickness of a BSG layer is 100 nm;
and step 3: etching and polishing the back of a silicon wafer 1, growing an ultrathin tunneling oxide layer 3 in situ by PECVD, and depositing an amorphous silicon layer 6 and SiO 2 A mask layer, wherein the deposition temperature of the deposited amorphous silicon layer is 400 ℃, and the deposition temperature of the intrinsic layer is SiH 4 The flow rate of (1) is 2000sccm, and a layer of SiH is heavily doped 4 At a flow rate of 2000sccm, PH 3 At a flow rate of 2000sccm, SiO 2 The thickness of the mask layer is 100 nm;
and 4, step 4: cleaning to remove the polysilicon on the front surface, and reserving the BSG layer on the front surface for 50 nm;
and 5: carrying out laser grooving on the non-grid line region on the front surface of the silicon wafer 1, wherein the laser wavelength is 532nm, and removing the re-expansion region of the non-grid line region;
step 6: carrying out secondary cleaning and texturing on the laser grooving position;
and 7: performing secondary boron diffusion on the front surface of the silicon wafer 1, forming light diffusion at a laser grooving position, wherein the diffusion temperature is 900 ℃, the diffusion junction depth is 0.45 mu m, and the sheet resistance is 240 omega/sqr, and thus an emitter heavily-doped region 21 and an emitter lightly-doped region 22 are obtained;
and 8: cleaning, and removing BSG (boron silicate glass) layers and mask layers on the front surface and the back surface of the silicon wafer 1;
and step 9: depositing an alumina layer 61 (Al) on the front surface of the silicon wafer 1 2 O 3 ) And a silicon nitride layer 62 (SiNx); depositing a back passivation layer 7 on the back surface of the silicon wafer 1, wherein the back passivation layer 7 is made of SiNx;
step 10: a front metal electrode 8 and a back metal electrode 9 are prepared on the front and back sides, respectively.
Comparative example
In contrast to examples 1-3, N-type solar cells without SE were prepared.
Step 1: cleaning and texturing an N-type silicon wafer 1;
and 2, step: performing boron diffusion on the surface of one side of the silicon wafer 1 to serve as the front surface of the silicon wafer 1, wherein the diffusion temperature is 1000 ℃, the diffusion junction depth is 1.0 mu m, the sheet resistance is 150 omega/sqr, and the thickness of a BSG layer is 100 nm;
and step 3: etching and polishing the back of the silicon wafer 1; growing an ultrathin tunneling oxide layer in situ by PECVD (plasma enhanced chemical vapor deposition), and depositing a heavily doped amorphous silicon layer; the deposition temperature of the amorphous silicon layer was 450 deg.C and the intrinsic layer SiH 4 The flow rate of (1) is 1500sccm, and a layer SiH is heavily doped 4 The flow rate of (2) is 2000sccm, PH 3 The flow rate is 3000 sccm;
and 4, step 4: annealing at 700 ℃ to realize crystallization of the amorphous silicon layer;
step 5: cleaning and removing the polysilicon wound and plated on the front surface and the BSG layer on the front surface;
step 6: depositing a passivation anti-reflection film layer (Al) on the front surface of a silicon wafer 2 O 3 ) And a silicon nitride layer (SiNx); depositing a passivation film SiNx on the back of the silicon wafer;
and 7: and preparing a front metal electrode and a back metal electrode on the front surface and the back surface respectively.
The cells prepared according to the methods of preparation of the passivated contact cells of examples 1 to 3 and comparative example were subjected to the relevant electrochemical performance tests, which were: the test was carried out using a conventional Halm tester under standard test conditions (25 ℃, 1000w/m 2). The test results are shown in Table 1.
Table 1 results of electrical property tests of passivated contact cells prepared in examples 1 to 3 and comparative example
| Eta | Uoc | Isc | FF | |
| Example 1 | 1 | 1 | 1 | 1 |
| Example 2 | +1.39％ | +0.71％ | +0.23％ | +0.44％ |
| Example 3 | +1.55％ | +0.85％ | +0.21％ | +0.48％ |
| Comparative example | +1.42％ | +0.78％ | +0.20％ | +0.43％ |
In table 1, + represents: the Eta, Uoc, Isc and FF of the passivated contact cells prepared in examples 1 to 3 increased relative to the Eta, Uoc, Isc and FF of the passivated contact cells prepared in comparative example, as + 1.39% in the Eta of example 2 indicating an increase of 1.39% in comparative example.
Referring to fig. 6, the invention further provides an N-type solar cell with a selective emitter, which includes an N-type silicon wafer 1, wherein a front passivation layer 6, an emitter heavily doped region 21, and an emitter lightly doped region 22 are disposed on the front surface of the N-type silicon wafer 1, and a tunneling oxide layer 3, a doped polysilicon layer 4, a back passivation layer 7, and a back metal electrode 9 are sequentially disposed on the back surface of the N-type silicon wafer 1 from inside to outside.
The N-type solar cell with the selective emitter prepared by the preparation method provided by the invention has deep junction of the re-expansion region, low sheet resistance and low contact resistance, namely, a metal semiconductor can form better contact; the light diffusion region has shallow junction, high sheet resistance, low recombination rate and good short-wave response, and shows that the open-circuit voltage, the short-circuit current and the filling factor of the battery are all improved, and finally the conversion efficiency of the battery is improved.
The above embodiments are merely illustrative of the technical ideas and features of the present invention, and the purpose thereof is to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and not to limit the protection scope of the present invention. All equivalent changes and modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.
Claims (9)
1. A preparation method of an N-type solar cell with a selective emitter is characterized by comprising the following steps:
(1) preprocessing an N-type silicon wafer;
(2) performing first boron diffusion on the front surface of the silicon wafer to form a whole-surface re-diffusion area;
(3) growing a tunneling oxide layer, depositing a heavily doped amorphous silicon layer and a mask layer on the back of the silicon wafer in sequence;
(4) removing the polysilicon wound and plated on the front surface, and reserving a BSG layer with a preset thickness;
(5) performing laser grooving on a non-grid line region on the front side of the silicon wafer, and removing a re-expansion region of the non-grid line region;
(6) carrying out secondary cleaning and texturing on the laser grooving position on the front side of the silicon wafer;
(7) performing boron diffusion on the front surface of the silicon wafer for the second time, forming a light diffusion area at the laser grooving position, and simultaneously crystallizing the amorphous silicon layer to obtain a doped polycrystalline silicon layer;
(8) removing the BSG layer on the front surface and the back surface of the silicon wafer and the mask layer on the back surface;
in the step (7), the junction depth of the heavy expansion region is greater than that of the light expansion region, and the sheet resistance of the heavy expansion region is less than that of the light expansion region.
2. The method as claimed in claim 1, wherein in the step (2), the boron source for the first boron diffusion is boron tribromide or boron trichloride, the diffusion temperature is 950-.
3. The method for preparing an N-type solar cell with a selective emitter according to claim 1, wherein in the step (2), after the first boron diffusion, the thickness of the BSG layer is 80-300 nm.
4. The method of claim 1, wherein the predetermined thickness of the BSG layer remaining in the step (2) is 50-200 nm.
5. The method as claimed in claim 1, wherein in the step (7), the boron source for the second boron diffusion is boron tribromide or boron trichloride, the diffusion temperature is 850-.
6. The method for preparing an N-type solar cell with a selective emitter according to claim 1, wherein in the step (3), when the amorphous silicon layer is deposited: the deposition temperature is 350-500 ℃, and the intrinsic layer is SiH 4 The flow rate of (1) is 500-2500 sccm, and a heavily doped layer SiH 4 The flow rate of (2) is 500-2500 sccm, and the pH value is 3 The flow rate of the catalyst is 500sccm to 4000 sccm.
7. The method according to claim 1, wherein in the step (3), the mask layer is made of SiO 2 、SiN X Combinations of one or more of SiOxNy; the thickness of the mask layer is 30-150 nm; the preparation method of the tunneling oxide layer comprises a high-temperature thermal oxidation method, a PECVD (plasma enhanced chemical vapor deposition) method, a thermal nitric acid oxidation method or an ozone oxidation method; the preparation methods of the amorphous silicon layer and the mask layer are both PECVD.
8. The method for preparing an N-type solar cell with a selective emitter according to claim 1, further comprising the following steps after the step (8):
(9) depositing a front passivation layer on the front surface of the silicon wafer; depositing a back passivation layer on the back of the silicon wafer;
(10) and preparing metal electrodes on the front side and the back side of the silicon wafer.
9. A solar cell prepared by the method for preparing an N-type solar cell having a selective emitter according to any one of claims 1 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210729584.0A CN115036391A (en) | 2022-06-24 | 2022-06-24 | Preparation method of N-type solar cell with selective emitter and cell |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210729584.0A CN115036391A (en) | 2022-06-24 | 2022-06-24 | Preparation method of N-type solar cell with selective emitter and cell |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115036391A true CN115036391A (en) | 2022-09-09 |
Family
ID=83126235
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210729584.0A Pending CN115036391A (en) | 2022-06-24 | 2022-06-24 | Preparation method of N-type solar cell with selective emitter and cell |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115036391A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115911186A (en) * | 2023-01-30 | 2023-04-04 | 通威太阳能(眉山)有限公司 | Solar cell and preparation method thereof |
| CN116995110A (en) * | 2023-07-31 | 2023-11-03 | 江苏润阳世纪光伏科技有限公司 | Preparation method of N-type TOPCON battery |
| CN117153953A (en) * | 2023-10-30 | 2023-12-01 | 常州亿晶光电科技有限公司 | Preparation method of split-film type double-sided TOPCON battery |
| CN117352597A (en) * | 2023-12-05 | 2024-01-05 | 一道新能源科技股份有限公司 | Preparation method of solar cell, solar cell and electric equipment |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101814547A (en) * | 2009-02-19 | 2010-08-25 | 上海交大泰阳绿色能源有限公司 | Method for preparing selective emitter crystalline silicon solar cell |
| CN102169923A (en) * | 2011-03-05 | 2011-08-31 | 常州天合光能有限公司 | Method for passivating P-type doping layer of N-type silicon solar cell and cell structure |
| CN109671807A (en) * | 2018-12-26 | 2019-04-23 | 浙江晶科能源有限公司 | A kind of preparation method of solar battery |
| CN110707178A (en) * | 2019-08-29 | 2020-01-17 | 晶科能源科技（海宁）有限公司 | Preparation method of N-type solar cell boron-diffusion SE structure |
| CN110739367A (en) * | 2019-10-23 | 2020-01-31 | 泰州中来光电科技有限公司 | Preparation method of N-type TOPCon solar cells |
| CN111370539A (en) * | 2020-03-19 | 2020-07-03 | 泰州中来光电科技有限公司 | Preparation method of solar cell with selective emitter |
| WO2022068132A1 (en) * | 2020-09-30 | 2022-04-07 | 浙江正泰太阳能科技有限公司 | Selective emitter preparation method, solar cell and preparation method therefor |
| WO2022105192A1 (en) * | 2020-11-19 | 2022-05-27 | 江苏大学 | Pecvd technology-based preparation method for high-efficiency low-cost n-type topcon battery |
-
2022
- 2022-06-24 CN CN202210729584.0A patent/CN115036391A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101814547A (en) * | 2009-02-19 | 2010-08-25 | 上海交大泰阳绿色能源有限公司 | Method for preparing selective emitter crystalline silicon solar cell |
| CN102169923A (en) * | 2011-03-05 | 2011-08-31 | 常州天合光能有限公司 | Method for passivating P-type doping layer of N-type silicon solar cell and cell structure |
| CN109671807A (en) * | 2018-12-26 | 2019-04-23 | 浙江晶科能源有限公司 | A kind of preparation method of solar battery |
| CN110707178A (en) * | 2019-08-29 | 2020-01-17 | 晶科能源科技（海宁）有限公司 | Preparation method of N-type solar cell boron-diffusion SE structure |
| CN110739367A (en) * | 2019-10-23 | 2020-01-31 | 泰州中来光电科技有限公司 | Preparation method of N-type TOPCon solar cells |
| CN111370539A (en) * | 2020-03-19 | 2020-07-03 | 泰州中来光电科技有限公司 | Preparation method of solar cell with selective emitter |
| WO2022068132A1 (en) * | 2020-09-30 | 2022-04-07 | 浙江正泰太阳能科技有限公司 | Selective emitter preparation method, solar cell and preparation method therefor |
| WO2022105192A1 (en) * | 2020-11-19 | 2022-05-27 | 江苏大学 | Pecvd technology-based preparation method for high-efficiency low-cost n-type topcon battery |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115911186A (en) * | 2023-01-30 | 2023-04-04 | 通威太阳能(眉山)有限公司 | Solar cell and preparation method thereof |
| CN116995110A (en) * | 2023-07-31 | 2023-11-03 | 江苏润阳世纪光伏科技有限公司 | Preparation method of N-type TOPCON battery |
| CN116995110B (en) * | 2023-07-31 | 2024-02-27 | 江苏润阳世纪光伏科技有限公司 | Preparation method of N-type TOPCON battery |
| CN117153953A (en) * | 2023-10-30 | 2023-12-01 | 常州亿晶光电科技有限公司 | Preparation method of split-film type double-sided TOPCON battery |
| CN117153953B (en) * | 2023-10-30 | 2024-01-02 | 常州亿晶光电科技有限公司 | Preparation method of split-film type double-sided TOPCON battery |
| CN117352597A (en) * | 2023-12-05 | 2024-01-05 | 一道新能源科技股份有限公司 | Preparation method of solar cell, solar cell and electric equipment |
| CN117352597B (en) * | 2023-12-05 | 2024-04-02 | 一道新能源科技股份有限公司 | Preparation method of solar cell, solar cell and electric equipment |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN115036391A (en) | Preparation method of N-type solar cell with selective emitter and cell | |
| CN109494261A (en) | Silica-based solar cell and preparation method, photovoltaic module | |
| CN112490304A (en) | Preparation method of high-efficiency solar cell | |
| CN210926046U (en) | Solar cell | |
| CN113611755A (en) | Local passivation contact IBC battery structure and preparation method thereof | |
| CN112510121B (en) | Pre-and-post alkali polishing protection process for perc battery | |
| CN114975691A (en) | Passivated contact solar cell with selective emitter and preparation method, assembly and system thereof | |
| CN113964223B (en) | Crystalline silicon solar cell capable of inhibiting electric leakage at cutting edge, cell assembly and preparation method | |
| CN112820793A (en) | Solar cell and preparation method thereof | |
| WO2024066207A1 (en) | New solar cell and fabrication method therefor | |
| CN115411146A (en) | TOPCon battery preparation method and TOPCon battery | |
| CN111477720A (en) | Passivated contact N-type back junction solar cell and preparation method thereof | |
| CN114256385A (en) | TBC back contact solar cell and preparation method thereof | |
| CN115458612A (en) | Solar cell and preparation method thereof | |
| WO2014092649A1 (en) | A method of manufacturing a photovoltaic cell | |
| CN117457797A (en) | Preparation method and application of TOPCON battery structure | |
| CN117153948A (en) | Passivation contact solar cell preparation method | |
| CN116825896A (en) | Preparation method of TOPCON battery with back selective passivation layer | |
| CN219696463U (en) | Solar cell | |
| CN116314471A (en) | Preparation method of rear SE structure | |
| CN110047950A (en) | A kind of solar cell and preparation method thereof with passivation layer structure | |
| CN117594684A (en) | Double-sided hybrid solar cell and preparation method thereof | |
| CN115692516A (en) | Novel TOPCON battery and manufacturing method thereof | |
| CN115440839A (en) | Solar cell and preparation method thereof | |
| CN115332392A (en) | Preparation method of P-type passivated contact solar cell |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |