CN117153885A - Split gate trench MOSFET device and method of making - Google Patents
Split gate trench MOSFET device and method of making Download PDFInfo
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- CN117153885A CN117153885A CN202311192994.7A CN202311192994A CN117153885A CN 117153885 A CN117153885 A CN 117153885A CN 202311192994 A CN202311192994 A CN 202311192994A CN 117153885 A CN117153885 A CN 117153885A
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- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 259
- 229920005591 polysilicon Polymers 0.000 claims abstract description 161
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 82
- 229910052751 metal Inorganic materials 0.000 claims abstract description 42
- 239000002184 metal Substances 0.000 claims abstract description 42
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 34
- 239000010703 silicon Substances 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims description 75
- 230000008569 process Effects 0.000 claims description 73
- 238000005530 etching Methods 0.000 claims description 59
- 238000002513 implantation Methods 0.000 claims description 32
- 238000001259 photo etching Methods 0.000 claims description 26
- 238000000137 annealing Methods 0.000 claims description 21
- 238000002347 injection Methods 0.000 claims description 20
- 239000007924 injection Substances 0.000 claims description 20
- 238000000151 deposition Methods 0.000 claims description 18
- 238000005468 ion implantation Methods 0.000 claims description 13
- 230000003647 oxidation Effects 0.000 claims description 13
- 238000007254 oxidation reaction Methods 0.000 claims description 13
- 238000002161 passivation Methods 0.000 claims description 9
- 229910052796 boron Inorganic materials 0.000 claims description 8
- 229910052760 oxygen Inorganic materials 0.000 claims description 7
- 239000001301 oxygen Substances 0.000 claims description 7
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- -1 boron ions Chemical class 0.000 claims description 6
- 238000000206 photolithography Methods 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 238000001704 evaporation Methods 0.000 claims description 3
- 239000007943 implant Substances 0.000 claims 2
- 238000002360 preparation method Methods 0.000 abstract description 8
- 238000010586 diagram Methods 0.000 description 9
- 239000000243 solution Substances 0.000 description 7
- 238000000926 separation method Methods 0.000 description 5
- 230000008859 change Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229920006395 saturated elastomer Polymers 0.000 description 3
- 238000002955 isolation Methods 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 239000008186 active pharmaceutical agent Substances 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 150000002500 ions Chemical group 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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Abstract
The invention provides a split gate trench MOSFET device and a preparation method thereof, comprising the following steps: an N+ type silicon substrate, an N-type drift region, a cell trench, a source polysilicon contact trench, a first gate electrode, a second gate electrode, a source electrode and a drain electrode; the N-type drift region is arranged on the N+ type silicon substrate, the cell groove and the source polycrystalline silicon contact groove are arranged on the N-type drift region, the first gate electrode, the second gate electrode and the source electrode are arranged on the metal layer on the surface of the cell groove, and the drain electrode is arranged on the metal layer on the back surface of the N+ type silicon substrate; a first source polycrystalline silicon structure is arranged in the primitive cell groove, grid polycrystalline silicon structures are arranged around the first source polycrystalline silicon structure, and a second source polycrystalline silicon structure is arranged in the source polycrystalline silicon contact groove; the first gate electrode and the second gate electrode are connected in series through the gate polysilicon structure, and the second gate electrode is also connected in series with the source electrode through the second source polysilicon structure, so that the device has good transconductance stability and linear output characteristics.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a split gate trench MOSFET device and a preparation method thereof.
Background
The modern power MOS can simultaneously realize lower on-state resistance and higher blocking voltage by introducing a charge compensation structure, wherein a split gate trench MOSFET (Split Gate Trench MOSFET, SGT MOSFET) is characterized in that a split polysilicon gate which is equipotential with a source electrode is introduced into the bottom of a polysilicon gate of a common trench MOSFET by utilizing a charge compensation principle, and the drift region of an in-body field plate auxiliary MOSFET is used for depletion, so that the R of a low-power MOS device can be obviously reduced by arranging a low-resistance drift region under the condition of ensuring the voltage-withstanding grade DS(ON) . Currently, split gate trench MOSFETs have been used not only as power switches, but also in many scenarios for a variety of linear applications such as linear regulators, linear amplifiers, electronic loads, hot plug circuits, etc.
However, most split gate trench MOSFET devices have poor transconductance stability due to the shielding effect of the split gate structure against the channel voltage at high Vds voltages, resulting in distortion of the output signal in linear applications.
Disclosure of Invention
The invention provides a split gate trench MOSFET device and a preparation method thereof, which are used for solving the problem of poor transconductance stability caused by the shielding effect of a split gate structure on channel voltage under high Vds voltage in the prior art.
The invention provides a split gate trench MOSFET device, comprising: an N+ type silicon substrate, an N-type drift region, a cell trench, a source polysilicon contact trench, a first gate electrode, a second gate electrode, a source electrode and a drain electrode;
the N-type drift region is arranged on the N+ type silicon substrate, the cell groove and the source polycrystalline silicon contact groove are arranged on the N-type drift region, the first gate electrode, the second gate electrode and the source electrode are arranged on a metal layer on the surface of the cell groove, and the drain electrode is arranged on a metal layer on the surface, far away from the N-type drift region, of the N+ type silicon substrate;
a first source polycrystalline silicon structure is arranged in the primitive cell groove, grid polycrystalline silicon structures are arranged around the first source polycrystalline silicon structure, and a second source polycrystalline silicon structure is arranged in the source polycrystalline silicon contact groove;
the first gate electrode and the second gate electrode are connected in series through the gate polysilicon structure, and the second gate electrode is also connected in series with the source electrode through the second source polysilicon structure.
According to the split gate trench MOSFET device provided by the invention, the cell trench and the source polysilicon contact trench are periodically arranged in a number ratio (15-30): 1.
According to the split gate trench MOSFET device provided by the invention, the bottom oxide layer is arranged between the inside of the cell trench and the first source polycrystalline silicon structure, and between the source polycrystalline silicon contact trench and the second source polycrystalline silicon structure.
According to the split gate trench MOSFET device provided by the invention, the first source polycrystalline silicon structure is formed by carrying out a photoetching process and a back etching process on polycrystalline silicon deposited in the primitive cell trench;
the second source polysilicon structure is formed by performing a photolithography process on polysilicon deposited in the source polysilicon contact trench.
According to the split gate trench MOSFET device provided by the invention, the first source polycrystalline silicon structure is provided with the oxide layer;
the gate oxide layer structure is formed by thermally growing side walls on two sides of a cell groove above the oxide layer through a dry oxygen oxidation process.
According to the split gate trench MOSFET device provided by the invention, the surface of the gate polysilicon structure is provided with the shielding oxide layer;
and the P base region is formed by performing global boron ion implantation on the wafer on which the shielding oxide layer is formed.
According to the split gate trench MOSFET device provided by the invention, the surface of the P base region is provided with the N+ type injection layer;
and the N+ type injection layer is formed by carrying out arsenic ion injection on the surface of the P base region.
According to the split gate trench MOSFET device provided by the invention, the surface of the N+ type injection layer is also provided with a dielectric oxide layer;
and forming a metal electrode contact hole through a photoetching process on the dielectric oxide layer, wherein the grid polycrystalline silicon structure and the second grid electrode on the second source polycrystalline silicon structure are connected through the metal electrode contact hole.
The invention also provides a preparation method of the split gate trench MOSFET device, which comprises the following steps:
an N+ type silicon substrate is selected as a wafer, an N-type epitaxial layer is deposited on the N+ type silicon substrate to serve as an N-type drift region, a photoetching process and an etching process are carried out on the N-type drift region, and a groove is formed, wherein the groove comprises a primitive cell groove and a source polycrystalline silicon contact groove; the number of the primitive cell grooves and the number of the source polycrystalline silicon contact grooves are periodically arranged in a ratio of (15-30): 1;
forming a bottom oxide layer in the primordial cell groove and the source polycrystalline silicon contact groove through thermally growing an oxide layer by a thermal oxidation process;
depositing polysilicon on the bottom oxide layer, in the cell groove and in the source polysilicon contact groove, and removing redundant polysilicon higher than the surfaces of the bottom oxide layer, the cell groove and the source polysilicon contact groove; carrying out back etching on the polysilicon of the back etching area of the intrinsic pole polysilicon of the primitive cell groove by adopting a photoetching process and an etching process, and not carrying out back etching on the polysilicon of the area outside the back etching area of the polysilicon in the primitive cell groove to form a first source polysilicon structure; the whole polysilicon deposited in the source polysilicon contact groove is not etched back, so that a second source polysilicon structure is formed;
removing the bottom oxide layer on the side wall of the primitive cell groove to the position of the back etching depth of the first source polycrystalline silicon structure of 0.3-0.6 mu m by adopting a photoetching process and an etching process; forming a gate oxide layer structure on the side walls of the two sides of the primitive cell groove above the oxide layer by adopting a dry oxygen oxidation process through an oxidation process of the first source polycrystalline silicon structure;
polysilicon deposition is carried out on the primitive cell groove and the source polysilicon contact groove, polysilicon higher than the surface of the groove is removed, a grid polysilicon structure is formed in the etching-back area of the first source polysilicon structure, and the grid polysilicon structure surrounds the periphery of the first source polysilicon structure; performing a dry oxygen oxidation process on the surface of the grid polycrystalline silicon structure to form an oxide layer with the thickness of 0.04-0.07 mm;
thinning the oxide layer to a thickness of 0.03-0.04 mu m, and performing global implantation of boron ions on a wafer on which the oxide layer is formed to form a P base region;
carrying out arsenic ion implantation on the surface of the P base region to form an N+ type ion implantation region, and then carrying out ion implantation annealing to form an N+ type implantation layer;
depositing a dielectric oxide layer with the thickness of 1.0-1.5 mu m on the wafer on which the N+ type injection layer is formed; forming a metal electrode contact hole on the dielectric oxide layer through a photoetching process, forming a first type source polycrystalline silicon contact hole in a source polycrystalline silicon non-etching area in the primitive cell groove, forming a first grid contact hole in a source polycrystalline silicon etching area in the primitive cell groove, forming a first grid contact hole and a first type second grid contact hole in the source polycrystalline silicon etching area in the primitive cell groove, and forming a second type second grid contact hole and a second type source polycrystalline silicon contact hole in a second source polycrystalline silicon structure in the source polycrystalline silicon contact groove;
silicon back etching is carried out through the metal electrode contact hole, the back etching depth is 0.4-0.6 mu m, an N+ source region is formed, a source electrode contact region BF2 injection process is carried out, and annealing is carried out after injection; depositing an AlSiCu metal layer with the thickness of 4-6 mu m on the upper surface of the wafer with the metal electrode contact hole, and forming a source electrode, a first gate electrode and a second gate electrode through a photoetching process and an etching process;
the first gate electrode is connected in series through the first gate contact hole, the first type second gate contact hole and the source polycrystalline silicon structure in the primitive cell groove; the second gate electrode is connected in series through the second type source polycrystalline silicon contact hole, the second type second gate contact hole and the second type source polycrystalline silicon, and the first type source polycrystalline silicon contact hole is connected with the source electrode;
depositing passivation layers on the source electrode, the first gate electrode and the second gate electrode, and forming a passivation structure through a photoetching process and an etching process; and evaporating a Ti/Ni/Ag metal layer on the surface of the N+ type silicon substrate far away from the N-type drift region to form a drain electrode.
According to the preparation method of the split gate trench MOSFET device, the depth of the cell trench and the depth of the source polycrystalline silicon contact trench are 4-7 mu m, and the width of the cell trench and the source polycrystalline silicon contact trench is 1.0-1.8 mu m;
the thickness of the bottom oxide layer is 0.4-0.9 mu m;
the thickness of the gate oxide layer structure is 0.04-0.09 mu m;
forming the P base region, wherein the implantation energy of the boron ions is 80-150 KeV, and the implantation dosage is 1.3E13-2.1E13;
when the N+ type injection layer is formed, the annealing temperature is 950-1000 ℃ and the annealing time is 90-120 min;
in the BF2 implantation process, the implantation energy is 60-80 KeV, the implantation dosage is 3E 14-5E 14, the annealing temperature is 900-1000 ℃, and the annealing time is 20-30 min.
The invention provides a split gate trench MOSFET device and a preparation method thereof, wherein the split gate trench MOSFET device comprises: an N+ type silicon substrate, an N-type drift region, a cell trench, a source polysilicon contact trench, a first gate electrode, a second gate electrode, a source electrode and a drain electrode; the N-type drift region is arranged on the N+ type silicon substrate, the cell groove and the source polycrystalline silicon contact groove are arranged on the N-type drift region, the first gate electrode, the second gate electrode and the source electrode are arranged on the metal layer on the surface of the cell groove, and the drain electrode is arranged on the metal layer on the surface, far away from the N-type drift region, of the N+ type silicon substrate; a first source polycrystalline silicon structure is arranged in the primitive cell groove, grid polycrystalline silicon structures are arranged around the first source polycrystalline silicon structure, and a second source polycrystalline silicon structure is arranged in the source polycrystalline silicon contact groove; the first gate electrode and the second gate electrode are connected in series through the gate polysilicon structure, the second gate electrode is also connected in series with the source electrode through the second source polysilicon structure, and due to the fact that the first gate electrode and the second gate electrode are arranged, serial voltage division is achieved, gradual change Vgs voltage is introduced in the direction of a cell groove, the actual potential difference Vds 'generated at two ends of a device channel by a high drain source voltage Vds is enabled to approach saturation by a separation gate groove MOSFET device, meanwhile, the MOSFET cell at the side of the second gate electrode with lower gate source potential meets the actual potential difference Vds' > Vgs-Vth at two ends of the channel in a relatively lower Vds voltage interval, channel pinch-off is generated, and the channel pinch-off enters a saturated working area of an input-output characteristic curve of the MOSFET device, and the device has good transconductance stability and linear output characteristics.
Drawings
In order to more clearly illustrate the invention or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic cross-sectional view of a cell trench of a split gate trench MOSFET device according to an embodiment of the present invention;
fig. 2 is a schematic cross-sectional view of a source polysilicon contact trench of a split gate trench MOSFET device provided by an embodiment of the invention;
fig. 3 is a top view of a split gate trench MOSFET device provided in an embodiment of the invention;
fig. 4 is one of partial structure diagrams of a split gate trench MOSFET device according to an embodiment of the present invention:
fig. 5 is a second partial structure diagram of a split gate trench MOSFET device according to an embodiment of the present invention:
fig. 6 is a third partial structure diagram of a split gate trench MOSFET device according to an embodiment of the present invention:
fig. 7 is a diagram showing a partial structure of a split gate trench MOSFET device according to an embodiment of the present invention:
fig. 8 is a fifth partial structure diagram of a split gate trench MOSFET device according to an embodiment of the present invention:
fig. 9 is a sixth partial structure diagram of a split gate trench MOSFET device according to an embodiment of the present invention:
fig. 10 is a seventh partial structure diagram of a split gate trench MOSFET device according to an embodiment of the present invention:
fig. 11 is a schematic diagram of a partial structure of a split gate trench MOSFET device according to an embodiment of the present invention:
fig. 12 is a ninth partial structure diagram of a split gate trench MOSFET device according to an embodiment of the present invention:
fig. 13 is an input-output characteristic curve of a conventional split gate trench MOSFET device;
fig. 14 is a graph showing the input-output characteristics of the split gate trench provided by the present invention.
Reference numerals:
1. an n+ type silicon substrate; 2. an N-type drift region; 3-1, a cell groove; 3-2, a source polysilicon contact trench; 4. a bottom oxide layer; 5-1, a first source polycrystalline silicon structure; 5-2, a second source polycrystalline silicon structure; 6. a gate oxide layer structure; 7. a gate polysilicon structure; 8. a P base region; 9. an n+ type injection layer; 10. a source electrode; 11-1, a first gate electrode; 11-2, a second gate electrode; 12. a passivation structure; 13. and a drain electrode.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
A split gate trench MOSFET device and method of fabrication of the present invention is described below with reference to fig. 1-14.
Fig. 1 is a schematic cross-sectional view of a cell trench of a split gate trench MOSFET device according to an embodiment of the present invention, fig. 2 is a schematic cross-sectional view of a source polysilicon contact trench of a split gate trench MOSFET device according to an embodiment of the present invention, and fig. 3 is a top view of a split gate trench MOSFET device according to an embodiment of the present invention.
As shown in fig. 1 to 3, a split gate trench MOSFET device according to an embodiment of the present invention includes: an N+ type silicon substrate 1, an N-type drift region 2, a cell trench 3-1, a source polysilicon contact trench 3-2, a first gate electrode 11-1, a second gate electrode 11-2, a source electrode 10 and a drain electrode 13; the N-type drift region 2 is arranged on the N+ type silicon substrate 1, the cell groove 3-1 and the source polycrystalline silicon contact groove 3-2 are arranged on the N-type drift region 2, the first gate electrode 11-1, the second gate electrode 11-2 and the source electrode 10 are arranged on a metal layer on the surface of the cell groove 3-1, and the drain electrode 13 is arranged on a metal layer on the surface, far away from the N-type drift region 2, of the N+ type silicon substrate 1; a first source polycrystalline silicon structure 5-1 is arranged in the primitive cell groove 3-1, a grid polycrystalline silicon structure 7 is arranged around the first source polycrystalline silicon structure 5-1, and a second source polycrystalline silicon structure 5-2 is arranged in the source polycrystalline silicon contact groove 3-2; the first gate electrode 11-1 and the second gate electrode 11-2 are connected in series through the gate polysilicon structure 7, and the second gate electrode 11-2 is also connected in series with the source electrode 10 through the second source polysilicon structure 5-2.
In a specific implementation process, an N+ type silicon substrate 1 is used as a wafer, an N-type drift region 2 is formed on the surface of the N+ type silicon substrate 1 through epitaxial growth, then a cell groove 3-1 and a source polycrystalline silicon contact groove 3-2 are arranged on the N-type drift region 2 according to a certain periodic rule, wherein the cell groove 3-1 and the source polycrystalline silicon contact groove 3-2 are periodically arranged in a quantity ratio (15-30): 1, and the partial pressure relation between a first gate electrode and a second gate electrode can be adjusted through specific arrangement. 15:1, each 15 cell trenches 3-1 are provided, and a source polysilicon contact trench 3-2 is correspondingly provided. Each cell trench 3-1 and each source polysilicon contact trench 3-2 are explained, and as shown in fig. 3, isolation regions are included on both sides of each cell trench 3-1, which can be understood as four columns, from left to right, the second column being the cell trench 3-1 and the fourth column being the source polysilicon contact trench 3-2. The metal layer of the cell trench 3-1 is provided with a first gate electrode 11-1, a second gate electrode 11-2, a source electrode 10 and a drain electrode 13, which are arranged on the lower surface of the n+ type silicon substrate 1, i.e. the surface far from the N-type drift region 2.
The first gate electrode 11-1 and the second gate electrode 11-2 are respectively located at two ends of the cell groove 3-1 and are connected with gate polysilicon in the cell groove 3-1. The first gate electrode 11-1 and the second gate electrode 11-2 are connected in series through the gate polysilicon structure 7 around the first source polysilicon structure 5-1, and the second gate electrode 11-2 is also connected in series with the source electrode 10 through the second source polysilicon structure 5-2 within the source polysilicon contact trench 3-2. As shown in fig. 3, the second gate electrode 11-2 of the cell trench 3-1 and the second gate electrode 11-2 in the source polysilicon contact trench 3-2 are the same electrode, and are connected through separate electrode holes.
The cell trench 3-1 of the split gate trench MOSFET device of the embodiment is internally provided with a first source polysilicon structure 5-1 and a gate polysilicon structure 7; a base region injection layer and a source region injection layer are arranged on the upper surface of the silicon drift region between the cell grooves 3-1; an active metal opening is formed between the grooves, active metal is filled in the active metal opening, and ohmic contact is formed between the active metal opening and the base region and the source region; the grid polysilicon in the groove is connected with the grid electrode, the source polysilicon is connected with the source electrode 10, and the metal electrode and the silicon surface are provided with the tetraethoxysilane dielectric layer.
Further, as shown in fig. 1 and 2, a bottom oxide layer 4 is disposed between the first source polysilicon structure 5-1 and the inside of the cell trench 3-1, and between the source polysilicon contact trench 3-2 and the second source polysilicon structure 5-2. The first source polycrystalline silicon structure 5-1 is formed by carrying out a photoetching process and a back etching process on polycrystalline silicon deposited in the primitive cell groove 3-1; the second source polysilicon structure 5-2 is formed by performing a photolithography process on the polysilicon deposited in the source polysilicon contact trench 3-2.
Specifically, the cell trench 3-1 and the source polysilicon contact trench 3-2 are both provided with a bottom oxide layer 4, and the thickness of the bottom oxide layer 4 is 0.4-0.9 μm. A first source polysilicon structure 5-1 is provided between the bottom oxide layer 4 and the cell trench 3-1, and a second source polysilicon structure 5-2 is provided between the bottom oxide layer 4 and the source polysilicon contact trench 3-2. The first source polysilicon structure 5-1 is different from the second source polysilicon structure 5-2, the first source polysilicon structure 5-1 is obtained by depositing polysilicon in the bottom oxide layer 4 and the cell trench 3-1, then removing the excessive polysilicon higher than the surfaces of the bottom oxide layer 4 and the cell trench 3-1, and performing photolithography and etching processes on the polysilicon in the cell trench 3-1 without performing polysilicon back etching on the contact area of the polysilicon and the source electrode 10. The second source polysilicon structure 5-2 is formed by depositing polysilicon directly in the bottom oxide layer 4 and the source polysilicon contact trench 3-2.
Further, gate oxide layer junctions are arranged on the first source polycrystalline silicon structure 5-1; the gate oxide layer structure 6 is formed by thermally growing side walls on two sides of the cell groove 3-1 above the oxide layer through a dry oxygen oxidation process.
Specifically, the gate oxide layer structure 6 is used to separate the first source polysilicon structure 5-1 from the gate polysilicon, and the gate polysilicon surrounds the first source polysilicon structure 5-1, as shown in fig. 3, so that a series connection between the first gate electrode 11-1 and the second gate electrode 11-2 disposed at two ends of the gate polysilicon can be achieved. A shielding oxide layer is arranged on the surface of the grid polycrystalline silicon structure 7; for example, the thickness of the shielding oxide layer is 0.04-0.07mm, then the shielding oxide layer is thinned to a thickness of 0.03-0.04 μm, and global implantation of boron ions is performed on the wafer on which the shielding oxide layer is formed to obtain the P base region 8. Wherein the implantation energy is 80-150 KeV, and the implantation dose is 1.3E13-2.1E13.
Furthermore, on the basis of the above embodiment, an n+ type injection layer 9 is further disposed on the surface of the P base region 8; the n+ type implanted layer 9 is formed by arsenic ion implantation on the surface of the P base region 8. The surface of the N+ type injection layer 9 is also provided with a dielectric oxide layer; the dielectric oxide layer forms a metal electrode contact hole through a photoetching process, and the gate polysilicon structure 7 is connected with the second gate electrode 11-2 on the second source polysilicon structure 5-2 through the metal electrode contact hole.
Specifically, the N+ implantation layer is ion annealed after arsenic ions are implanted, the annealing temperature is 950-1000 ℃, and the annealing time is 90-120 min, so that the N+ implantation layer 9 is formed. A dielectric oxide layer with the thickness of 1.0-1.5 mu m is deposited on the wafer of the N+ type injection layer 9, and the dielectric oxide layer is used for realizing the isolation between the electrode and the N+ type injection layer 9.
The source electrode 10, the first gate electrode 11-1 and the second gate electrode 11-2 are formed by performing a photoetching process on a dielectric oxide layer to form a metal electrode contact hole, then performing silicon back etching on the metal electrode contact hole, wherein the back etching depth is 0.4-0.6 um, forming an N+ source region, performing a BF2 implantation process of the source electrode 10 contact region, and performing annealing after implantation, wherein the implantation energy is 60-80 KeV, the implantation dosage is 3E 14-5E 14, the annealing temperature is 900-1000 ℃, and the annealing time is 20-30 min; and depositing an AlSiCu metal layer with the thickness of 4-6 mu m on the upper surface of the wafer with the metal electrode contact hole, and forming the AlSiCu metal layer through a photoetching process and an etching process.
A passivation structure 12 is further disposed on the source electrode 10, the first gate electrode 11-1, and the second gate electrode 11-2, and the passivation structure 12 is formed on the source electrode 10, the first gate electrode 11-1, and the second gate electrode 11-2 through a photolithography process and an etching process.
The invention defines a first gate electrode 11-1 and a second gate electrode 11-2 at two ends of an array of primitive cell grooves 3-1, adopts a photoetching process and an etching process to control the back etching depth of local source polysilicon in the primitive cell grooves 3-1, and connects the first gate electrode 11-1 and the second gate electrode 11-2 in series through gate polysilicon; defining a part of unetched region of source polycrystalline silicon in the primitive cell groove 3-1 by adopting a photoetching pattern to form a groove without a grid structure, and realizing the series connection of the second grid electrode 11-2 and the source electrode 10 by utilizing the source polycrystalline silicon in the groove; the impurity doping concentration in the deposition process of the grid polysilicon and the source polysilicon is controlled to enable the grid polysilicon and the source polysilicon to have proper resistivity, and proper resistance values are introduced into the first grid electrode 11-1 and the second grid electrode 11-2 which are connected in series and the second grid electrode 11-2 and the source electrode 10 by utilizing the grid polysilicon and the source polysilicon resistor; when Vgs voltage is applied to the device, the first gate electrode 11-1 and the second gate electrode 11-2 have different gate-source voltages Vgs1 and Vgs2 and Vgs1 > Vgs2, respectively, due to the resistance voltage division relationship, which gradually reduces the potential of the gate polysilicon in the same trench from the first gate electrode 11-1 potential Vgs1 to the second gate electrode 11-2 potential Vgs2. Compared with a separation gate trench MOSFET with constant common threshold voltage, due to the arrangement of the first gate electrode 11-1 and the second gate electrode 11-2, the serial partial pressure of the first gate electrode 11-1 and the second gate electrode 11-2 is realized, the gradual change Vgs voltage is introduced in the direction of the primitive cell trench 3-1, the actual potential difference Vds ' generated by the high drain source voltage Vds at two ends of a device channel is approaching saturation by utilizing a separation gate structure, and meanwhile, the MOSFET primitive cells at the side of the second gate electrode 11-2 with lower gate source potential meet the actual potential difference Vds ' at two ends of the channel in a relatively lower Vds voltage interval to generate channel pinch-off, and enter a saturated working area of an input-output characteristic curve of the separation gate trench MOSFET device, and the output current is in a direct proportion relation with the Vgs, and is irrelevant to the Vds ', so that the device has good transconductance stability and linear output characteristic.
Based on the same general inventive concept, the invention also provides a preparation method of the split gate trench MOSFET device, which mainly comprises the following steps:
as shown in fig. 4, the left side view in fig. 4 is a cross-sectional view of the cell trench 3-1 and the source polysilicon contact trench 3-2, and the right side view is a top view. An N+ type silicon substrate 1 is selected as a wafer, an N-type epitaxial layer is deposited on the N+ type silicon substrate 1 to serve as an N-type drift region 2, and a photoetching process and an etching process are carried out on the N-type drift region 2 to form grooves with the depth of 4-7 mu m and the width of 1.0-1.8 mu m, wherein the grooves comprise a cell groove 3-1 and a source polycrystalline silicon contact groove 3-2; the number of the cell trenches 3-1 and the number of the source polysilicon contact trenches 3-2 are periodically set in a ratio of (15-30): 1.
As shown in fig. 5, the left side view is a cross-sectional view of the cell trench 3-1 and the source polysilicon contact trench 3-2, and the right side view is a top view. And forming a bottom oxide layer 4 with the thickness of 0.4-0.9 mu m in the primitive cell groove 3-1 and the source polycrystalline silicon contact groove 3-2 through thermally growing an oxide layer by a thermal oxidation process.
As shown in fig. 6, the left side view is a cross-sectional view of the cell trench 3-1, the middle view is a cross-sectional view of the source polysilicon contact trench 3-2, and the right side view is a top view. Depositing polysilicon on the bottom oxide layer 4, in the cell groove 3-1 and in the source polysilicon contact groove 3-2, and removing redundant polysilicon higher than the surfaces of the bottom oxide layer 4, the cell groove 3-1 and the source polysilicon contact groove 3-2; the polysilicon of the source electrode polysilicon etching back area in the primitive cell groove 3-1 is etched back by adopting a photoetching process and an etching process, and the polysilicon etching back area is not etched back in the area outside the source electrode polysilicon etching back area in the primitive cell groove 3-1, so that a first source electrode polysilicon structure 5-1 is formed; and etching the whole deposited polysilicon in the source polysilicon contact groove 3-2 without back etching to form a second source polysilicon structure 5-2.
As shown in fig. 7, the left side view is a cross-sectional view of the cell trench 3-1, the middle view is a cross-sectional view of the source polysilicon contact trench 3-2, and the right side view is a top view. Removing the bottom oxide layer 4 on the side wall of the cell groove 3-1 to a position 0.3-06 mu m above the back etching depth of the first source polycrystalline silicon structure 5-1 by adopting a photoetching process and an etching process; and forming a gate oxide layer structure 6 on the side walls of the two sides of the primitive cell groove above the oxide layer through an oxidation process of the first source polycrystalline silicon structure.
As shown in fig. 8, the left side view is a cross-sectional view of the cell trench 3-1, the middle view is a cross-sectional view of the source polysilicon contact trench 3-2, and the right side view is a top view. Polysilicon deposition is carried out on the primitive cell groove 3-1 and the source polysilicon contact groove 3-2, polysilicon higher than the surface of the groove is removed, a grid polysilicon structure 7 is formed in a back etching area of the first source polysilicon structure 5-1, and the grid polysilicon structure 7 surrounds the periphery of the first source polysilicon structure 5-1; and performing a dry oxygen oxidation process on the surface of the grid polycrystalline silicon structure 7 to form an oxide layer with the thickness of 0.04-0.07 mm.
As shown in fig. 9, the shielding oxide layer is thinned to a thickness of 0.03-0.04 μm, and boron ion global implantation is performed on the wafer on which the shielding oxide layer is formed to form a P base region 8; the implantation energy is 80-150 KeV, and the implantation dose is 1.3E13-2.1E13.
As shown in fig. 10, arsenic ion implantation is performed on the surface of the P base region 8 to form an n+ type ion implantation region, and then ion implantation annealing is performed at 950-1000 ℃ for 90-120 min to form an n+ type implantation layer 9.
As shown in fig. 11, the left side view is a cross-sectional view of the cell trench 3-1, the middle view is a cross-sectional view of the source polysilicon contact trench 3-2, and the right side view is a top view. Depositing a dielectric oxide layer with the thickness of 1.0-1.5 mu m on a wafer on which an N+ type injection layer 9 is formed; forming a metal electrode contact hole on the dielectric oxide layer through a photoetching process, forming a first type source electrode polysilicon contact hole in a source electrode polysilicon non-etching area in the primitive cell groove, forming a first grid electrode contact hole in a source electrode polysilicon etching area in the primitive cell groove, forming a first type second grid electrode contact hole in the source electrode polysilicon etching area in the primitive cell groove, forming a first type second grid electrode contact hole and a first type second grid electrode contact hole in the source electrode polysilicon etching area in the primitive cell groove, and forming a second type second grid electrode contact hole and a second type source electrode polysilicon contact hole in a second source electrode polysilicon structure in the source electrode polysilicon contact groove; silicon back etching is carried out through the metal electrode contact hole, the back etching depth is 0.4-0.6 mu m, an N+ source region is formed, a BF2 implantation process of the source electrode 10 contact region is carried out, and annealing is carried out after implantation; the implantation energy is 60-80 KeV, the implantation dosage is 3E 14-5E 14, the annealing temperature is 900-1000 ℃, and the annealing time is 20-30 min; depositing an AlSiCu metal layer with the thickness of 4-6 mu m on the upper surface of the wafer with the metal electrode contact hole, and forming a source electrode 10, a first gate electrode 11-1 and a second gate electrode 11-2 through a photoetching process and an etching process; the first gate electrode is connected in series through the first gate contact hole, the first type second gate contact hole and the source polycrystalline silicon structure in the primitive cell groove; the second gate electrode is connected in series through the second type source polycrystalline silicon contact hole, the second type second gate contact hole and the second type source polycrystalline silicon, and the first type source polycrystalline silicon contact hole is connected with the source electrode.
As shown in fig. 12, the left side view is a cross-sectional view of the cell trench 3-1, and the right side view is a cross-sectional view of the source polysilicon contact trench 3-2. Depositing passivation layers on the source electrode 10, the first gate electrode 11-1 and the second gate electrode 11-2, and forming a passivation structure 12 through a photolithography process and an etching process; and evaporating a Ti/Ni/Ag metal layer on the surface of the N+ type silicon substrate 1, which is far away from the N-type drift region 2, to form a drain electrode 13, thereby completing the preparation of the split gate trench MOSFET device.
Fig. 13 is a graph showing the input/output characteristics of a conventional split gate trench MOSFET device, and fig. 14 is a graph showing the input/output characteristics of a split gate trench MOSFET device according to the present invention.
As shown in fig. 13 and 14, the device drain-source voltage Vds is in the lateral direction, the drain current Id is in the longitudinal direction, the curves are drain current variation curves as the Vgs voltage increases from bottom to top, and the curves in fig. 13 and 14 are drain current variation curves of the conventional split gate trench MOSFET device and the split gate trench MOSFET device of the present invention when the gate-source voltage Vgs is 3V, 4V, 5V, 6V, 7V, 8V, 9V, 10V, respectively. Compared with the traditional split gate trench MOSFET device, the input-output characteristic curve of the invention has the advantages that the inter-trench shielding barrier generated by the traditional split gate structure under the high drain-source voltage Vds has a shielding effect on the MOSFET channel voltage, so that the potential difference Vds 'at the two ends of the device channel is close to saturation and is lower than the channel pinch-off voltage Vgs-Vth, the MOSFET device always works in a variable resistance area on the input-output characteristic curve, the output current is close to saturation relative to the increase of Vgs, the increasing current of Vds can be linearly increased along with the actual voltage Vds' at the two ends of the channel according to the transconductance value of the corresponding variable resistance area, and the transconductance value of the current of the split gate trench MOSFET device under the high Vds voltage is gradually reduced and the linear output characteristic is deteriorated.
The SGT MOSFET device is provided with the first gate electrode and the second gate electrode, realizes series voltage division, introduces gradual change Vgs voltage in the direction of a cell groove, enables an actual potential difference Vds 'generated at two ends of a device channel by utilizing the separation gate groove MOSFET device to enable a high drain source voltage Vds to approach saturation, and enables a MOSFET cell at the second gate electrode side with lower gate source potential to meet the actual potential difference Vds' at two ends of the channel in a relatively lower Vds voltage interval so as to generate channel pinch-off, enter a saturated working area of an input-output characteristic curve of the MOSFET device and enable the device to have good transconductance stability and linear output characteristics.
The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A split gate trench MOSFET device, comprising: an N+ type silicon substrate, an N-type drift region, a cell trench, a source polysilicon contact trench, a first gate electrode, a second gate electrode, a source electrode and a drain electrode;
the N-type drift region is arranged on the N+ type silicon substrate, the cell groove and the source polycrystalline silicon contact groove are arranged on the N-type drift region, the first gate electrode, the second gate electrode and the source electrode are arranged on a metal layer on the surface of the cell groove, and the drain electrode is arranged on a metal layer on the surface, far away from the N-type drift region, of the N+ type silicon substrate;
a first source polycrystalline silicon structure is arranged in the primitive cell groove, grid polycrystalline silicon structures are arranged around the first source polycrystalline silicon structure, and a second source polycrystalline silicon structure is arranged in the source polycrystalline silicon contact groove;
the first gate electrode and the second gate electrode are connected in series through the gate polysilicon structure, and the second gate electrode is also connected in series with the source electrode through the second source polysilicon structure.
2. The split gate trench MOSFET device of claim 1, wherein the cell trench and the source polysilicon contact trench are periodically arranged in a number ratio (15-30): 1.
3. The split gate trench MOSFET device of claim 1, wherein a bottom oxide layer is disposed between the first source polysilicon structure and the source polysilicon contact trench and the second source polysilicon structure within the cell trench.
4. The split-gate trench MOSFET device of claim 3, wherein said first source polysilicon structure is formed by performing a photolithographic process, a back-etching process, on polysilicon deposited in said cell trench;
the second source polysilicon structure is formed by performing a photolithography process on polysilicon deposited in the source polysilicon contact trench.
5. The split-gate trench MOSFET device of claim 1, wherein an oxide layer is disposed on both the first source polysilicon structure and the second source polysilicon structure;
and gate oxide layer structures are arranged on the side walls of the two sides of the primitive cell groove above the oxide layer.
6. The split gate trench MOSFET device of claim 1, wherein a surface of the gate polysilicon structure is provided with a shield oxide layer;
and the P base region is formed by performing global boron ion implantation on the wafer on which the shielding oxide layer is formed.
7. The split gate trench MOSFET device of claim 6, wherein the P base surface is provided with an n+ implant layer;
and the N+ type injection layer is formed by carrying out arsenic ion injection on the surface of the P base region.
8. The split gate trench MOSFET device of claim 7, wherein a dielectric oxide layer is further provided on the surface of the n+ implant layer;
and forming a metal electrode contact hole through a photoetching process on the dielectric oxide layer, wherein the grid polycrystalline silicon structure and the second grid electrode on the second source polycrystalline silicon structure are connected through the metal electrode contact hole.
9. A method of fabricating a split gate trench MOSFET device as claimed in any one of claims 1 to 8, comprising:
an N+ type silicon substrate is selected as a wafer, an N-type epitaxial layer is deposited on the N+ type silicon substrate to serve as an N-type drift region, a photoetching process and an etching process are carried out on the N-type drift region, and a groove is formed, wherein the groove comprises a primitive cell groove and a source polycrystalline silicon contact groove; the number of the primitive cell grooves and the number of the source polycrystalline silicon contact grooves are periodically arranged in a ratio of (15-30): 1;
forming a bottom oxide layer in the primordial cell groove and the source polycrystalline silicon contact groove through thermally growing an oxide layer by a thermal oxidation process;
depositing polysilicon on the bottom oxide layer, in the cell groove and in the source polysilicon contact groove, and removing redundant polysilicon higher than the surfaces of the bottom oxide layer, the cell groove and the source polysilicon contact groove; carrying out back etching on the polysilicon of the back etching area of the intrinsic pole polysilicon of the primitive cell groove by adopting a photoetching process and an etching process, and not carrying out back etching on the polysilicon of the area outside the back etching area of the intrinsic pole polysilicon of the primitive cell groove to form a first source polysilicon structure; the whole polysilicon deposited in the source polysilicon contact groove is not etched back, so that a second source polysilicon structure is formed;
removing the bottom oxide layer on the side wall of the primitive cell groove to a preset etching depth of the first source polycrystalline silicon structure by adopting a photoetching process and an etching process; thermally growing an oxide layer on the surfaces of the first source polycrystalline silicon structure and the second source polycrystalline silicon structure through an oxidation process, and forming a gate oxide layer structure on the side walls of the two sides of the primitive cell groove above the oxide layer by adopting a dry oxygen oxidation process;
polysilicon deposition is carried out on the primitive cell groove and the source polysilicon contact groove, polysilicon higher than the surface of the groove is removed, a grid polysilicon structure is formed in a back etching area of the first source polysilicon structure, and the grid polysilicon structure surrounds the periphery of the first source polysilicon structure; performing a dry-oxygen oxidation process on the surface of the grid polycrystalline silicon structure to form a shielding oxide layer;
thinning the shielding oxide layer, and performing global boron ion implantation on a wafer on which the shielding oxide layer is formed to form a P base region;
carrying out arsenic ion implantation on the surface of the P base region to form an N+ type ion implantation region, and then carrying out ion implantation annealing to form an N+ type implantation layer;
depositing a dielectric oxide layer on the wafer on which the N+ type injection layer is formed; forming a metal electrode contact hole on the dielectric oxide layer through a photoetching process, forming a first type source polycrystalline silicon contact hole in a source polycrystalline silicon non-etching area in the primitive cell groove, forming a first grid contact hole in a source polycrystalline silicon etching area in the primitive cell groove, forming a first grid contact hole and a first type second grid contact hole in the source polycrystalline silicon etching area in the primitive cell groove, and forming a second type second grid contact hole and a second type source polycrystalline silicon contact hole in a second source polycrystalline silicon structure in the source polycrystalline silicon contact groove;
silicon back etching is carried out through the metal electrode contact hole to form an N+ source region, a BF2 implantation process of the source electrode contact region is carried out, and annealing is carried out after implantation; depositing an AlSiCu metal layer on the upper surface of the wafer with the metal electrode contact hole, and forming a source electrode, a first gate electrode and a second gate electrode through a photoetching process and an etching process;
the first gate electrode is connected in series through the first gate contact hole, the first type second gate contact hole and the source polycrystalline silicon structure in the primitive cell groove; the second gate electrode is connected in series through the second type source polycrystalline silicon contact hole, the second type second gate contact hole and the second type source polycrystalline silicon, and the first type source polycrystalline silicon contact hole is connected with the source electrode;
depositing passivation layers on the source electrode, the first gate electrode and the second gate electrode, and forming a passivation structure through a photoetching process and an etching process; and evaporating a Ti/Ni/Ag metal layer on the surface of the N+ type silicon substrate far away from the N-type drift region to form a drain electrode.
10. The method for manufacturing a split gate trench MOSFET device according to claim 9, wherein: the depth of the cell groove and the source polycrystalline silicon contact groove is 4-7 mu m, and the width of the cell groove and the source polycrystalline silicon contact groove is 1.0-1.8 mu m;
the thickness of the bottom oxide layer is 0.4-0.9 mu m;
the thickness of the gate oxide layer structure is 0.04-0.09 mu m;
forming the P base region, wherein the implantation energy of the boron ions is 80-150 KeV, and the implantation dosage is 1.3E13-2.1E13;
when the N+ type injection layer is formed, the annealing temperature is 950-1000 ℃ and the annealing time is 90-120 min;
in the BF2 implantation process, the implantation energy is 60-80 KeV, the implantation dosage is 3E 14-5E 14, the annealing temperature is 900-1000 ℃, and the annealing time is 20-30 min.
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