CN111180510A - Semiconductor power device structure and manufacturing method thereof - Google Patents
Semiconductor power device structure and manufacturing method thereof Download PDFInfo
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- CN111180510A CN111180510A CN202010100170.2A CN202010100170A CN111180510A CN 111180510 A CN111180510 A CN 111180510A CN 202010100170 A CN202010100170 A CN 202010100170A CN 111180510 A CN111180510 A CN 111180510A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 143
- 238000000926 separation method Methods 0.000 claims abstract description 114
- 229920005591 polysilicon Polymers 0.000 claims abstract description 111
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims description 52
- 238000000151 deposition Methods 0.000 claims description 28
- 238000005530 etching Methods 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 13
- 238000001039 wet etching Methods 0.000 claims description 8
- 150000002500 ions Chemical class 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 230000003071 parasitic effect Effects 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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Abstract
The invention discloses a semiconductor power device structure and a manufacturing method thereof, and the semiconductor power device structure comprises a substrate of a first conduction type and an epitaxial layer of the first conduction type, wherein a well region of a second conduction type is arranged at the upper part of the epitaxial layer, control gate grooves are arranged among the well regions, separation gate grooves are arranged at the bottoms of the control gate grooves, separation gate polycrystalline silicon and separation gate oxide layers wrapping the side surfaces and the bottom surfaces of the separation gate polycrystalline silicon are filled in the separation gate grooves, gate oxide layers are arranged on the side walls and the bottom walls of the control gate grooves, the gate oxide layers cover the separation gate polycrystalline silicon and the tops of the separation gate oxide layers, and gate polycrystalline silicon is arranged at the side walls of the control gate grooves formed by the gate oxide; the inner side of the gate polysilicon is positioned in the region outside the side wall of the separation gate polysilicon. The parasitic capacitance between the source electrode and the grid electrode is extremely small, the risk of leakage current between the source electrode and the grid electrode is greatly reduced, the problem of the traditional separation grid MOSFET is solved, and the reliability of the device is improved besides the characteristic of the device.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor power device structure and a manufacturing method thereof.
Background
The trench power MOSFET is a high-efficiency switching device newly developed after a planar VDMOS, and is widely applied to the field of power electronics due to the advantages of high input impedance, small driving current, high switching speed, good high-temperature characteristic and the like. The high breakdown voltage, the large current and the low on-resistance are the most critical indexes of the power MOSFET, the breakdown voltage is related to the on-resistance value, the high breakdown voltage and the low on-resistance cannot be obtained simultaneously in the MOSFET design process, and the high breakdown voltage and the low on-resistance need to be mutually balanced.
Compared with the common trench MOSFET structure, the novel split gate MOSFET device has the main characteristic that a deep trench split gate which is in short circuit with a source electrode is added, and then the effect of improving the withstand voltage of the device is achieved by utilizing a transverse electric field between the split gates.
At present, mainly, a split-gate MOSFET device mainly has two structures, namely an upper-lower split gate and a left-right split gate, as shown in fig. 1 and fig. 2, in the two types of split-gate devices, an inner-poly oxide (IPO) always exists between a gate polysilicon and a split-gate polysilicon, and the current manufacturing process easily causes the inter-poly oxide to be very thin, which results in poor insulation between a source and a gate, increased leakage current, and easily causes an excessively large overlapping area between the gate polysilicon and the split-gate polysilicon, which results in a large increase in parasitic capacitance between the source and the gate.
Disclosure of Invention
The invention aims to provide a novel semiconductor power device structure and a manufacturing method thereof, and the grid polysilicon and the separation grid polysilicon of the invention have no overlapping region, so that the parasitic capacitance between a source electrode and a grid electrode is extremely small, the risk of leakage current between the source electrode and the grid electrode is greatly reduced, the problems generated by the traditional separation grid MOSFET are solved, the device characteristics are improved, and the device reliability is also improved.
In order to achieve the above object, an aspect of the present invention provides a semiconductor power device structure, which includes an active region, the active region includes a plurality of device cell units connected in parallel, each device cell unit includes a substrate of a first conductivity type and an epitaxial layer of the first conductivity type on the substrate, a well region of a second conductivity type is disposed on an upper portion of the epitaxial layer,
a control gate groove is arranged in the trap region, the control gate groove extends from the surface of the epitaxial layer to the interior of the epitaxial layer, a separation gate groove is arranged at the bottom of the control gate groove, separation gate polycrystalline silicon and a separation gate oxide layer wrapping the side surface and the bottom surface of the separation gate polycrystalline silicon are filled in the separation gate groove, gate oxide layers are arranged on the side wall and the bottom wall of the control gate groove, the gate oxide layers cover the top of the separation gate polycrystalline silicon and the top of the separation gate oxide layer, and gate polycrystalline silicon is arranged on the side wall of the control gate groove formed by the gate oxide layers;
the inner side of the gate polysilicon is positioned in the region outside the side wall of the separation gate polysilicon.
Preferably, the control gate trench is covered with an insulating medium layer, the insulating medium layer is covered with source metal, a source region of the first conductivity type is arranged at the upper part in the well region, the source metal is filled in a contact hole between the source regions, and the source metal is electrically connected with the split gate polysilicon in the split gate trench.
Preferably, the semiconductor device further comprises a gate metal electrically connected with the gate polysilicon through the gate polysilicon contact hole.
Preferably, the source region is adjacent to the control gate trench, and the source metal is isolated from the gate polysilicon in the control gate trench by an insulating dielectric layer.
Preferably, the depth of the separation gate trench is greater than that of the control gate trench, and the depth of the control gate trench is not less than the junction depth of the well region.
Preferably, a drain metal is provided on a lower surface of the substrate, and the drain metal is in ohmic contact with the substrate.
In another aspect, the present invention provides a method for manufacturing a semiconductor power device structure, including the following steps:
the method comprises the steps of firstly, selecting a substrate of a first conductivity type, and forming an epitaxial layer of the first conductivity type on the substrate, wherein the upper surface of the epitaxial layer is a first main surface, and the lower surface of the substrate is a second main surface.
Depositing a first insulating layer on the first main surface, and etching the first insulating layer and the epitaxial layer by adopting a photoetching process to form a control gate groove; the first insulating layer is a hard mask, preferably, the first insulating layer is silicon oxide, and the depth of the control gate trench is 0.5-1.5 micrometers.
And thirdly, depositing a second insulating layer in the control gate groove, wherein the second insulating layer extends to the surface of the first insulating layer, and preferably, depositing the second insulating layer in a Chemical Vapor Deposition (CVD) mode, wherein the second insulating layer is silicon oxide or silicon nitride.
Etching the second insulating layer, and reserving the second insulating layer on the side wall of the control gate groove; specifically, the second insulating layer on the surface of the first insulating layer is etched, and the second insulating layer on the bottom wall of the control gate trench is etched along the side wall edge of the second insulating layer on the side wall of the control gate trench, so that the bottom wall of the control gate trench is exposed.
And fifthly, etching the exposed epitaxial layer at the bottom of the control gate groove, forming a separation gate groove in the epitaxial layer, wherein the separation gate groove is communicated with the control gate groove, and preferably, the depth of the separation gate groove is 2-6 microns.
Sixthly, removing the first insulating layer and the second insulating layer in a wet etching mode;
and step seven, depositing a separation gate oxide layer in the control gate groove and the separation gate groove, wherein the separation gate oxide layer with a thickness of one layer is formed on the surface of the structure formed in the step five, the separation gate oxide layer extends to the first main surface, preferably, the separation gate oxide layer is formed in a thermal oxidation mode, the separation gate oxide layer is silicon oxide, and the thickness of the separation gate oxide layer is 1000-8000 angstroms.
Eighthly, depositing first polysilicon in the control gate groove and the separation gate groove; preferably, a first polysilicon is deposited by Low Pressure Chemical Vapor Deposition (LPCVD), which fills the split gate trenches and the control gate trenches.
Step nine, carrying out back etching on the first polycrystalline silicon to enable the surface of the first polycrystalline silicon to be positioned at the opening of the separation gate groove to form separation gate polycrystalline silicon;
and step ten, removing the separated gate oxide layer in the control gate groove in a wet etching mode, and simultaneously removing the separated gate oxide layer on the first main surface, wherein the separated gate oxide layer on the top of the separated gate groove is partially corroded in the wet etching mode, so that the separated gate oxide layer is lower than the surfaces of the separated gate polycrystalline silicon and the separated gate groove.
And step eleven, etching the separation gate polycrystalline silicon and the epitaxial layer positioned at the bottom of the control gate groove to enable the surfaces of the separation gate oxide layer, the separation gate polycrystalline silicon and the separation gate groove to be flush.
Step twelve, forming a gate oxide layer in the control gate trench, wherein the gate oxide layer extends to the first main surface and covers the separation gate polysilicon and the separation gate oxide layer; preferably, the gate oxide layer is formed by thermal oxidation, and the gate oxide layer is silicon oxide.
Thirteen, depositing second polysilicon in the control gate groove formed by the gate oxide layer;
and fourteen, carrying out back etching on the second polysilicon to reserve the second polysilicon positioned on the side wall of the control gate groove and form gate polysilicon. Specifically, the second polysilicon on the first main surface is etched, and the second polysilicon on the bottom wall of the control gate trench is etched along the side wall edge of the second polysilicon on the side wall of the control gate trench, so that the second polysilicon on the side wall of the control gate trench is reserved, and the gate polysilicon is formed.
Preferably, step thirteen is specifically: and depositing second polysilicon in a control gate groove formed by the gate oxide layer, wherein the surface of the second polysilicon is provided with a concave notch, and the side wall of the concave notch is positioned outside the side wall of the separation gate polysilicon.
Preferably, after the fourteenth step, the method further comprises:
step fifteen, second conductive type ions are injected into the first main surface and pushed to form a well region of the second conductive type, and the depth of the control gate groove is not less than the junction depth of the well region, so that the gate polysilicon covers the well region from the side.
Sixthly, implanting first conductive type ions into the first main surface, and annealing to form a source region of the first conductive type, wherein the source region is covered by the gate polysilicon from the side surface.
Seventhly, depositing an insulating medium layer in the control gate groove and on the surface of the epitaxial layer, and then etching the insulating medium layer by adopting a photoetching process to form a contact hole, wherein the contact hole penetrating through the source region extends into the well region.
Eighteen, depositing a metal layer on the insulating medium layer and in the contact hole, and etching the metal layer to obtain the source metal.
And nineteenth, depositing metal on the second main surface to obtain drain metal.
Preferably, the contact hole in the seventeenth step further includes a gate polysilicon contact hole and a separation gate polysilicon contact hole;
and eighteen, etching the metal layer to obtain grid metal, wherein the grid metal is electrically connected with the grid polysilicon through a grid polysilicon contact hole, and the source metal is electrically connected with the separation grid polysilicon through a separation grid polysilicon contact hole.
Compared with the prior art, the invention has the following beneficial effects:
(1) according to the invention, no overlapping area exists between the grid polysilicon and the separation grid polysilicon, the parasitic capacitance between the source electrode and the grid electrode is extremely low, the risk of leakage current between the source electrode and the grid electrode is greatly reduced, the problems generated by the traditional separation grid MOSFET are solved, and the reliability of the device is improved besides the improvement of the device characteristics.
(2) In the traditional separation gate MOSFET, for an upper separation gate MOSFET and a lower separation gate MOSFET, a separation gate groove and a control gate groove are both manufactured in the same large groove, so that the width of the control gate groove is limited; for the left and right type separation gate MOSFET, the transverse width of the gate polysilicon is narrower, so that the etching difficulty of the control gate contact hole is increased. In the structure of the invention, the control grid groove is wider than the existing structure, and because the overlapping area is not arranged between the grid polycrystalline silicon and the separation grid polycrystalline silicon, the width of the grid polycrystalline silicon can be increased by increasing the thickness of the second insulating layer in the manufacturing process, so that the grid polycrystalline silicon and the separation grid polycrystalline silicon can be directly used as leading-out holes from the corresponding grooves, and the width of the control grid groove can be randomly set.
Drawings
FIG. 1 is a schematic cross-sectional view of a prior art top and bottom split gate MOSFET;
FIG. 2 is a schematic cross-sectional view of a prior art left-right split-gate MOSFET;
FIG. 3 is a schematic cross-sectional view of a device structure of the present invention;
fig. 4A to 4S are schematic cross-sectional views illustrating a manufacturing method of the present invention.
In the figure: 1. a substrate; 2. an epitaxial layer; 3. a well region; 4. a control gate trench; 5. separating the gate trench; 6. separating the gate polysilicon; 7. separating the gate oxide layer; 8. a gate oxide layer; 9. grid polysilicon; 10. an insulating dielectric layer; 11. a source metal; 12. a source region; 13. a drain metal; 14. a first insulating layer; 15. a second insulating layer; 16. an inter-polysilicon spacer oxide layer; 17. a concave notch; 001. a first major face; 002. a second major surface.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 3 shows a cross-sectional view of the semiconductor power device structure of this embodiment, taking an N-type device as an example, which includes an active region, the active region includes a plurality of device cell units connected in parallel, the device cell units include a heavily doped N + -type substrate 1 and a lightly doped N-type epitaxial layer 2 located on the N + -type substrate 1, a P-type well region 3 is disposed on an upper portion of the N-type epitaxial layer 2,
the inner side of the gate polysilicon 9 is located in the region outside the sidewall of the split gate polysilicon 6, wherein the side of the gate polysilicon 9 facing the inside of the control gate trench 4 is the inner side. It is understood that the gate polysilicon 9 has no overlapping area with the split gate polysilicon 6, and the gate polysilicon 9 is disposed outside the split gate polysilicon 6, so there is no overlapping area in the horizontal direction; the gate polysilicon 9 is arranged above the separation gate polysilicon 6, so that no overlapping region exists in the vertical direction, and therefore, in the horizontal direction and the vertical direction, no overlapping region exists between the gate polysilicon 9 and the separation gate polysilicon 6 in the embodiment of the invention, so that the parasitic capacitance between the source and the gate is extremely small, the risk of leakage current between the source and the gate is greatly reduced, the problem of the conventional separation gate MOSFET is solved, and the reliability of the device is improved besides the improvement of the device characteristics.
An insulating medium layer 10 covers the control gate trench 4, a source metal 11 covers the insulating medium layer 10, an N + type source region 12 is arranged at the upper part in the well region 3, the source metal 11 is filled in a contact hole between the source regions 12, and the source metal 11 is electrically connected with the separation gate polysilicon 6 in the separation gate trench 5; and arranging drain metal 13 on the lower surface of the N + type substrate 1, wherein the drain metal 13 is in ohmic contact with the N + type substrate 1.
The N + type source region 12 is adjacent to the control gate trench 4, and the source metal 11 is isolated from the gate polysilicon 9 in the control gate trench 4 by an insulating dielectric layer 10.
In the embodiment of the present invention, the depth of the split gate trench 5 is greater than the depth of the control gate trench 4, and the depth of the control gate trench 4 is not less than the junction depth of the well region 3.
Embodiments of the present invention further include a gate metal (not shown) electrically connected to the gate polysilicon 9 through a gate polysilicon contact hole.
Fig. 4A to 4S show a method for manufacturing a semiconductor power device structure according to an embodiment of the present invention, including the steps of:
step one, as shown in fig. 4A, a heavily doped N + type substrate 1 is selected, a lightly doped N-type epitaxial layer 2 is formed on the N + type substrate 1, an upper surface of the N-type epitaxial layer 2 is a first main surface 001, and a lower surface of the N + type substrate 1 is a second main surface 002.
Step two, as shown in fig. 4B, depositing a first insulating layer 14 on the first main surface 001, and etching the first insulating layer 14 and the N-type epitaxial layer 2 by using the first insulating layer 14 as a hard mask through a photolithography process to form a control gate trench 4; preferably, the first insulating layer 14 is silicon oxide; preferably, the depth of the control gate trench 4 is 0.5-1.5 μm.
Step three, as shown in fig. 4C, depositing a second insulating layer 15 in the control gate trench 4, wherein the second insulating layer 15 extends to the surface of the first insulating layer 14, and preferably, depositing the second insulating layer 15 by Chemical Vapor Deposition (CVD), wherein the second insulating layer 15 is silicon oxide or silicon nitride.
Step four, as shown in fig. 4D, etching the second insulating layer 15, and reserving the second insulating layer 15 on the sidewall of the control gate trench 4; specifically, the second insulating layer 15 on the surface of the first insulating layer 14 is etched, and the second insulating layer 15 on the bottom wall of the control gate trench 4 is etched along the sidewall edge of the second insulating layer 15 on the sidewall of the control gate trench 4, so that the bottom wall of the control gate trench 4 is exposed.
Step five, as shown in fig. 4E, etching the exposed N-type epitaxial layer 2 at the bottom of the control gate trench 4, forming a separation gate trench 5 inside the N-type epitaxial layer 2, wherein the separation gate trench 5 is communicated with the control gate trench 4; preferably, the depth of the separation gate trench 5 is 2 to 6 micrometers. In the present embodiment, the top of the split gate trench 5 is the bottom of the control gate trench 4.
And sixthly, as shown in fig. 4F, removing the first insulating layer 14 and the second insulating layer 15 by wet etching.
Step seven, as shown in fig. 4G, depositing a separation gate oxide layer 7 on the surface of the control gate trench 4 and the separation gate trench 5, it can be understood that a thick separation gate oxide layer 7 is formed on the surface of the structure formed in step five, the separation gate oxide layer 7 extends to the first main surface 001, preferably, the separation gate oxide layer 7 is formed in a thermal oxidation manner, the separation gate oxide layer 7 is silicon oxide, and the thickness of the separation gate oxide layer 7 is 1000-8000 angstroms.
Step eight, as shown in fig. 4H, depositing first polysilicon in the control gate trench 4 and the split gate trench 5; preferably, a first polysilicon is deposited by LPCVD, which fills the split gate trenches 5 and the control gate trenches 4.
Step nine, as shown in fig. 4I, the first polysilicon is etched back, so that the surface of the first polysilicon is located at the opening of the split gate trench 5, and the split gate polysilicon 6 is formed.
Step ten, as shown in fig. 4J, the separation gate oxide layer 7 on the surface of the control gate trench 4 is removed in a wet etching manner, and simultaneously the separation gate oxide layer 7 on the first main surface 001 is also removed, and the wet etching manner can etch part of the separation gate oxide layer 7 on the top of the separation gate trench 5, so that the separation gate oxide layer 7 is lower than the surfaces of the separation gate polysilicon 6 and the separation gate trench 5. The dotted line portion in fig. 4J shows a portion of the split gate oxide layer 7 lower than the split gate trench 5.
Step eleven, as shown in fig. 4K, etching the separation gate polysilicon 6 and the N-type epitaxial layer 2 positioned at the bottom of the control gate trench 4 in a dry etching manner so as to enable the surfaces of the separation gate oxide layer 7, the separation gate polysilicon 6 and the separation gate trench 5 to be flush; in this process, the N-type epitaxial layer 2 on the first main surface is also etched at the same time.
Step twelve, as shown in fig. 4L, forming a gate oxide layer 8 in the control gate trench 4, wherein the gate oxide layer 8 extends to the first main surface 001, and the gate oxide layer 8 covers the separation gate polysilicon 6 and the separation gate oxide layer 7; preferably, the gate oxide layer 8 is formed by thermal oxidation, and the gate oxide layer 8 is silicon oxide.
Thirteenth, as shown in fig. 4M, depositing a second polysilicon in the control gate trench 4 formed by the gate oxide layer 8, where the surface of the second polysilicon has a concave notch 17, and a sidewall of the concave notch 17 is located outside a sidewall of the separation gate polysilicon 6, that is, a sidewall of the concave notch 17 is located outside an inner wall of the separation gate oxide layer 7, as shown by a dotted line in fig. 4M; preferably, the second polysilicon is deposited by LPCVD.
Fourteenth, as shown in fig. 4N, the second polysilicon is etched back to retain the second polysilicon on the sidewall of the control gate trench 4, so as to form a gate polysilicon 9; specifically, the second polysilicon on the first main surface 001 is etched, and the second polysilicon on the bottom wall of the control gate trench 4 is etched along the sidewall edge of the second polysilicon on the sidewall of the control gate trench 4, so as to retain the second polysilicon on the sidewall of the control gate trench 4, thereby forming the gate polysilicon 9.
In a preferred embodiment, after the fourteenth step, the method further includes:
fifteenth, as shown in fig. 4O, P-type ions are implanted into the first main surface 001 and pushed into the well to form a P-type well region 3, and the depth of the control gate trench 4 is not less than the junction depth of the well region 3, which can be understood that the gate polysilicon 9 laterally covers the well region 3.
Sixthly, as shown in fig. 4P, N-type ions are implanted into the first main surface 001, and annealing is performed to form an N + -type source region 12, where the N + -type source region 12 is located on the surface of the P-type well region 3, and the gate polysilicon 9 covers the source region 12 from the side surface.
Seventhly, as shown in fig. 4Q, depositing an insulating medium layer 10 in the control gate trench 4 and on the surface of the N-type epitaxial layer 2, and then etching the insulating medium layer 10 by using a photolithography process to form a contact hole, wherein the contact hole penetrating through the source region 12 extends into the well region 3, and the contact hole further includes a gate polysilicon contact hole and a separation gate polysilicon contact hole.
Eighteen, as shown in fig. 4R, depositing a metal layer on the insulating dielectric layer 10 and in the contact hole, etching the metal layer to obtain a source metal 11 and a gate metal, wherein the source metal 11 is in ohmic contact with the N + type source region 12, the source metal 11 is electrically connected to the split gate polysilicon 6 through the split gate polysilicon contact hole, and the gate metal is electrically connected to the gate polysilicon 9 through the gate polysilicon contact hole. In this embodiment, the gate metal, the gate polysilicon contact hole and the split gate polysilicon contact hole are not shown, which is well known to those skilled in the art and will not be described herein.
Nineteenth, as shown in fig. 4S, depositing metal on the second main surface 002 to obtain the drain metal 13, and making ohmic contact between the drain metal 13 and the N + -type substrate 1 to complete the semiconductor power device according to the embodiment of the present invention.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (10)
1. A semiconductor power device structure comprises an active area, wherein the active area comprises a plurality of device cell units which are connected in parallel, each device cell unit comprises a substrate of a first conduction type and an epitaxial layer of the first conduction type positioned on the substrate, and a well region of a second conduction type is arranged on the upper part of the epitaxial layer, and the semiconductor power device structure is characterized in that:
a control gate groove is arranged in the trap region, the control gate groove extends from the surface of the epitaxial layer to the interior of the epitaxial layer, a separation gate groove is arranged at the bottom of the control gate groove, separation gate polycrystalline silicon and a separation gate oxide layer wrapping the side surface and the bottom surface of the separation gate polycrystalline silicon are filled in the separation gate groove, gate oxide layers are arranged on the side wall and the bottom wall of the control gate groove, the gate oxide layers cover the top of the separation gate polycrystalline silicon and the top of the separation gate oxide layer, and gate polycrystalline silicon is arranged on the side wall of the control gate groove formed by the gate oxide layers;
the inner side of the gate polysilicon is positioned in the region outside the side wall of the separation gate polysilicon.
2. The semiconductor power device structure of claim 1, wherein the control gate trench is covered with an insulating dielectric layer, the insulating dielectric layer is covered with a source metal, a source region of the first conductivity type is disposed at an upper portion in the well region, the source metal is filled in a contact hole between the source regions, and the source metal is electrically connected to the split gate polysilicon in the split gate trench.
3. The semiconductor power device structure of claim 2, further comprising a gate metal electrically connected to the gate polysilicon through a gate polysilicon contact hole.
4. The semiconductor power device structure of claim 2, wherein the source region is adjacent to the control gate trench, and the source metal is isolated from the gate polysilicon in the control gate trench by an insulating dielectric layer.
5. The semiconductor power device structure of claim 1, wherein a depth of the separation gate trench is greater than a depth of the control gate trench, and the depth of the control gate trench is not less than a junction depth of the well region.
6. The semiconductor power device structure of claim 1, wherein a drain metal is disposed on a lower surface of the substrate, the drain metal in ohmic contact with the substrate.
7. A manufacturing method of a semiconductor power device structure is characterized by comprising the following steps:
the method comprises the steps of firstly, selecting a substrate of a first conductive type, and forming an epitaxial layer of the first conductive type on the substrate, wherein the upper surface of the epitaxial layer is a first main surface, and the lower surface of the substrate is a second main surface;
depositing a first insulating layer on the first main surface, and etching the first insulating layer and the epitaxial layer by adopting a photoetching process to form a control gate groove;
depositing a second insulating layer in the control gate groove;
etching the second insulating layer, and reserving the second insulating layer on the side wall of the control gate groove;
etching the exposed epitaxial layer at the bottom of the control gate groove, and forming a separation gate groove in the epitaxial layer;
sixthly, removing the first insulating layer and the second insulating layer in a wet etching mode;
step seven, depositing a separation gate oxide layer in the control gate groove and the separation gate groove;
eighthly, depositing first polysilicon in the control gate groove and the separation gate groove;
step nine, carrying out back etching on the first polycrystalline silicon to enable the surface of the first polycrystalline silicon to be positioned at the opening of the separation gate groove to form separation gate polycrystalline silicon;
step ten, removing the separated gate oxide layer in the control gate groove in a wet etching mode;
step eleven, etching the separation gate polycrystalline silicon and the epitaxial layer positioned at the bottom of the control gate groove to enable the surfaces of the separation gate oxide layer, the separation gate polycrystalline silicon and the separation gate groove to be flush;
step twelve, forming a gate oxide layer in the control gate trench, wherein the gate oxide layer covers the separation gate polysilicon and the separation gate oxide layer;
thirteen, depositing second polysilicon in the control gate groove formed by the gate oxide layer;
and fourteen, carrying out back etching on the second polysilicon to reserve the second polysilicon positioned on the side wall of the control gate groove and form gate polysilicon.
8. The manufacturing method according to claim 7, wherein step thirteen is specifically: and depositing second polysilicon in a control gate groove formed by the gate oxide layer, wherein the surface of the second polysilicon is provided with a concave notch, and the side wall of the concave notch is positioned outside the side wall of the separation gate polysilicon.
9. The manufacturing method according to claim 7, characterized by, after step fourteen, further comprising:
fifteenth, second conductive type ions are injected into the first main surface and pushed to form a well region of the second conductive type, and the depth of the control gate groove is not less than the junction depth of the well region;
sixthly, implanting first conductive type ions into the first main surface, and annealing to form a first conductive type source region, wherein the gate polysilicon covers the source region from the side surface;
seventhly, depositing an insulating medium layer, and etching the insulating medium layer by adopting a photoetching process to form a contact hole, wherein the contact hole penetrating through the source region extends into the well region;
eighteen, depositing a metal layer on the insulating medium layer and in the contact hole, and etching the metal layer to obtain source metal;
and nineteenth, depositing metal on the second main surface to obtain drain metal.
10. The manufacturing method according to claim 9, wherein the contact hole in the seventeenth step further comprises a gate polysilicon contact hole and a split gate polysilicon contact hole;
and eighteen, etching the metal layer to obtain grid metal, wherein the grid metal is electrically connected with the grid polysilicon through a grid polysilicon contact hole, and the source metal is electrically connected with the separation grid polysilicon through a separation grid polysilicon contact hole.
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| CN117153885A (en) * | 2023-09-15 | 2023-12-01 | 陕西亚成微电子股份有限公司 | Split gate trench MOSFET device and method of making |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117153885A (en) * | 2023-09-15 | 2023-12-01 | 陕西亚成微电子股份有限公司 | Split gate trench MOSFET device and method of making |
| CN117153885B (en) * | 2023-09-15 | 2024-05-28 | 陕西亚成微电子股份有限公司 | Split gate trench MOSFET device and method of making |
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Inventor after: Sun Yantao Inventor after: Huang Jian Inventor after: Gu Yunpu Inventor after: Song Yuehua Inventor after: Wu Pingli Inventor after: Fan Jun Inventor after: Zhang Lina Inventor before: Sun Yantao Inventor before: Huang Jian Inventor before: Chen Zerui Inventor before: Gu Yunpu Inventor before: Song Yuehua Inventor before: Wu Pingli Inventor before: Fan Jun Inventor before: Zhang Lina |