CN111370479A - Trench gate power device and manufacturing method thereof - Google Patents
Trench gate power device and manufacturing method thereof Download PDFInfo
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- CN111370479A CN111370479A CN201811601009.2A CN201811601009A CN111370479A CN 111370479 A CN111370479 A CN 111370479A CN 201811601009 A CN201811601009 A CN 201811601009A CN 111370479 A CN111370479 A CN 111370479A
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- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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Abstract
The invention discloses a trench gate power device, which comprises a device unit area and a terminal area, wherein the terminal area surrounds the periphery of the device unit area, and the device unit area is formed by connecting a plurality of device units in parallel; the terminal structure of the terminal area includes: the terminal trench is filled with a terminal dielectric layer, sequentially penetrates through a channel region, a carrier storage layer and a drift region of the device unit, and has a depth larger than that of a depletion region formed in the drift region when the trench gate power device is reversely biased; the region of the terminal groove is also set as a chip scribing region of the trench gate power device, and the width of the terminal groove meets the requirement value required by withstand voltage and is larger than the requirement value required by chip scribing by adopting photoetching. The invention discloses a manufacturing method of a trench gate power device. The technical problem to be solved by the invention is to provide a trench gate power device, which can greatly reduce the width of a terminal structure, thereby reducing the area of a terminal region.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a trench gate power device; the invention also relates to a manufacturing method of the trench gate power device.
Background
The semiconductor power device is a basic electronic component for controlling and converting energy of a power electronic system, and the continuous development of the power electronic technology develops a wide application field for the semiconductor power device. Semiconductor power devices marked by Insulated Gate Bipolar Transistors (IGBTs) and Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are mainstream devices in the field of power electronics nowadays, wherein an IGBT device is a composite device of a voltage-controlled MOSFET and a Bipolar Junction Transistor (BJT).
The gate structures of the IGBT and the MOSFET include a planar gate and a Trench (Trench) gate, so the gate structures of the existing IGBT and MOSFET are formed by a planar gate or Trench gate process. A trench gate power device such as a trench gate IGBT or a trench gate MOSFET generally includes a device cell region and a termination region, where the termination region surrounds the device cell region; the device unit area is also commonly called an Active area (Active), and is connected with a plurality of device units in parallel, and the device units can generate current flow when working; the termination region forms a termination structure for withstanding a termination voltage and for forming a protection for the device cells in the device cell region. As the voltage of the device increases, the area of the existing termination structure also needs to be increased greatly.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a trench gate power device, which can greatly reduce the width of a terminal structure, thereby reducing the area of a terminal region. Therefore, the invention also provides a manufacturing method of the trench gate power device.
In order to solve the technical problem, the trench gate power device provided by the invention comprises a device unit area and a terminal area, wherein the terminal area surrounds the periphery of the device unit area, and the device unit area is formed by connecting a plurality of device units in parallel; the terminal structure of the terminal area comprises:
and the terminal trench is filled with a terminal dielectric layer, sequentially penetrates through a channel region, a current carrier storage layer and a drift region of the device unit, and has a depth larger than that of a depletion region formed in the drift region when the trench gate power device is reversely biased.
The area of the terminal groove is also set as a chip scribing area of the groove gate power device, and the width of the terminal groove meets the requirement value required by withstand voltage and is larger than the value to be evaluated by adopting photoetching etching to scribe the chip.
In a further improvement, the front structure of the device unit comprises:
the drift region is composed of the first epitaxial layer, and the doping concentration of the first epitaxial layer is set according to the requirements of the drift region.
And the second epitaxial layer is formed on the surface of the first epitaxial layer, has the doping of the first conductivity type, has the doping concentration higher than that of the first epitaxial layer, and is used as a carrier storage layer of the trench gate power device.
And the third epitaxial layer is formed on the surface of the second epitaxial layer, has second conductive type doping, and is used as a channel region of the trench gate power device.
The carrier storage layer and the channel region both adopt epitaxial layer process structures, and the influence of a thermal process in a structure formed by injecting and pushing wells in the carrier storage layer or the channel region on the doping concentration distribution and thickness of the carrier storage layer and the channel region can be prevented, so that the carrier storage layer and the channel region both have a structure with accurately controlled impurity concentration distribution and thickness.
The groove gate comprises a gate groove, a gate dielectric layer and a polysilicon gate, the gate groove penetrates through the channel region, the bottom of the gate groove is positioned in the current carrier storage layer or penetrates through the current carrier storage layer, the gate dielectric layer is formed on the side surface and the bottom surface of the gate groove, the polysilicon gate is filled in the gate groove formed with the gate dielectric layer, and the surface of the channel region covered by the side surface of the polysilicon gate is used for forming a channel.
And the source region consists of a first conduction type heavily doped region formed on the surface of the channel region.
The interlayer film, the contact hole, the source electrode and the grid electrode are formed by patterning the front metal layer.
The contact hole penetrates the interlayer film.
The source region is connected to the source electrode through the contact hole corresponding to the top.
The polysilicon gate is connected to the gate through the corresponding contact hole at the top.
The further improvement is that the trench gate power device is a trench gate IGBT, and comprises the following back structure:
and a collector region consisting of a second conductive type heavily doped region is formed on the back surface of the thinned semiconductor substrate.
And a collector composed of a back metal layer is formed on the back of the collector region.
Or, the trench gate power device is a trench gate MOSFET, and includes the following back structure:
and a drain region consisting of a first conductive type heavily doped region is formed on the back surface of the thinned semiconductor substrate.
And a drain electrode consisting of a back metal layer is formed on the back surface of the drain region.
In a further improvement, the semiconductor substrate is a silicon substrate, and the first epitaxial layer, the second epitaxial layer and the third epitaxial layer are silicon epitaxial layers.
The gate dielectric layer is a gate oxide layer and is formed by adopting a thermal oxidation process.
In a further improvement, the doping concentration of the carrier storage layer is 5e15cm-3～5e17cm-3The thickness is 0.5 to 5 microns; the doping concentration of the channel region is 5e16cm-3～5e17cm-3The thickness is 0.5-3 microns.
In a further improvement, when the trench gate power device is a trench gate IGBT, the back structure of the trench gate power device further includes:
and the field stop layer is doped with the first conduction type and is formed between the drift region and the collector region.
The bottom of the termination trench penetrates into the field stop layer and penetrates through a depletion layer formed in the field stop layer.
In a further refinement, the width of the termination trench is within a few microns.
The further improvement is that the material of the terminal dielectric layer comprises silicon oxide, silicon oxynitride or silicon nitride, and the terminal dielectric layer is a single-layer structure composed of one material or a multi-layer structure composed of more than two materials.
In order to solve the above technical problem, in the method for manufacturing a trench gate power device according to the present invention, the trench gate power device includes a device cell region and a termination region, the device cell region is formed by connecting a plurality of device cells in parallel, the step of forming a front structure of the device cell is performed first until a source region of the front structure of the device cell is formed, and the step of forming the termination structure is performed before forming an interlayer film of the front structure of the device cell as follows, including:
The area of the terminal groove is also set as a chip scribing area of the groove gate power device, and the width of the terminal groove meets the requirement value required by withstand voltage and is larger than the value to be evaluated by adopting photoetching etching to scribe the chip.
And 102, filling a terminal dielectric layer in the terminal groove to form the terminal structure.
In a further refinement, the source region of the front side structure of the device cell is formed by a preceding step comprising:
the method comprises the following steps of firstly, forming a first epitaxial layer with first conductivity type doping on the surface of a semiconductor substrate by adopting an epitaxial growth process, wherein a drift region is composed of the first epitaxial layer, and the doping concentration of the first epitaxial layer is set according to the requirements of the drift region.
And secondly, forming a second epitaxial layer on the surface of the first epitaxial layer by adopting an epitaxial growth process, wherein the second epitaxial layer has the first conductive type doping, the doping concentration of the second epitaxial layer is greater than that of the first epitaxial layer, and the second epitaxial layer is used as a current carrier storage layer of the trench gate power device.
And thirdly, forming a third epitaxial layer on the surface of the second epitaxial layer by adopting an epitaxial growth process, wherein the third epitaxial layer has second conductive type doping, and the third epitaxial layer is used as a channel region of the trench gate power device.
The carrier storage layer and the channel region both adopt epitaxial layer process structures, and the influence of a thermal process in a structure formed by injecting and pushing wells in the carrier storage layer or the channel region on the doping concentration distribution and thickness of the carrier storage layer and the channel region can be prevented, so that the carrier storage layer and the channel region both have a structure with accurately controlled impurity concentration distribution and thickness.
Step four, forming a trench gate, comprising the following sub-steps:
and 41, forming a grid groove by adopting a photoetching process, wherein the grid groove penetrates through the channel region and the current carrier storage layer.
And 42, forming a gate dielectric layer on the side surface and the bottom surface of the gate groove.
And 43, filling polycrystalline silicon into the grid groove formed with the grid dielectric layer to form a polycrystalline silicon grid, wherein the surface of the channel region covered by the side surface of the polycrystalline silicon grid is used for forming a channel.
And fifthly, forming a source region on the surface of the channel region between the trench gates in a self-alignment manner by adopting a first conductive type heavy doping ion implantation process.
Thereafter, step 101 and step 102 are performed.
Then, the following steps are continued:
and step six, forming an interlayer film, a contact hole and a front metal layer, and patterning the front metal layer to form a source electrode and a grid electrode.
The contact hole penetrates the interlayer film.
The source region is connected to the source electrode through the contact hole corresponding to the top.
The polysilicon gate is connected to the gate through the corresponding contact hole at the top.
The further improvement is that the trench gate power device is a trench gate IGBT, and the method comprises the following steps of forming a back structure:
and seventhly, thinning the back of the semiconductor substrate.
And step eight, forming a collector region consisting of a second conductive type heavily doped region on the back of the thinned semiconductor substrate.
And step nine, forming a back metal layer on the back of the collector region and forming a collector by the back metal layer.
Or, the trench gate power device is a trench gate MOSFET, and includes the following steps of forming a back structure:
and seventhly, thinning the back of the semiconductor substrate.
And step eight, forming a drain region consisting of the first conductive type heavily doped region on the back surface of the thinned semiconductor substrate.
And step nine, forming a back metal layer on the back of the drain region and forming a drain electrode by the back metal layer.
A further improvement is that after the back structure is formed, a dicing process is further performed to separate each chip integrated on the same semiconductor substrate into independent chips, and the dicing process includes the steps of:
and photoetching to open a scribing region, wherein the scribing region is positioned in the region of the terminal groove.
And sequentially removing the terminal dielectric layer in the scribing region and removing the structures including the semiconductor substrate at the bottom of the terminal dielectric layer by adopting an etching process, thereby realizing the cutting of each chip.
In a further improvement, the width of the termination trench is within a few microns;
the terminal dielectric layer is made of silicon oxide, silicon oxynitride or silicon nitride, and is of a single-layer structure made of one material or a multi-layer structure made of more than two materials.
In a further improvement, when the trench gate power device is a trench gate IGBT, the back structure of the trench gate power device further includes:
and forming a field stop layer doped with the first conductivity type by adopting a back ion implantation process, wherein the field stop layer is positioned between the drift region and the collector region.
Alternatively, the field stop layer is formed on the surface of the semiconductor substrate by an epitaxial process before being formed on the first epitaxial layer.
The bottom of the termination trench penetrates into the field stop layer and penetrates through a depletion layer formed in the field stop layer.
In a further improvement, the bottom of the contact hole corresponding to the top of the source region also penetrates through the source region and is connected with the channel region at the bottom.
After the opening of the contact hole is formed and before metal filling, forming a well contact region formed by a second conductive type heavily doped region on the surface of the channel region at the bottom of the contact hole corresponding to the top of the source region, wherein the well contact region and the contact hole corresponding to the top form ohmic contact.
The invention makes special design for the terminal structure of the trench gate power device, designs the terminal structure as a structure consisting of a terminal dielectric layer filled in the terminal trench, and makes special arrangement for the terminal trench, wherein the terminal trench sequentially passes through a channel region, a carrier storage layer and a drift region of a device unit in the longitudinal depth, and the depth of the terminal trench is greater than the depth of a depletion region formed in the drift region when the trench gate power device is reversely biased, so that the device unit forming the device unit region can be well protected.
In addition, the width of the terminal groove is specially set, and the width of the terminal groove meets the requirement value required by withstand voltage and simultaneously meets the requirement value which is greater than the requirement value for scribing a chip by adopting photoetching; because the terminal dielectric layer is directly adopted as the terminal structure and the depth of the longitudinal structure of the terminal structure is larger than that of the depletion region, the width of the terminal structure can be reduced under the condition of meeting the same withstand voltage; meanwhile, the terminal groove is also used as a scribing region, so that the minimum value of the reduction of the width of the terminal structure needs to meet the requirement of scribing by adopting photoetching; in short, the invention can greatly reduce the width of the terminal structure, thereby reducing the area of the terminal area. Compared with the width of the terminal structure in the prior structure which is dozens to hundreds of microns, the invention can reduce the width of the terminal structure to be several microns.
In addition, the terminal structure formed by filling the groove and the dielectric layer does not introduce an additional thermal process, and can eliminate the adverse effect of the thermal process of the terminal structure process on the impurity concentration distribution and the thickness of the doped regions of the device unit region, such as a channel region and a carrier storage layer, so that the performance of the device can be stable.
In addition, the invention can also set the structure of the channel region and the carrier storage layer formed by the epitaxial layer in the device unit region, and the epitaxial process does not need to adopt an additional thermal process, thereby accurately controlling the doping concentration, the doping concentration distribution and the thickness of the channel region and the carrier storage layer; compared with the prior art, the method breaks through the limitation that the forming process of the well region and the carrier storage layer corresponding to the channel region of the trench gate power device in the prior art adopts a conventional thinking mode formed by injecting and pushing wells; therefore, the invention can prevent the influence of the thermal process in the structure formed by injecting the carrier storage layer or the channel region into the push-in well on the doping concentration distribution and the thickness of the carrier storage layer and the channel region, thereby realizing the accurate control on the impurity concentration distribution and the thickness of the carrier storage layer and the channel region and improving the performance of the device.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
fig. 1 is a schematic structural diagram of a trench gate power device according to a first embodiment of the present invention;
fig. 2 is a schematic structural diagram of a trench gate power device according to a second embodiment of the present invention;
fig. 3 is a schematic structural diagram of a trench gate power device according to a third embodiment of the present invention;
fig. 4A-4H are schematic structural diagrams of devices in steps of a method according to a first embodiment of the present invention.
Detailed Description
The trench gate power device of the first embodiment of the present invention:
fig. 1 is a schematic structural diagram of a trench gate power device according to a first embodiment of the present invention; the trench gate power device according to the first embodiment of the present invention includes a device cell region 101 and a termination region 102, where the device cell region 101 and the termination region 102 are respectively located at two sides of a dashed line AA in fig. 1. The termination region 102 surrounds the periphery of the device cell region 101, and a plurality of device cells are connected in parallel in the device cell region 101; the terminal structure of the terminal area 102 includes:
and a terminal trench 103, wherein a terminal dielectric layer 104 is filled in the terminal trench 103, the terminal trench 103 sequentially penetrates through the channel region 4, the carrier storage layer 3 and the drift region 2 of the device unit, and the depth of the terminal trench 103 is greater than that of a depletion region formed in the drift region 2 when the trench gate power device is reversely biased.
The region of the terminal trench 103 is also set as a chip scribing region of the trench gate power device, and the width of the terminal trench 103 meets the requirement value required by withstand voltage and is larger than the requirement value required by chip scribing by adopting photoetching.
The front structure of the device unit comprises:
the drift region 2 is composed of the first epitaxial layer 2, and the doping concentration of the first epitaxial layer 2 is set according to the requirements of the drift region 2.
The second epitaxial layer 3 is formed on the surface of the first epitaxial layer 2, the second epitaxial layer 3 has a first conductivity type doping, the doping concentration of the second epitaxial layer 3 is greater than that of the first epitaxial layer 2, and the second epitaxial layer 3 serves as a carrier storage layer 3 of the trench gate power device.
And a third epitaxial layer 4 formed on the surface of the second epitaxial layer 3, wherein the third epitaxial layer 4 has a second conductivity type doping, and the third epitaxial layer 4 is used as a channel region 4 of the trench gate power device.
The carrier storage layer 3 and the channel region 4 both adopt epitaxial layer process structures, and can prevent the influence of a thermal process in a structure formed by injecting and pushing wells into the carrier storage layer 3 or the channel region 4 on the doping concentration distribution and thickness of the carrier storage layer 3 and the channel region 4, so that the carrier storage layer 3 and the channel region 4 both have a structure in which the impurity concentration distribution and the thickness can be accurately controlled.
The trench gate comprises a gate trench 5, a gate dielectric layer 6 and a polysilicon gate 7, wherein the gate trench 5 penetrates through the channel region 4, the bottom of the gate trench 5 is positioned in the current carrier storage layer 3 or penetrates through the current carrier storage layer 3, the gate dielectric layer 6 is formed on the side surface and the bottom surface of the gate trench 5, the polysilicon gate 7 is filled in the gate trench 5 formed with the gate dielectric layer 6, and the surface of the channel region 4 covered by the side surface of the polysilicon gate 7 is used for forming a channel.
And the source region 8 consists of a first conduction type heavily doped region formed on the surface of the channel region 4.
The interlayer film 9, the contact hole 10, the source electrode and the gate electrode formed by patterning the front metal layer 12.
The contact hole 10 passes through the interlayer film 9.
The source region 8 is connected to the source electrode through the corresponding contact hole 10 at the top.
The polysilicon gate 7 is connected to the gate through the corresponding contact hole 10 at the top.
In a first embodiment of the present invention, the trench gate power device is a trench gate IGBT, and includes the following back structure:
a collector region 13a composed of a heavily doped region of the second conductivity type is formed on the back surface of the thinned semiconductor substrate 1.
A collector composed of a back metal layer is formed on the back surface of the collector region 13 a.
In the first embodiment of the present invention, the semiconductor substrate 1 is a silicon substrate, and the first epitaxial layer 2, the second epitaxial layer 3, and the third epitaxial layer 4 are all silicon epitaxial layers. In an actual process, an epitaxial wafer silicon substrate on which the first epitaxial layer 2, the second epitaxial layer 3, and the third epitaxial layer 4 are formed, or a general epitaxial material or a substrate made of a Float Zone (FZ) material can be directly used.
The gate dielectric layer 6 is a gate oxide layer and is formed by adopting a thermal oxidation process.
The doping concentration of the carrier storage layer 3 is 5e15cm-3～5e17cm-3The thickness is 0.5-5 microns.
The doping concentration of the channel region 4 is 5e16cm-3～5e17cm-3The thickness is 0.5-3 microns.
Preferably, the back structure of the trench gate power device further includes:
a field stop layer doped with a first conductivity type is formed between the drift region and the collector region 13 a. The bottom of the termination trench 103 penetrates into the field stop layer and penetrates through a depletion layer formed in the field stop layer. The depth of the termination trench 103 is typically several tens of microns, such as 40 to 60 microns, depending on the depletion region formed in the drift region.
The width of the termination trench 103 is within a few microns.
The field stop layer is formed by backside ion implantation plus backside annealing, such as laser annealing. Alternatively, the field stop layer is formed using an epitaxial layer formed on the surface of the semiconductor substrate 1.
The material of the terminal dielectric layer 104 includes silicon oxide, silicon oxynitride or silicon nitride, and the terminal dielectric layer 104 is a single-layer structure made of one material or the terminal dielectric layer 104 is a multi-layer structure made of more than two materials.
The bottom of the contact hole 10 corresponding to the top of the source region 8 also passes through the source region 8 and is connected with the channel region 4 at the bottom. In an IGBT device, the source region 8 is also referred to as an emitter region. Typically, the source regions 8 are formed by blanket ion implantation and are self-aligned to the surface of the channel region 4 formed between the polysilicon gates 7.
A well contact region 11 formed by a second conductive type heavily doped region is further formed on the surface of the channel region 4 at the bottom of the contact hole 10 corresponding to the top of the source region 8, and the well contact region 11 and the contact hole 10 corresponding to the top form ohmic contact.
In the first embodiment of the present invention, the trench gate power device is an N-type device, the first conductivity type is an N-type device, and the second conductivity type is a P-type device. In other embodiments can also be: the trench gate power device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.
The first embodiment of the present invention makes a special design for the terminal structure of the trench gate power device, the terminal structure is designed to be a structure composed of the terminal dielectric layer 104 filled in the terminal trench 103, and the terminal trench 103 is specially configured, the terminal trench 103 sequentially passes through the channel region 4, the carrier storage layer 3 and the drift region 2 of the device unit in the longitudinal depth, and the depth of the terminal trench 103 is greater than the depth of the depletion region formed in the drift region 2 when the trench gate power device is reversely biased, so that the device unit formed in the device unit region 101 can be well protected.
In addition, the first embodiment of the present invention makes a special setting for the width of the terminal trench 103, and the width of the terminal trench 103 satisfies the requirement value required for withstand voltage and simultaneously satisfies a value greater than the value to be evaluated for chip dicing by photolithography etching; because the terminal dielectric layer 104 is directly adopted as the terminal structure and the depth of the longitudinal structure of the terminal structure is larger than that of the depletion region, the width of the terminal structure of the first embodiment of the invention can be reduced under the condition of meeting the same withstand voltage; meanwhile, since the terminal trench 103 of the first embodiment of the present invention is also used as a dicing area, the minimum value of the reduction in the width of the terminal structure needs to satisfy the requirement of dicing by photolithography etching; in summary, the first embodiment of the present invention can greatly reduce the width of the termination structure, thereby reducing the area of the termination region 102. The first embodiment of the present invention can reduce the width of the terminal structure to several micrometers, compared to the width of the terminal structure in the conventional structure of several tens to several hundreds micrometers.
In addition, the terminal structure formed by filling the trench and the dielectric layer according to the first embodiment of the present invention does not introduce an additional thermal process, and can eliminate adverse effects of the thermal process of the terminal structure process on the impurity concentration distribution and thickness of the doped regions of the device unit region 101, such as the channel region 4 and the carrier storage layer 3, so that the device performance can be stable.
In addition, the first embodiment of the present invention can also provide the structure of the channel region 4 and the carrier storage layer 3 formed by the epitaxial layer in the device unit region 101, and the epitaxial process does not need to use an additional thermal process, so that the doping concentration, the doping concentration distribution, and the thickness of the channel region 4 and the carrier storage layer 3 can be accurately controlled; compared with the prior art, the method breaks through the limitation that the forming processes of the well region corresponding to the channel region 4 of the trench gate power device and the carrier storage layer 3 in the prior art both adopt a conventional thinking mode formed by injection and a push well; therefore, the first embodiment of the present invention can prevent the influence of the thermal process in the structure formed by injecting and pushing the carrier storage layer 3 or the channel region 4 into the channel region 4 on the doping concentration distribution and thickness of the carrier storage layer 3 and the channel region 4, thereby enabling the precise control of the impurity concentration distribution and thickness of the carrier storage layer 3 and the channel region 4 to be realized, and improving the performance of the device.
The trench gate power device of the second embodiment of the present invention:
as shown in fig. 2, which is a schematic structural diagram of a trench gate power device according to a second embodiment of the present invention, the difference between the trench gate power device according to the second embodiment of the present invention and the first trench gate power device according to the present invention is:
the source region 8 is defined by photolithography, and the source region 8 on the surface of the transition region between the device cell region 101 and the termination region 102 is removed, so that the source region 8 is not formed on the surface of the transition region.
The trench gate power device of the third embodiment of the present invention:
as shown in fig. 2, which is a schematic structural diagram of a trench gate power device according to a third embodiment of the present invention, the trench gate power device according to the third embodiment of the present invention is different from the first trench gate power device according to the present invention in that:
in a third embodiment of the present invention, the trench gate power device is a trench gate MOSFET, and includes the following back structure:
a drain region 13b composed of a heavily doped region of the first conductivity type is formed on the back surface of the thinned semiconductor substrate 1.
A drain electrode made of a back metal layer 14 is formed on the back surface of the drain region 13 b.
The method of the first embodiment of the invention:
as shown in fig. 4A to 4H, which are schematic structural diagrams of devices in steps of a method according to a first embodiment of the present invention, in a method for manufacturing a trench gate power device according to the first embodiment of the present invention, the trench gate power device includes a device cell region 101 and a termination region 102, the device cell region 101 is formed by connecting a plurality of device cells in parallel, and first, a step of forming a front structure of the device cell is performed until a source region 8 of the front structure of the device cell is formed, including the following steps:
step one, as shown in fig. 4A, a first epitaxial layer 2 with a first conductivity type doping is formed on the surface of a semiconductor substrate 1 by using an epitaxial growth process, a drift region is composed of the first epitaxial layer 2, and the doping concentration of the first epitaxial layer 2 is set according to the requirement of the drift region.
In the method according to the first embodiment of the present invention, the semiconductor substrate 1 is a silicon substrate, and the subsequent first epitaxial layer 2, second epitaxial layer 3, and third epitaxial layer 4 are all silicon epitaxial layers.
Step two, as shown in fig. 4A, a second epitaxial layer 3 is formed on the surface of the first epitaxial layer 2 by adopting an epitaxial growth process, the second epitaxial layer 3 has a first conductivity type dopant, the dopant concentration of the second epitaxial layer 3 is greater than that of the first epitaxial layer 2, and the second epitaxial layer 3 serves as a carrier storage layer 3 of the trench gate power device.
The doping concentration of the carrier storage layer 3 is 5e15cm-3～5e17cm-3The thickness is 0.5-5 microns.
Step three, as shown in fig. 4A, a third epitaxial layer 4 is formed on the surface of the second epitaxial layer 3 by using an epitaxial growth process, the third epitaxial layer 4 has a second conductivity type dopant, and the third epitaxial layer 4 is used as a channel region 4 of the trench gate power device.
The doping concentration of the channel region 4 is 5e16cm-3～5e17cm-3The thickness is 0.5-3 microns.
The carrier storage layer 3 and the channel region 4 both adopt epitaxial layer process structures, and can prevent the influence of a thermal process in a structure formed by injecting and pushing wells into the carrier storage layer 3 or the channel region 4 on the doping concentration distribution and thickness of the carrier storage layer 3 and the channel region 4, so that the carrier storage layer 3 and the channel region 4 both have a structure in which the impurity concentration distribution and the thickness can be accurately controlled.
Step four, forming a trench gate, comprising the following sub-steps:
step 41, as shown in fig. 4B, a gate trench 5 is formed by using a photolithography etching process, and the gate trench 5 passes through the channel region 4 and the carrier storage layer 3.
A Hard Mask (HM) is usually used to form the gate trench 5 by etching, the HM is silicon dioxide and has a thickness of
The width of the top opening of the gate trench 5 defined by photoetching is 0.3-1.5 micrometers, and the depth of the gate trench 5 is 1.5-7.0 micrometers.
And 42, as shown in fig. 4C, forming a gate dielectric layer 6 on the side surface and the bottom surface of the gate trench 5.
The gate dielectric layer 6 is a gate oxide layer formed by a thermal oxidation process, and the thickness of the gate dielectric layer 6 is
The temperature of the thermal oxidation process is 800-1050 ℃.
Step 43, as shown in fig. 4D, filling polysilicon into the gate trench 5 formed with the gate dielectric layer 6 to form a polysilicon gate 7, and forming a channel on the surface of the channel region 4 covered by the side surface of the polysilicon gate 7.
And fifthly, as shown in fig. 4E, forming a source region 8 on the surface of the channel region 4 between the trench gates in a self-alignment manner by adopting a first conductive type heavily doped ion implantation process.
The implanted impurity of the source region 8 is phosphorus or arsenic, and the doping concentration is 1e15cm-3～1e16cm-3. And annealing is carried out after the ion implantation of the source region 8 is finished, wherein the annealing is rapid thermal annealing or furnace tube annealing, and the annealing temperature is 700-950 ℃.
And then forming a termination structure comprising:
The region of the terminal trench 103 is also set as a chip scribing region of the trench gate power device, and the width of the terminal trench 103 meets the requirement value required by withstand voltage and is larger than the requirement value required by chip scribing by adopting photoetching.
In the method according to the first embodiment of the present invention, the width of the termination trench 103 is within several micrometers. The depth of the termination trench 103 is typically several tens of microns.
The material of the terminal dielectric layer 104 includes silicon oxide, silicon oxynitride or silicon nitride, and the terminal dielectric layer 104 is a single-layer structure made of one material or the terminal dielectric layer 104 is a multi-layer structure made of more than two materials.
Then, the following steps are continued:
and sixthly, as shown in fig. 4H, forming an interlayer film 9, a contact hole 10 and a front metal layer 12, and patterning the front metal layer 12 to form a source electrode and a gate electrode.
The interlayer film 9 is an oxide layer with a thickness of
The contact hole 10 passes through the interlayer film 9.
The source region 8 is connected to the source electrode through the corresponding contact hole 10 at the top.
The polysilicon gate 7 is connected to the gate through the corresponding contact hole 10 at the top.
In the method according to the first embodiment of the present invention, the bottom of the contact hole 10 corresponding to the top of the source region 8 further passes through the source region 8 and is connected to the channel region 4 at the bottom, and the thickness of the contact hole 10 over-etching silicon is 0.2 to 0.6 micrometers.
After the opening of the contact hole 10 is formed and before metal filling, forming a well contact region 11 formed by a second conductive type heavily doped region on the surface of the channel region 4 at the bottom of the contact hole 10 corresponding to the top of the source region 8, wherein the well contact region 11 and the contact hole 10 corresponding to the top form ohmic contact. What is needed isThe ion implantation impurity of the trap contact region 11 is B or BF2, and the doping concentration is 1e14cm-3～5e15cm-3. And annealing is carried out after the ion implantation of the source region 8 is finished, wherein the annealing is rapid thermal annealing or furnace tube annealing, and the annealing temperature is 700-950 ℃.
The trench gate power device is a trench gate IGBT and comprises the following steps of forming a back structure:
and seventhly, thinning the back of the semiconductor substrate 1.
Step eight, as shown in fig. 1, a collector region 13a composed of a second conductivity type heavily doped region is formed on the back surface of the thinned semiconductor substrate 1.
The collector region 13a is typically formed using a back side implant followed by activation using a laser anneal.
In the method according to the first embodiment of the present invention, before forming the collector region 13a in the eighth step, a field stop layer doped with a first conductivity type is formed by using a back ion implantation process, where the field stop layer is located between the drift region and the collector region 13 a. In other embodiments can also be: the field stop layer is formed on the surface of the semiconductor substrate 1 by an epitaxial process before being formed on the first epitaxial layer 2.
Step nine, forming a back metal layer 14 on the back of the collector region 13a and forming a collector by the back metal layer 14.
After the back structure is formed, a scribing process is further performed to divide each chip integrated on the same semiconductor substrate 1 into independent chips, and the scribing process includes the steps of:
a scribe area is lithographically opened, which is located in the region of the termination trench 103.
And sequentially removing the terminal dielectric layer 104 in the scribing region and removing the structures including the semiconductor substrate 1 at the bottom of the terminal dielectric layer 104 by adopting an etching process, so as to realize the cutting of each chip.
The method of the second embodiment of the invention:
the difference between the method according to the second embodiment of the present invention and the method according to the first embodiment of the present invention is that the method according to the second embodiment of the present invention comprises the following steps of forming the back structure:
and seventhly, thinning the back of the semiconductor substrate 1.
Step eight, as shown in fig. 3, a drain region 13b composed of a heavily doped region of the first conductivity type is formed on the back surface of the thinned semiconductor substrate 1.
Generally, the semiconductor substrate 1 can be directly provided with a heavy doping of the first conductivity type, so that the drain region 13b can be directly formed after thinning the semiconductor substrate 1. Can also be: the drain region 13b is formed by ion implantation after the semiconductor substrate 1 is thinned.
Step nine, forming a back metal layer 14 on the back of the drain region 13b and forming a drain electrode by the back metal layer 14.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (15)
1. A trench gate power device is characterized in that the trench gate power device comprises a device unit area and a terminal area, wherein the terminal area surrounds the periphery of the device unit area, and the device unit area is formed by connecting a plurality of device units in parallel; the terminal structure of the terminal area comprises:
the terminal trench is filled with a terminal dielectric layer, sequentially penetrates through a channel region, a carrier storage layer and a drift region of the device unit, and has a depth larger than that of a depletion region formed in the drift region when the trench gate power device is reversely biased;
the region of the terminal groove is also set as a chip scribing region of the groove gate power device, and the width of the terminal groove meets the requirement value required by withstand voltage and is larger than the requirement value required by chip scribing by adopting photoetching.
2. The trench-gate power device of claim 1 wherein:
the front structure of the device unit comprises:
the drift region is composed of the first epitaxial layer, and the doping concentration of the first epitaxial layer is set according to the requirement of the drift region;
the second epitaxial layer is formed on the surface of the first epitaxial layer and has first conductive type doping, the doping concentration of the second epitaxial layer is larger than that of the first epitaxial layer, and the second epitaxial layer is used as a carrier storage layer of the trench gate power device;
a third epitaxial layer formed on the surface of the second epitaxial layer, wherein the third epitaxial layer has a second conductivity type doping, and the third epitaxial layer is used as a channel region of the trench gate power device;
the carrier storage layer and the channel region both adopt epitaxial layer process structures, and the influence of a thermal process in a structure formed by injecting and pushing wells in the carrier storage layer or the channel region on the doping concentration distribution and thickness of the carrier storage layer and the channel region can be prevented, so that the carrier storage layer and the channel region both have a structure in which the impurity concentration distribution and the thickness can be accurately controlled;
the groove gate comprises a gate groove, a gate dielectric layer and a polysilicon gate, the gate groove penetrates through the channel region, the bottom of the gate groove is positioned in the current carrier storage layer or penetrates through the current carrier storage layer, the gate dielectric layer is formed on the side surface and the bottom surface of the gate groove, the polysilicon gate is filled in the gate groove formed with the gate dielectric layer, and the surface of the channel region covered by the side surface of the polysilicon gate is used for forming a channel;
the source region consists of a first conduction type heavily doped region formed on the surface of the channel region;
the interlayer film, the contact hole, the source electrode and the grid electrode are formed by patterning the front metal layer;
the contact hole penetrates through the interlayer film;
the source region is connected to the source electrode through the contact hole corresponding to the top;
the polysilicon gate is connected to the gate through the corresponding contact hole at the top.
3. The trench-gate power device of claim 2 wherein: the trench gate power device is a trench gate IGBT and comprises a back structure as follows:
a collector region consisting of a second conductive type heavily doped region is formed on the back surface of the thinned semiconductor substrate;
a collector composed of a back metal layer is formed on the back of the collector region;
or, the trench gate power device is a trench gate MOSFET, and includes the following back structure:
forming a drain region consisting of a first conductive type heavily doped region on the back surface of the thinned semiconductor substrate;
and a drain electrode consisting of a back metal layer is formed on the back surface of the drain region.
4. The trench-gate power device of claim 1 wherein: the semiconductor substrate is a silicon substrate, and the first epitaxial layer, the second epitaxial layer and the third epitaxial layer are silicon epitaxial layers;
the gate dielectric layer is a gate oxide layer and is formed by adopting a thermal oxidation process.
5. The trench-gate power device of claim 1 wherein: the doping concentration of the carrier storage layer is 5e15cm-3～5e17cm-3The thickness is 0.5 to 5 microns; the doping concentration of the channel region is 5e16cm-3～5e17cm-3The thickness is 0.5-3 microns.
6. The trench-gate power device of claim 3 wherein: when the trench gate power device is a trench gate IGBT, the back structure of the trench gate power device further includes:
a field stop layer doped with a first conductivity type and formed between the drift region and the collector region;
the bottom of the termination trench penetrates into the field stop layer and penetrates through a depletion layer formed in the field stop layer.
7. The trench-gate power device of claim 1 wherein: the width of the termination trench is within a few microns.
8. The trench-gate power device of claim 1 wherein: the terminal dielectric layer is made of silicon oxide, silicon oxynitride or silicon nitride, and is of a single-layer structure made of one material or a multi-layer structure made of more than two materials.
9. A manufacturing method of a trench gate power device is characterized in that the trench gate power device comprises a device unit area and a terminal area, wherein the device unit area is formed by connecting a plurality of device units in parallel, firstly, a step of forming a front structure of the device unit is carried out until a source area of the front structure of the device unit is formed, and before an interlayer film of the front structure of the device unit is formed, the following steps of forming the terminal structure are carried out, and the method comprises the following steps:
step 101, forming a terminal groove in the terminal area by adopting a photoetching process, wherein the terminal groove sequentially penetrates through the channel area, the current carrier storage layer and the drift area, and the depth of the terminal groove is greater than that of a depletion area formed in the drift area when the trench gate power device is reversely biased;
the region of the terminal groove is also set as a chip scribing region of the groove gate power device, and the width of the terminal groove meets the requirement value required by withstand voltage and is larger than the requirement value required by chip scribing by adopting photoetching;
and 102, filling a terminal dielectric layer in the terminal groove to form the terminal structure.
10. The method of manufacturing a trench-gate power device of claim 9, wherein: the step before the formation of the source region of the front side structure of the device cell comprises:
forming a first epitaxial layer doped with a first conduction type on the surface of a semiconductor substrate by adopting an epitaxial growth process, wherein a drift region consists of the first epitaxial layer, and the doping concentration of the first epitaxial layer is set according to the requirement of the drift region;
forming a second epitaxial layer on the surface of the first epitaxial layer by adopting an epitaxial growth process, wherein the second epitaxial layer has a first conductive type doping, the doping concentration of the second epitaxial layer is greater than that of the first epitaxial layer, and the second epitaxial layer is used as a current carrier storage layer of the trench gate power device;
forming a third epitaxial layer on the surface of the second epitaxial layer by adopting an epitaxial growth process, wherein the third epitaxial layer has second conductive type doping and is used as a channel region of the trench gate power device;
the carrier storage layer and the channel region both adopt epitaxial layer process structures, and the influence of a thermal process in a structure formed by injecting and pushing wells in the carrier storage layer or the channel region on the doping concentration distribution and thickness of the carrier storage layer and the channel region can be prevented, so that the carrier storage layer and the channel region both have a structure in which the impurity concentration distribution and the thickness can be accurately controlled;
step four, forming a trench gate, comprising the following sub-steps:
step 41, forming a gate trench by adopting a photoetching process, wherein the gate trench penetrates through the channel region and the carrier storage layer;
step 42, forming gate dielectric layers on the side surfaces and the bottom surfaces of the gate trenches;
step 43, filling polysilicon in the gate trench formed with the gate dielectric layer to form a polysilicon gate, wherein the surface of the channel region covered by the side surface of the polysilicon gate is used for forming a channel;
forming a source region on the surface of the channel region between the trench gates in a self-alignment manner by adopting a first conductive type heavily doped ion implantation process;
thereafter, step 101 and step 102 are performed thereafter;
then, the following steps are continued:
forming an interlayer film, a contact hole and a front metal layer, and patterning the front metal layer to form a source electrode and a grid electrode;
the contact hole penetrates through the interlayer film;
the source region is connected to the source electrode through the contact hole corresponding to the top;
the polysilicon gate is connected to the gate through the corresponding contact hole at the top.
11. The method of manufacturing a trench-gate power device of claim 10, wherein: the trench gate power device is a trench gate IGBT and comprises the following steps of forming a back structure:
seventhly, thinning the back of the semiconductor substrate;
step eight, forming a collector region consisting of a second conductive type heavily doped region on the back of the thinned semiconductor substrate;
step nine, forming a back metal layer on the back of the collector region and forming a collector by the back metal layer;
or, the trench gate power device is a trench gate MOSFET, and includes the following steps of forming a back structure:
seventhly, thinning the back of the semiconductor substrate;
step eight, forming a drain region consisting of a first conductive type heavily doped region on the back of the thinned semiconductor substrate;
and step nine, forming a back metal layer on the back of the drain region and forming a drain electrode by the back metal layer.
12. The method of manufacturing a trench-gate power device of claim 11, wherein: after the back structure is formed, a scribing process is further performed to divide each chip integrated on the same semiconductor substrate into independent chips, and the scribing process comprises the following steps:
photoetching and opening a scribing region, wherein the scribing region is positioned in the region of the terminal groove;
and sequentially removing the terminal dielectric layer in the scribing region and removing the structures including the semiconductor substrate at the bottom of the terminal dielectric layer by adopting an etching process, thereby realizing the cutting of each chip.
13. The method of manufacturing a trench-gate power device of claim 9, wherein: the width of the terminal groove is within a few micrometers;
the terminal dielectric layer is made of silicon oxide, silicon oxynitride or silicon nitride, and is of a single-layer structure made of one material or a multi-layer structure made of more than two materials.
14. The method of manufacturing a trench-gate power device of claim 11, wherein: when the trench gate power device is a trench gate IGBT, the back structure of the trench gate power device further includes:
forming a field stop layer doped with a first conductive type by adopting a back ion implantation process, wherein the field stop layer is positioned between the drift region and the collector region;
or the field stop layer is formed on the surface of the semiconductor substrate through an epitaxial process before being formed on the first epitaxial layer;
the bottom of the termination trench penetrates into the field stop layer and penetrates through a depletion layer formed in the field stop layer.
15. The method of manufacturing a trench-gate power device of claim 10, wherein: the bottom of the contact hole corresponding to the top of the source region also penetrates through the source region and is connected with the channel region at the bottom;
after the opening of the contact hole is formed and before metal filling, forming a well contact region formed by a second conduction type heavily doped region on the surface of the channel region at the bottom of the contact hole corresponding to the top of the source region, wherein the well contact region and the contact hole corresponding to the top form ohmic contact.
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| CN112201685B (en) * | 2020-09-08 | 2022-02-11 | 浙江大学 | Super junction device and dielectric combined terminal |
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