CN116864485A - 用于调整硅化镍的电阻率的工艺整合方法 - Google Patents
用于调整硅化镍的电阻率的工艺整合方法 Download PDFInfo
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- CN116864485A CN116864485A CN202310657384.3A CN202310657384A CN116864485A CN 116864485 A CN116864485 A CN 116864485A CN 202310657384 A CN202310657384 A CN 202310657384A CN 116864485 A CN116864485 A CN 116864485A
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- Prior art keywords
- layer
- nickel
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- electronic device
- substrate
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- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 title claims abstract description 55
- 229910021334 nickel silicide Inorganic materials 0.000 title claims abstract description 54
- 238000000034 method Methods 0.000 title abstract description 85
- 230000008569 process Effects 0.000 title abstract description 46
- 230000010354 integration Effects 0.000 title description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 139
- 239000000758 substrate Substances 0.000 claims abstract description 81
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 56
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 52
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 52
- 239000010703 silicon Substances 0.000 claims abstract description 52
- 238000004544 sputter deposition Methods 0.000 claims abstract description 24
- 239000000463 material Substances 0.000 claims description 24
- 230000004888 barrier function Effects 0.000 claims description 12
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 7
- 238000000151 deposition Methods 0.000 abstract description 24
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 14
- 229910052802 copper Inorganic materials 0.000 description 14
- 239000010949 copper Substances 0.000 description 14
- 239000007789 gas Substances 0.000 description 13
- 238000005240 physical vapour deposition Methods 0.000 description 13
- 229910017052 cobalt Inorganic materials 0.000 description 11
- 239000010941 cobalt Substances 0.000 description 11
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 11
- 239000000203 mixture Substances 0.000 description 11
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 10
- 230000008021 deposition Effects 0.000 description 9
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 6
- 239000013078 crystal Substances 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 229910052757 nitrogen Inorganic materials 0.000 description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 229910052786 argon Inorganic materials 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000011109 contamination Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000003993 interaction Effects 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000001307 helium Substances 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 229910052707 ruthenium Inorganic materials 0.000 description 2
- 239000004952 Polyamide Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000001803 electron scattering Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- -1 nitrogen Chemical compound 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Classifications
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
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- C01B33/00—Silicon; Compounds thereof
- C01B33/06—Metal silicides
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- C01G53/00—Compounds of nickel
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- C23C14/0036—Reactive sputtering
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- C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
- C23C14/0641—Nitrides
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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- Mechanical Engineering (AREA)
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- Manufacturing & Machinery (AREA)
- Plasma & Fusion (AREA)
- Analytical Chemistry (AREA)
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- Electrodes Of Semiconductors (AREA)
- Physical Vapour Deposition (AREA)
Abstract
本文描述在形成互连中使用的用于沉积低电阻率硅化镍层的方法和使用所述方法形成的电子装置。在一个实施方式中,一种用于沉积层的方法包括:将基板定位在处理腔室中的基板支撑件上,所述处理腔室具有设置在所述处理腔室中的镍靶材和硅靶材,所述镍靶材和硅靶材的面向基板部分各自具有从基板的面向靶材表面的在约10度与约50度之间的角度;使气体流动到处理腔室中;向镍靶材施加射频功率并且同时向硅靶材施加直流功率;分别从硅靶材和镍靶材同时地溅射硅和镍;并且在基板上沉积NixSi1‑x层,其中x在约0.01与约0.99之间。
Description
本申请是申请日为2018年6月12日、申请号为201880036646.1、发明名称为“用于调整硅化镍的电阻率的工艺整合方法”的发明专利申请的分案申请。
背景
技术领域
本文所述的实施方式总体涉及半导体装置制造的领域,并且更特别地涉及在多阴极物理气相沉积(physical vapor deposition;PVD)腔室中使用共溅射物理气相沉积(PVD)工艺形成金属硅化物互连的方法,和使用所述方法形成的电子装置。
背景技术
随着下一代装置的电路密度增加并且晶体管尺寸持续缩小,用于电线互连(wireinterconnect)的材料的性质开始主导针对主要性能度量标准(metric)的装置性能,所述主要性能度量标准包括功耗、电阻电容(resistance-capacitance;RC)延迟和可靠性。因为铜通常表现出相对较低的电阻率,并且从而表现出高的导电率,所以铜在过去的二十年里用于先进的USLI和VSLI技术中的电线互连。然而,随着装置的互连布线(wiring)的宽度缩小至互连布线材料的电子平均自由程(electron mean free path;eMFP)的尺寸或更小,材料的有效电阻率(effective resistivity)由于在互连布线的表面处的不希望的侧壁电子散射和材料的晶界界面而增加。因此,通常用于互连中的铜的有效电阻率对于具有低于铜的39nm的eMFP的宽度的铜互连开始增加,并且对于具有20nm或更小的宽度的互连显著增加。此外,与铜互连一起使用以防止铜材料至周围电介质材料的不希望扩散的阻挡层促成增加的电线互连的总体电阻率。
因此,在本技术中需要替代的导体材料。
发明内容
本文所述的实施方式通常涉及制造半导体装置的方法,并且特别地涉及在多阴极物理气相沉积(PVD)腔室中将硅化镍层共溅射至基板上的方法。
在一个实施方式中,用于沉积层的方法包括:将基板定位在处理腔室中的基板支撑件上,所述处理腔室具有设置在所述处理腔室中的镍靶材和硅靶材,所述镍靶材和硅靶材的面向基板部分各自具有从基板的面向靶材表面的在约10度与约50度之间的角度;使气体流动到处理腔室中;向镍靶材施加射频功率并且同时向硅靶材施加直流功率;分别从硅靶材和镍靶材同时地溅射硅和镍;并且在基板上沉积NixSi1-x层,其中x在约0.01与约0.99之间。
在另一实施方式中,一种形成装置的方法包括:将基板定位在处理腔室内的基板支撑件上,所述基板具有设置在所述基板上的复数个特征和设置在复数个特征之间的复数个开口;使气体流动到处理腔室中;向镍靶材施加射频功率并且同时向硅靶材施加直流功率,其中镍靶材和硅靶材设置在处理腔室中,并且面向基板的镍靶材和硅靶材的表面各自与面向靶材的基板的表面具有在约10度与约50度之间的角度;分别从硅靶材和镍靶材同时地溅射硅和镍;并且在基板上沉积NixSi1-x层以形成复数个互连,其中x在约0.01与约0.09之间。
在另一实施方式中,电子装置的特征在于图案化的基板,所述基板包含电介质层和设置在电介质层中的复数个互连特征,其中复数个互连特征包含具有约30μohm-cm或更低的有效电阻率的NixSi1-x,x在约0.4与约0.6之间,并且一个或多个互连特征具有小于约20nm的宽度和是所述宽度的约2倍或更大的高度。
在另一实施方式中,一种沉积包含镍和硅的层的方法包括:将基板定位在处理腔室中的基板支撑件上,所述处理腔室具有镍靶材和硅靶材,所述镍靶材和硅靶材具有与基板支撑件的表面在约10度与约50度之间的角度;使惰性气体流动到处理腔室中;向镍靶材施加射频功率并且向硅靶材施加直流功率,其中射频功率与直流功率的比率在约1:1与约1:12之间;并且共溅射NixSi1-x层至基板上,所述NixSi1-x层具有小于约200μohm-cm的电阻率,其中x在约0.01与0.99之间。
附图描述
为了可以详细理解本公开内容的上述特征的方式,可参照实施方式获得上文简要概述的本公开内容的更具体描述,所述实施方式的一些实施方式在附图中示出。然而,应注意,附图仅示出本公开内容的典型实施方式,并且因此不视为限制本公开内容的范围,因为本公开可允许其他同等有效的实施方式。
图1示出在到50nm和更小的电线互连按比例缩放(scale)与用于所述电线互连的材料选择之间的关系。
图2A是用于实践本文所公开的实施方式的多阴极处理腔室的横截面图。
图2B示出在图2A的处理腔室中的沉积期间靶材与基板的相对位置。
图2C是示出设置在用于实践本文公开的方法的处理腔室的腔室盖中的屏蔽组件的示意图。
图3A示出根据本文公开的实施方式沉积的硅化镍层的电阻率。
图3B将铜层、退火的钴层、退火的钌层和硅化镍层的电阻率相比较,其中根据本文所述的方法沉积所述硅化镍层。
图4是阐述根据本文公开的实施方式的将硅化镍层沉积至基板上的方法的流程图。
图5A至图5C图示使用图4阐述的方法的电线互连的形成。
为了促进理解,已经尽可能使用相同的参考数字指示附图共有的相同元件。预期一个实施方式的元件和特征可有益的并入其他实施方式中,而无需进一步叙述。
具体实施方式
本公开内容的实施方式通常描述用于使用在多阴极PVD腔室中的共溅射物理气相沉积(PVD)工艺将硅化镍层沉积至基板上(包括在基板上先前形成的层上方)的方法,并且所述方法特别地用于通过控制施加于镍靶材和硅靶材的功率和功率比来控制所沉积的硅化镍层的所得电阻率、组成和晶体取向的方法。
图1示出在到50nm和更小的厚度的沟槽按比例缩放与用于电线互连的材料选择之间的关系,其中按比例缩放涉及随着电线变窄到达并且超过材料的电子平均自由程eMFP,所选择的材料的线电阻率(电线电阻率)的变化。在图1中,互连电线在设置于电介质材料中的沟槽中,并且具有50nm和更小的宽度(沟槽CD)和2:1的深宽比(深度比宽度)。图1示出铜105、钴103和硅化镍101的有效电阻率之间的关系,其中衬垫/阻挡层插置在铜、钴或硅化镍与电介质材料之间以防止铜、钴或硅化镍原子扩散至周围电介质材料中。
如本文使用的,有效电阻率是指材料的所测量的电阻率,而不是材料的体积电阻率(bulk resistivity)。如从图1中可见,三种材料的有效电阻率随着电线互连的宽度按比例缩放至20nm和更小而开始有意义地增加,但是具有减小的沟槽CD的钴103(具有9.5的eMFP)的电阻率增加递增地小于铜105的电阻率的增加,使得钴103成为对于10nm和更小的沟槽CD的有前途的材料;事实上,对于在10nm至50nm宽度范围中的特征而言小于钴的有效电阻率的铜的有效电阻率在稍小于10nm宽的特征尺寸处变得大于钴的有效电阻率。硅化镍101(取决于镍与硅的组成而具有小于10nm的eMFP)的有效电阻率的递增增加小于钴103的有效电阻率的递增增加,使得硅化镍101成为对于具有7nm至8nm和更小的沟槽CD的电线互连的有前途的材料,并且钴的有效电阻率在大约6nm的线宽处变得大于硅化镍的有效电阻率。
图2A是根据本文所述的方法的用于将硅化镍沉积至基板228上的多阴极物理气相沉积(PVD)处理腔室200的横截面图。图2C是示出设置在处理腔室200的腔室盖240中的阴极屏蔽配置的示意图。图2C中所示的阴极屏蔽配置未在图2A中示出,然而,本文描述的方法包括使用阴极屏蔽配置,诸如图2C中所示的与处理腔室200一起的阴极屏蔽配置。在此实施方式中,处理腔室200被配置以处理单个基板,诸如设置在图2A中的基板支撑件226上的基板228。在其他实施方式中,本文描述的方法用于被配置以处理设置在基板转台上的多个基板。
在本文中,处理腔室200的特征在于限定处理容积299的一个或多个侧壁230、腔室盖240和腔室底部234。处理容积299流体耦接至真空209,诸如一个或多个专用真空泵,并且具有设置在处理容积299中的基板支撑件226。基板支撑件226包括由在处理腔室外部的基板支撑波纹管222围绕并且密封地延伸通过腔室底部234的轴224,所述轴224升高或降低基板支撑件226以促进将基板228传送到处理腔室200和从处理腔室200传送。基板228通过在一个或多个侧壁230的一个中的可密封开口232装载至处理容积299中,所述可密封开口常规地在沉积工艺期间用门或阀(未示出)密封。在一些实施方式中,轴224进一步耦接至致动器220,所述致动器220在处理期间旋转轴224,并且从而旋转设置在基板支撑件226上的基板228;在一些情况下,此举改善在基板228的表面上的沉积膜的厚度均匀性。
处理腔室200包括复数个阴极250A至250E,在本文中复数个阴极包含通过腔室盖240中的开口设置的五个阴极(在图2C中示出阴极250D至250E),其中复数个阴极250A至250E的每个阴极被配置以将一种或多种材料溅射至基板228上。在此实施方式中,第一阴极250A被配置以从镍靶材252溅射镍,而第二阴极250B被配置以从硅靶材262同时溅射(共溅射)硅,从而在基板228的表面上沉积均匀的硅化镍层。在本文中,第三阴极250C被配置以在存在含氮的反应性气体(诸如氮或氨)的情况下从钛靶材264溅射钛,从而在基板228的表面上沉积氮化钛层。在其他实施方式中,第三阴极250C被配置以从氮化钛靶材溅射氮化钛。
复数个阴极250A至250E的一个或多个包括磁性组件254和靶材背板253,磁性组件254设置在由阴极外壳255限定的外壳容积267内,靶材背板253具有靶材,诸如设置在靶材背板253上的镍靶材252。磁性组件254耦接至旋转轴256,旋转轴256耦接至电动机258,电动机258旋转旋转轴256,并且因此旋转在靶材背板253的后部非溅射侧上方的磁性组件254。复数个阴极250A至250E的每一个耦接至电源,诸如耦接至第一阴极250A并且耦接至第三阴极250C的射频(RF)电源263,或者耦接至第二阴极的250B的直流(DC)电源265。在其他实施方式中,直流电源265是脉冲直流电源。通过进气口211向处理腔室提供溅射气体和/或反应性气体。
复数个阴极250A至250E的每一个包括波纹管257和角度调节机构(未示出),所述角度调节机构耦接至腔室盖240的外部并且耦接至阴极外壳255。波纹管257用于通过防止大气进入处理容积299中并且防止处理气体从处理容积299泄漏至周围环境来维持处理容积299的真空条件。角度调节机构用于以参考图2B进一步详细描述的相对于基板228的表面的角度,改变并且随后固定阴极外壳255的位置,并且因此改变和固定设置于所述阴极外壳中的靶材的位置,所述靶材诸如第一阴极250A的镍靶材252。
图2B示出在沉积期间靶材260(诸如处理腔室200中的复数个阴极250A至250E的靶材的任一个)与基板228的相对位置。在本文中,基板228具有300mm的直径并且靶材260具有小于基板228的直径的直径,诸如小于约300mm,诸如在约100mm与约300mm之间。在处理期间,基板228通过升高图2A中所示的基板支撑件226移动至处理位置,至其中基板228的表面的水平平面与靶材260隔开竖直距离Z1的位置。从最接近于基板228的表面的水平平面的靶材的位置测量竖直距离Z1。在本文中,Z1在约100mm与约400mm之间,诸如在约150mm与约350mm之间,诸如在约200mm与约300mm之间,诸如在约225mm与约275mm之间。靶材260的表面的平面以角度θ相对于基板228的表面的水平平面成角度,其中θ在约10度与约50度之间,诸如在约20度与约40度之间、在约20度与约30度之间或在约30度与约40度之间。
图2C是示出设置在处理腔室200的腔室盖240中的屏蔽组件282的示意图。屏蔽组件282包括复数个竖直壁285,所述复数个竖直壁在复数个阴极250A至250E的每一个之间延伸,其中复数个竖直壁285在中心线处耦接并且从中心线向外径向延伸。通过在复数个竖直壁285之间提供物理阻挡物,定位复数个竖直壁285以防止处理期间在复数个阴极250A至250E的两个或更多个之间的相互影响和/或相互靶材污染。相互影响是指在共溅射工艺中,来自一个阴极的电源(诸如射频电源263)与另一阴极电源(诸如直流电源265)的不希望的电干扰。相互靶材污染是指在共溅射和/或顺序溅射工艺中来自一个靶材的材料至另一靶材上的不希望的沉积。
在一些实施方式中,处理腔室200进一步包括耦接至如图2C中所示的复数个阴极250A至250E的一个或多个阴极的一个或多个圆柱形屏蔽物280。在那些实施方式中,一个或多个圆柱形屏蔽物280围绕阴极外壳255并且从而围绕复数个阴极250A至250C的一个或多个阴极的设置在阴极外壳255中的靶材。圆柱形屏蔽物280被配置以通过在腔室中的阴极之间提供物理阻挡物来防止相互影响和相互靶材污染。在其他实施方式中,处理腔室200包括圆柱形屏蔽物280而不包括屏蔽组件282。
图3A示出根据本文公开的实施方式沉积的硅化镍层的电阻率。线316、317、318、319各自表示在共溅射PVD工艺期间供应至镍阴极的功率与供应至硅阴极的功率的比率,其中与供应至硅阴极(诸如第二阴极250B)的功率相比,供应至镍阴极(诸如第一阴极250A)的功率从由线316表示的第一功率比增加至由线319表示的第四功率比,从而增加在沉积的层中的镍与硅的比率,使得以第一功率比316沉积的硅化镍层是富硅层,而以第四功率比319沉积的硅化镍层是富镍层。使用线316至319的功率比沉积所得到的硅化镍层R1至R8的电阻率在表1中展示。R1和R5各自使用第一功率比316沉积,R2和R6各自使用第二功率比317沉积,R3和R7各自使用第三功率比318沉积,R4和R8各自使用第四功率比319沉积。
如图3A中所示,R1至R4全部在相同的直流功率下沉积,同时至镍靶材的射频功率变化;R5至R8全部在相同的射频功率下沉积,同时至硅靶材的直流功率变化。通过测量所沉积膜的薄层电阻、测量所沉积膜的厚度,并且从薄层电阻和膜厚度测量推定膜的有效电阻率来计算比率R1至R8的材料层的有效电阻率。意外地,所沉积的层的电阻率不随着镍浓度增加而线性改变,例如,尽管与在比率R1处的硅化镍组成相比,在比率R2处的硅化镍组成显示有效电阻率的显著减小(由于在比率R2处的硅化镍组成具有较高浓度的更导电的镍,这会是预期的),在比率R3和R4处的硅化镍组成比在比率R2处的硅化镍组成具有更高浓度的镍,但也具有从在比率R2处的硅化镍组成增加的有效电阻率。同时意外的是使用相同功率比(诸如第一功率比316)、但在不同的射频和直流功率水平处沉积的硅化镍层中的电阻率的差异,其中在比率R1和R4下的硅化镍组成中的镍和硅的浓度大体上相同。
虽然不限于任何特定理论,但应相信,除了镍和硅浓度之外,根据本文所述的方法沉积的硅化镍层的晶体取向可通过调整施加至镍和硅阴极的功率水平并且从而调整对应的功率比来控制,以用期望的晶体取向和/或期望的有效电阻率沉积硅化镍层。此外,本文描述的方法可用于沉积具有期望的晶体取向的硅化镍层而无需在沉积之后的退火工艺,或至少无需高温退火工艺。这在由于低K电介质材料的低热预算而不希望高温的互连领域(interconnect level)是有益的。
表1
图3B比较不同材料的层的有效电阻率,所述不同材料诸如铜321、退火的钴323、退火的钌324和硅化镍325,其中根据本文所述的方法来沉积硅化镍325。针对25nm和更小的层厚度来测量有效电阻率。如图3b中所示,与在小于约10nm的覆盖膜厚度下的其他互连材料相比,根据本文所述的方法沉积的硅化镍325层持续具有相当低的有效电阻率,使得硅化镍成为用于不足10nm的互连宽度的合适材料。
图4是阐述将硅化镍层沉积至基板上、或沉积至设置在基板上的特征上的方法的流程图。图5A至图5C图示使用在图4中阐述的方法400的电线互连的形成。在活动405处,方法400包括将基板(诸如图案化的基板)定位在多阴极处理腔室中的基板支撑件上。在图5A中图示图案化的基板,其中图案包含具有高度H的复数个特征535和设置在复数个特征535之间的具有宽度W的复数个开口537。在本文中,复数个特征535是由电介质材料形成,诸如氧化硅、SIN、SiOC、SiC或低k聚合物(诸如聚酰胺)或上述材料的组合。开口的宽度小于约20nm,诸如小于约15nm、小于约10nm、小于约8nm、小于约7nm,诸如小于约5nm。复数个特征的高度H等于或大于复数个开口537的宽度W的约两倍。处理腔室维持在小于约1毫托,诸如在约0.5毫托与1毫托之间的压力下。在一些实施方式中,图案化的基板进一步包括阻挡层(未示出),诸如Ta、TaN、Ti、W、WN或上述材料的组合。在那些实施方式中,阻挡层设置在复数个特征535上方,并且用作设置在复数个特征535之间的复数个开口537中的衬垫。在一些实施方式中,阻挡层在与随后沉积的硅化镍层相同的处理腔室中沉积,并且因此在沉积阻挡层与沉积硅化镍层之间不存在基板破坏真空。
在活动410处,方法400包括使溅射气体流动到处理腔室中,其中溅射气体是诸如氩、氦或氮的惰性气体。
在活动415处,方法400包括向镍靶材施加射频功率并且相邻于所述镍靶材的表面形成第一溅射等离子体。镍靶材的表面以相对于基板支撑件的表面的在约10度与约50度之间的角度设置在处理腔室中,并且这相对于设置在基板支撑件上的基板的表面在约10度与约50度之间的角度。射频功率在约100瓦与约1000瓦之间。在本文中,射频功率耦接至背板,背板具有设置在背板上的镍靶材。在另一实施方式中,射频功率耦接至镍靶材。
在活动420处,方法400包括向硅靶材施加直流功率并且相邻于所述硅靶材的表面形成第二溅射等离子体。硅靶材以相对于基板支撑件的表面和设置在基板支撑件上的基板的表面的在约10度与约50度之间的角度设置在处理腔室中。直流功率在约600瓦与约1200瓦之间,并且与施加射频功率至镍靶材同时地施加直流功率至硅靶材。在本文中,直流功率耦接至背板,背板具有设置在背板上的硅靶材。在另一实施方式中,直流功率耦接至硅靶材。硅靶材包含非晶硅、多晶硅、结晶硅或上述材料的组合。在本文中,射频功率和直流功率的比率在约1:1与约1:12之间。
在活动425处,方法400包括通过从镍和硅靶材共溅射材料至基板和/或设置在所述基板上的特征上来沉积均匀的硅化镍层539(NixSi1-x,其中x在0.01与0.99之间,诸如在0.1与0.9之间)。图5B图示将硅化镍层539沉积至设置在基板228上的复数个特征535上。图5C图示根据上文描述的方法形成的复数个互连541,其中使用合适的工艺从复数个特征535的表面去除硅化镍层539的部分,所述工艺诸如蚀刻或化学机械抛光工艺,以形成电子装置。
本文的方法400通过调节射频功率、直流功率和射频功率与直流功率之间的比率,通过调节镍和硅靶材角度,并且通过调节处理腔室的压力而对调整硅化镍层的电阻率和组成有用。例如,在一个实施方式中,方法400用于沉积低电阻率NixSi1-x层,其中x在约0.4与约0.6之间,例如其中x是约0.5。低电阻率NixSi1-x层在小于约20nm的厚度和全晶体取向(full crystalline orientation)下具有小于约30μohm-cm的电阻率,诸如在约10μohm-cm与约30μohm-cm之间的电阻率。在具有在约0.6毫托与约0.7毫托之间的压力的处理腔室中通过共溅射镍和硅来沉积低电阻率NixSi1-x层。镍和硅靶材的面各自相对于基板支撑件的表面并且因此从设置在基板支撑件上的基板的表面具有在约20度与约40度之间的角度。在此实施方式中,射频功率和直流功率的比率在约1:1.6与约1:4之间,其中射频功率在约300瓦与约500瓦之间,直流功率在约800瓦与约1200瓦之间。
在另一实施方式中,方法400用于沉积中等电阻率NixSi1-x层,其中x大于约0.6。中等电阻率层在小于约20nm的厚度下具有在约30μohm-cm与约60μohm-cm之间的电阻率,诸如在约30μohm-cm与约50μohm-cm之间的电阻率。在具有在约0.5毫托与约0.8毫托之间的压力的处理腔室中通过共溅射镍和硅来沉积中等电阻率NixSi1-x层,其中镍和硅靶材各自从基板支撑件的表面并且从设置在基板支撑件上的基板的表面具有在约20度与约30度之间的角度。在此实施方式中,射频功率与直流功率的比率大于约1:2.4,诸如大于约1:1.6,其中大于涉及与直流功率相比增加的射频功率。射频功率大于约500瓦,例如在约500瓦与约1000瓦之间,并且直流功率在约800瓦与约1200瓦之间。
在另一实施方式中,方法400用于沉积高电阻率NixSi1-x层,其中x小于约0.4,诸如小于约0.33。高电阻率NixSi1-x层在小于约20nm的厚度下具有大于约60μohm-cm的电阻率,诸如在约60μohm-cm与200μohm-cm之间的电阻率。在具有在约0.5毫托与约1毫托之间的压力的处理腔室中通过共溅射镍和硅来沉积高电阻率NixSi1-x层。镍和硅靶材各自从基板支撑件的表面并且从设置在基板支撑件上的基板的表面具有在约30度与约40度之间的角度。在此实施方式中,射频功率与直流功率之间的比率在约1:12与约1:2之间。射频功率在约100瓦与约300瓦之间,直流功率在约600瓦与约1200瓦之间。
在另一实施方式中,方法400进一步包含在硅化镍层上沉积TiN钝化层,其中在与硅化镍层相同的处理腔室中沉积TiN钝化层,并且因此不存在基板破坏真空。通过使包含氩的溅射气体和与钛反应的气体(诸如氮、NH4或上述项的组合)流动到处理腔室中,向钛靶材施加射频功率,形成溅射气体的溅射等离子体,并且将TiN钝化层沉积至硅化镍层上来沉积TiN层。在另一实施方式中,靶材包含TiN并且溅射气体包含氩、氦、氮或上述项的组合。
在一些实施方式中,氮化硅层在约400℃以下的温度下退火。
上文所述的方法允许通过调节多阴极处理腔室的处理参数来沉积具有可调整的组成(镍和硅浓度)、晶体取向和电阻率的硅化镍层。在具有可调整的电阻率的情况下,根据本文公开的实施方式沉积的硅化镍层可用于需要中等电阻率或高电阻率的应用,诸如需要嵌入式电阻(诸如板电阻或线电阻)的装置。此外,根据本文所述的实施方式形成的低电阻率硅化镍层适用于用作如硅化镍的eMPF的不足20nm状况中的互连并且因此适用于互连的有效电阻率,允许将线宽度和其他导体特征宽度按比例缩放至小于当前可从其他已知材料获得的尺寸。
虽然前述内容针对本公开内容的实施方式,但是可在不背离本公开内容的基本范围的情况下设计本公开内容的其他和进一步的实施方式,并且本公开内容的范围由所附权利要求书确定。
Claims (20)
1.一种电子装置,包含:
图案化基板,所述图案化基板包含电介质层和设置在所述电介质层中的复数个互连特征,其中
所述复数个互连特征包含NixSi1-x层,
x在约0.4与约0.6之间,
所述NixSi1-x层具有30μohm-cm或更小的有效电阻率,并且
所述互连特征的一个或多个具有小于约20nm的宽度和是所述宽度的约2倍或更大的高度。
2.如权利要求1所述的电子装置,进一步包含阻挡层,所述阻挡层设置在所述电介质层与所述互连特征之间。
3.如权利要求1所述的电子装置,进一步包含氮化钛层,所述氮化钛层设置在所述NixSi1-x层上。
4.如权利要求1所述的电子装置,其中通过同时地从镍靶材溅射镍和从硅靶材溅射硅以形成均匀的硅化镍层来形成所述复数个互连特征。
5.如权利要求4所述的电子装置,进一步包含阻挡层,所述阻挡层设置在所述电介质层与所述互连特征之间。
6.如权利要求4所述的电子装置,进一步包含氮化钛层,所述氮化钛层设置在所述NixSi1-x层上。
7.如权利要求4所述的电子装置,其中如所沉积的所述均匀的硅化镍层具有全晶体取向。
8.一种电子装置,包含:
图案化基板,所述图案化基板包含设置在电介质层中的复数个特征,其中
所述复数个特征包含NixSi1-x层,其中x大于约0.6,
所述NixSi1-x层具有小于20nm的厚度,并且
所述NixSi1-x层的有效电阻率在约30μohm-cm与约60μohm-cm之间。
9.如权利要求8所述的电子装置,进一步包含阻挡层,所述阻挡层设置在所述电介质层与所述特征之间。
10.如权利要求8所述的电子装置,进一步包含氮化钛层,所述氮化钛层设置在所述NixSi1-x层上。
11.如权利要求8所述的电子装置,其中所述特征的一个或多个形成嵌入式电阻。
12.如权利要求8所述的电子装置,其中通过同时地从镍靶材溅射镍和从硅靶材溅射硅以形成均匀的硅化镍层来形成所述复数个特征。
13.如权利要求12所述的电子装置,其中所述特征形成嵌入式电阻。
14.一种电子装置,包含:
图案化基板,所述图案化基板包含设置在电介质层中的复数个特征,其中
所述复数个特征包含NixSi1-x层,其中x小于约0.4,
所述NixSi1-x层具有小于20nm的厚度,并且
所述NixSi1-x层的有效电阻率大于约60μohm-cm。
15.如权利要求14所述的电子装置,进一步包含阻挡层,所述阻挡层设置在所述电介质层与所述特征之间。
16.如权利要求14所述的电子装置,进一步包含氮化钛层,所述氮化钛层设置在所述NixSi1-x层上。
17.如权利要求14所述的电子装置,其中所述特征的一个或多个形成嵌入式电阻。
18.如权利要求14所述的电子装置,其中通过同时地从镍靶材溅射镍和从硅靶材溅射硅以形成均匀的硅化镍层来形成所述复数个特征。
19.如权利要求18所述的电子装置,其中所述特征的一个或多个形成嵌入式电阻。
20.如权利要求19所述的电子装置,其中所述有效电阻率小于约200μohm-cm。
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US10748783B2 (en) | 2018-07-25 | 2020-08-18 | Applied Materials, Inc. | Gas delivery module |
US10692734B2 (en) | 2018-10-25 | 2020-06-23 | Applied Materials, Inc. | Methods of patterning nickel silicide layers on a semiconductor device |
WO2020117462A1 (en) | 2018-12-07 | 2020-06-11 | Applied Materials, Inc. | Semiconductor processing system |
US11205589B2 (en) | 2019-10-06 | 2021-12-21 | Applied Materials, Inc. | Methods and apparatuses for forming interconnection structures |
US11901222B2 (en) | 2020-02-17 | 2024-02-13 | Applied Materials, Inc. | Multi-step process for flowable gap-fill film |
TW202348822A (zh) * | 2022-02-14 | 2023-12-16 | 美商應用材料股份有限公司 | 用於製造pvd鈣鈦礦膜的設備及方法 |
Family Cites Families (42)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4424101A (en) | 1980-11-06 | 1984-01-03 | The Perkin-Elmer Corp. | Method of depositing doped refractory metal silicides using DC magnetron/RF diode mode co-sputtering techniques |
US4954852A (en) * | 1987-12-24 | 1990-09-04 | Ford Microelectronics, Inc. | Sputtered metallic silicide gate for GaAs integrated circuits |
JPH0521347A (ja) | 1991-07-11 | 1993-01-29 | Canon Inc | スパツタリング装置 |
US6423196B1 (en) * | 1997-11-19 | 2002-07-23 | Tosoh Smd, Inc. | Method of making Ni-Si magnetron sputtering targets and targets made thereby |
JP3296281B2 (ja) | 1998-01-22 | 2002-06-24 | 日本電気株式会社 | スパッタリング装置及びスパッタリング方法 |
US6905578B1 (en) | 1998-04-27 | 2005-06-14 | Cvc Products, Inc. | Apparatus and method for multi-target physical-vapor deposition of a multi-layer material structure |
US6599644B1 (en) * | 2000-10-06 | 2003-07-29 | Foundation For Research & Technology-Hellas | Method of making an ohmic contact to p-type silicon carbide, comprising titanium carbide and nickel silicide |
US20020132473A1 (en) * | 2001-03-13 | 2002-09-19 | Applied Materials ,Inc. | Integrated barrier layer structure for copper contact level metallization |
US6806172B1 (en) * | 2001-04-05 | 2004-10-19 | Advanced Micro Devices, Inc. | Physical vapor deposition of nickel |
US6709553B2 (en) * | 2002-05-09 | 2004-03-23 | Applied Materials, Inc. | Multiple-step sputter deposition |
JP2004131839A (ja) * | 2002-06-17 | 2004-04-30 | Applied Materials Inc | パルス化された電力によるスパッタリング堆積 |
KR100480634B1 (ko) | 2002-11-19 | 2005-03-31 | 삼성전자주식회사 | 니켈 살리사이드 공정을 이용한 반도체 소자의 제조방법 |
WO2004099458A2 (en) * | 2003-05-02 | 2004-11-18 | Tosoh Smd, Inc. | METHODS FOR MAKING LOW SILICON CONTENT Ni-Si SPUTTERING TARGETS AND TARGETS MADE THEREBY |
US7268065B2 (en) | 2004-06-18 | 2007-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of manufacturing metal-silicide features |
TWI267183B (en) * | 2004-09-29 | 2006-11-21 | Sanyo Electric Co | Semiconductor device and manufacturing method of the same |
CN1778731B (zh) * | 2004-11-26 | 2011-02-02 | 鸿富锦精密工业(深圳)有限公司 | 模造玻璃模仁及其制造方法 |
US7485556B2 (en) * | 2005-03-18 | 2009-02-03 | Applied Materials, Inc. | Forming metal silicide on silicon-containing features of a substrate |
JP2007067225A (ja) * | 2005-08-31 | 2007-03-15 | Toshiba Corp | 半導体装置およびその製造方法 |
US8460519B2 (en) * | 2005-10-28 | 2013-06-11 | Applied Materials Inc. | Protective offset sputtering |
JP4983087B2 (ja) * | 2006-04-27 | 2012-07-25 | 富士通セミコンダクター株式会社 | 成膜方法、半導体装置の製造方法、コンピュータ可読記録媒体、スパッタ処理装置 |
JP4819566B2 (ja) * | 2006-04-28 | 2011-11-24 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US20080280439A1 (en) * | 2007-05-08 | 2008-11-13 | Atmel Corporation | Optimal concentration of platinum in a nickel film to form and stabilize nickel monosilicide in a microelectronic device |
US20080311711A1 (en) * | 2007-06-13 | 2008-12-18 | Roland Hampp | Gapfill for metal contacts |
JP5584409B2 (ja) * | 2008-02-21 | 2014-09-03 | キヤノンアネルバ株式会社 | スパッタリング装置およびその制御方法 |
CN101555016B (zh) * | 2008-04-09 | 2011-06-08 | 清华大学 | 硅化镍纳米线的制备方法 |
JP5446148B2 (ja) * | 2008-07-02 | 2014-03-19 | 富士電機株式会社 | 炭化珪素半導体装置の製造方法 |
JP2011066060A (ja) * | 2009-09-15 | 2011-03-31 | Tokyo Electron Ltd | 金属シリサイド膜の形成方法 |
US8563428B2 (en) * | 2010-09-17 | 2013-10-22 | Applied Materials, Inc. | Methods for depositing metal in high aspect ratio features |
US8491759B2 (en) | 2010-10-20 | 2013-07-23 | COMET Technologies USA, Inc. | RF impedance matching network with secondary frequency and sub-harmonic variant |
CN103635603B (zh) * | 2011-09-09 | 2016-04-13 | 佳能安内华股份有限公司 | 成膜装置 |
US9499901B2 (en) * | 2012-01-27 | 2016-11-22 | Applied Materials, Inc. | High density TiN RF/DC PVD deposition with stress tuning |
JP6325229B2 (ja) * | 2012-10-17 | 2018-05-16 | 株式会社半導体エネルギー研究所 | 酸化物膜の作製方法 |
US9190527B2 (en) * | 2013-02-13 | 2015-11-17 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method of semiconductor device |
CN103741104B (zh) * | 2013-12-24 | 2016-01-20 | 南京航空航天大学 | 通过磁控溅射在锆表面镀锆铜镍三元非晶合金薄膜的方法 |
US11183375B2 (en) | 2014-03-31 | 2021-11-23 | Applied Materials, Inc. | Deposition system with multi-cathode and method of manufacture thereof |
US9416049B2 (en) | 2014-06-23 | 2016-08-16 | Intermolecular, Inc. | Low-e panels and methods for forming the same |
US20160268127A1 (en) * | 2015-03-13 | 2016-09-15 | Semiconductor Energy Laboratory Co., Ltd. | Oxide and Manufacturing Method Thereof |
US9812328B2 (en) * | 2015-06-22 | 2017-11-07 | Applied Materials, Inc. | Methods for forming low resistivity interconnects |
US10468238B2 (en) | 2015-08-21 | 2019-11-05 | Applied Materials, Inc. | Methods and apparatus for co-sputtering multiple targets |
US9666606B2 (en) * | 2015-08-21 | 2017-05-30 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and electronic device |
WO2017149413A1 (en) * | 2016-03-04 | 2017-09-08 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
KR102513161B1 (ko) * | 2016-03-11 | 2023-03-22 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 복합체 및 트랜지스터 |
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