CN116453582B - Signal testing system and method for memory - Google Patents
Signal testing system and method for memory Download PDFInfo
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- CN116453582B CN116453582B CN202310699849.1A CN202310699849A CN116453582B CN 116453582 B CN116453582 B CN 116453582B CN 202310699849 A CN202310699849 A CN 202310699849A CN 116453582 B CN116453582 B CN 116453582B
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- 230000015654 memory Effects 0.000 title claims abstract description 87
- 238000000034 method Methods 0.000 title claims description 13
- 238000004891 communication Methods 0.000 claims abstract description 20
- 238000001514 detection method Methods 0.000 claims description 25
- 230000002159 abnormal effect Effects 0.000 claims description 10
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- 239000000523 sample Substances 0.000 description 23
- 238000012986 modification Methods 0.000 description 7
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- 238000004590 computer program Methods 0.000 description 4
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention provides a signal testing system and a signal testing method of a memory, comprising the following steps: the main control end is used for sending out a debugging instruction, a testing instruction and a termination instruction; the oscilloscope is connected with the main control end in a communication way and used for building a corresponding test environment according to the debugging instruction; the test board is connected with the main control end and the oscilloscope in a communication way, the embedded memory is connected with the test board in a communication way, and the test board tests the embedded memory according to the test instruction and generates test data in the oscilloscope; and after the main control end sends out the termination instruction, the test board stops testing, and the oscilloscope sends the test data to the main control end. According to the signal testing system and the signal testing method for the memory, disclosed by the invention, the testing efficiency of the signal testing of the memory can be improved.
Description
Technical Field
The present invention relates to the field of memories, and in particular, to a signal testing system and a signal testing method for a memory.
Background
The embedded memory (Embedded Multi Media Card, eMMC) is a memory capable of storing code and data management. The embedded memory needs to be subjected to signal testing in the research and development stage to ensure that the signal integrity of the embedded memory meets the specification standard. When the signal test is performed on the embedded memory, the test efficiency is low. Therefore, there is a need for improvement.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a signal testing system and a testing method for a memory, which can improve the testing efficiency of the signal testing of the memory.
To achieve the above and other related objects, the present invention provides a signal testing system for a memory, comprising:
the main control end is used for sending out a debugging instruction, a testing instruction and a termination instruction;
the oscilloscope is connected with the main control end in a communication way and used for building a corresponding test environment according to the debugging instruction; and
the test board is in communication connection with the main control end and the oscilloscope, the embedded memory is in communication connection with the test board, and the test board tests the embedded memory according to the test instruction and generates test data in the oscilloscope;
and after the main control end sends out the termination instruction, the test board stops testing, and the oscilloscope sends the test data to the main control end.
In an embodiment of the present invention, the test device further includes a probe, the probe is communicatively connected to the test board and the oscilloscope, and the oscilloscope selects a test channel between the probe and the test board based on a preset test item.
In an embodiment of the present invention, the debug instruction includes a setting instruction and a detection instruction, the oscilloscope is configured to respond to the setting instruction to set a corresponding test environment, and the oscilloscope is configured to respond to the detection instruction to enter a normal state.
In an embodiment of the present invention, the test board is further configured to respond to the test instruction, test the embedded memory based on the test instruction, and transmit the generated intermediate data to the oscilloscope through a corresponding test channel, where the oscilloscope selects the corresponding intermediate data based on a preset test item, and the oscilloscope generates the test data based on the selected intermediate data.
In an embodiment of the present invention, the master control end is further configured to assign different variables based on different test data, aggregate all the variables, represent the variables as test results, and derive the test results.
The invention also provides a signal testing method of the memory, which comprises the following steps:
responding to a debugging instruction of the main control end to set a corresponding test environment on the oscilloscope;
responding to the test instruction of the main control end, and testing the embedded memory by the test board based on the test instruction and generating test data;
and responding to a termination instruction of the main control end, stopping testing by the test board, and sending the test data to the main control end by the oscilloscope.
In an embodiment of the present invention, the step of responding to a debug instruction of a main control end to set a corresponding test environment on an oscilloscope includes:
responding to a setting instruction of the main control end to set a corresponding test environment on the oscilloscope;
responding to the detection instruction of the main control end so as to enable the oscilloscope to enter a normal state.
In an embodiment of the present invention, the step of responding to the detection instruction of the master control end to make the oscilloscope enter a normal state includes:
responding to the detection instruction of the main control end, and judging whether the oscilloscope is in a normal state or not;
if the oscilloscope is in a normal state, the test environment is successfully built;
if the oscilloscope is in an abnormal state, the test environment is built up and fails, and the main control end repeatedly sends the setting instruction to the oscilloscope until the oscilloscope is in a normal state, and at the moment, the test environment is built up successfully.
In an embodiment of the present invention, the step of the test board testing the embedded memory based on the test instruction and generating test data in response to the test instruction of the master control end includes:
responding to the test instruction of the main control end, testing the embedded memory by the test board based on the test instruction, and transmitting the generated intermediate data to the oscilloscope through a corresponding test channel;
the oscilloscope selects corresponding intermediate data based on a preset test item;
the oscilloscope generates test data based on the selected intermediate data.
In an embodiment of the present invention, after the step of responding to the termination instruction of the master control end, the test board stops testing, and the oscilloscope sends the test data to the master control end, the method further includes:
the main control terminal gives different variables based on different test data;
and the main control terminal gathers all the variables, represents the variables as test results and exports the variables.
As described above, the signal testing system and the signal testing method for the memory provided by the invention can automatically complete the signal testing of the embedded memory, thereby effectively improving the signal testing efficiency. Meanwhile, the test result is automatically exported, so that errors can be avoided when the test result is manually recorded, and the accuracy of the test result is ensured.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a signal testing system for a memory according to the present invention;
FIG. 2 is a flow chart showing a method for testing signals of a memory according to the present invention;
FIG. 3 is a flowchart showing step S10 in FIG. 2;
FIG. 4 is a flowchart showing step S12 in FIG. 3;
FIG. 5 is a flowchart showing step S20 in FIG. 2;
fig. 6 is a flowchart of step S40 in fig. 2.
Description of element numbers:
10. a main control end; 11. VBA program; 20. an oscilloscope; 30. a detector; 40. a test board; 50. an embedded memory; 61. a net wire; 62. an interface; 63. an asynchronous transceiving transmitter; 64. a serial port tool; 65. a probe; 66. and a communication interface.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, the present invention provides a signal testing system for a memory, which can be applied to a signal integrity testing process of an embedded memory 50. The test system may include a master 10, an oscilloscope 20, a prober 30, and a test board 40. The main control terminal 10 may be respectively connected with the oscilloscope 20 and the test board 40 in a communication manner. Oscilloscope 20 may be communicatively coupled to probe 30. The probes 30 may be communicatively coupled to a test board 40. The embedded memory 50 may be communicatively coupled to the test board 40. The signal integrity test of the embedded memory 50 can be completed through the cooperation of the main control terminal 10, the oscilloscope 20, the detector 30 and the test board 40.
In one embodiment of the present invention, the master control terminal 10 may be a computer device capable of running a computer program, such as a tablet computer, a notebook computer, a desktop computer, a server, etc. The computer device may include a processor, memory, a network interface, a display screen, and an input device connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device may include non-volatile storage media, internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory may provide an environment for the operation of the operating system and computer programs in the non-volatile storage media. The network interface of the computer device is used to communicate with an external server through a network connection.
Further, the main control terminal 10 can run VBA (Visual Basic for Applications) program 11. Alternatively, the VBA program 11 may be replaced by running Python/labview/c# programming software in the master 10. The master control terminal 10 may be communicatively connected to the oscilloscope 20 via a network cable (Ethernet) 61. The main control terminal 10 can send an instruction for connecting the oscilloscope 20 through a standard I/O function library programmed by the oscilloscope 20, so as to realize the communication between the VBA program 11 in the main control terminal 10 and the oscilloscope 20. The instruction sent by the master control terminal 10 to the oscilloscope 20 may include a setting instruction and a detection instruction.
In one embodiment of the present invention, the oscilloscope 20 may be used to respond to the debug instruction of the master 10, and build a corresponding test environment on the oscilloscope 20. The test environment may include setting a horizontal axis coordinate scale, a vertical axis coordinate scale, a sampling rate, a trigger channel, a trigger mode, and the like of the oscilloscope 20. The debugging instructions comprise setting instructions and detection instructions.
Specifically, after the main control terminal 10 is communicatively connected to the oscilloscope 20 through the network cable 61 or the USB cable, a setting instruction may be sent to the oscilloscope 20 through the VBA program 11 installed in the main control terminal 10. After the oscilloscope 20 receives the setting instruction, corresponding setting is performed based on the setting instruction, so as to build a corresponding test environment. For example, parameters such as a horizontal axis coordinate scale, a vertical axis coordinate scale, a sampling rate, a trigger channel, a trigger mode, etc. may be configured on the oscilloscope 20, so that corresponding test data can be displayed when the embedded memory 50 is tested later.
The oscilloscope 20 may be used to respond to the detection instruction of the master control terminal 10, so as to make the oscilloscope 20 enter a normal state. For example, the oscilloscope 20 may determine whether the oscilloscope 20 is in a normal state in response to a detection instruction of the master control terminal 10. If the oscilloscope 20 is in a normal state, the test environment is successfully built. If the oscilloscope 20 is in an abnormal state, the test environment is not built, and the main control terminal 10 can repeatedly send a setting instruction to the oscilloscope 20 until the oscilloscope 20 is in a normal state, and the test environment is built successfully.
Specifically, after the test environment is initially set up on the oscilloscope 20, the oscilloscope 20 needs to be detected to determine whether the oscilloscope 20 can enter a normal working state. The problem of display error is prevented when the data of the embedded memory 50 is displayed by the oscilloscope 20 later. Specifically, after the preliminary setting up of the test environment is completed, the master control terminal 10 may issue a detection instruction through the VBA program 11. The detection instructions may be transmitted to the oscilloscope 20 via the network cable 61. After the oscilloscope 20 receives the detection instruction from the main control terminal 10, the oscilloscope 20 can communicate with the main control terminal 10 to judge whether the oscilloscope 20 is in a normal state. When the oscilloscope 20 is in a normal state, it indicates that the oscilloscope 20 can perform testing normally, and the test environment of the oscilloscope 20 is successfully built. When the oscilloscope 20 is in an abnormal state, it indicates that the oscilloscope 20 cannot perform the test normally, and the test environment of the oscilloscope 20 fails to be built.
Further, after the oscilloscope 20 is in the abnormal state, the oscilloscope 20 will feed back a failure instruction to the main control terminal 10. After receiving the failure instruction, the master control terminal 10 may issue a setting instruction to the oscilloscope 20 again. After the oscilloscope 20 receives the setting instruction, a corresponding test environment is rebuilt based on the setting instruction. After the test environment is completed, the main control terminal 10 will send a detection instruction to the oscilloscope 20 again, and determine whether the oscilloscope is in a normal state again. If the oscilloscope 20 is in a normal state, the test environment of the oscilloscope 20 is successfully built. If the oscilloscope 20 is in an abnormal state, the test environment of the oscilloscope 20 is failed to be built. At this time, the main control terminal 10 repeatedly sends a setting instruction and a detection instruction to the oscilloscope 20 until the oscilloscope is in a normal state, which indicates that the test environment of the oscilloscope 20 is successfully built.
In one embodiment of the present invention, the detector 30 may be a Matrix Probe. Oscilloscope 20 may be communicatively coupled to probe 30 via a communications interface (USB) 66. The Probe 30 may be communicatively coupled to the test plate 40 via a Probe 65. During testing of embedded memory 50, it is necessary to communicatively connect all channels in embedded memory 50 to probe 30. For example, when the embedded memory 50 is emmc5.1, emmc5.1 has 8 Data channels, 1 Command channel, 1 Clock channel, and 1 Data strobe channel, so it is necessary to pass through the test board 40 to communicatively connect the probe 30 with all channels in the embedded memory 50, thereby facilitating the transfer of intermediate Data from the corresponding channels into the oscilloscope 20.
In one embodiment of the invention, test board 40 may be an XU4 test board. Test board 40 may be communicatively coupled to embedded memory 50 via an interface (Socket) 62. The test board 40 can be connected with a serial port tool (Tera terminal) 64 on the main control terminal 10 through an asynchronous transceiver (Universal Asynchronous Receiver Transmitter, UART) 63, so that the VBA program 11 in the main control terminal 10 can send a test instruction to the test board 40. Alternatively, an Xshell tool may be installed in the main control terminal 10 instead of the serial port tool 64, and control of the test board 40 may be completed. For example, the test board 40 may respond to the test instruction of the main control terminal 10, and the test board 40 tests the embedded memory 50 based on the test instruction, and transmits the generated intermediate data to the oscilloscope 20 through the corresponding test channel. The oscilloscope 20 may select corresponding intermediate data based on a preset test item, and the oscilloscope 20 generates test data based on the selected intermediate data.
Specifically, after the communication connection of the main control terminal 10, the oscilloscope 20, the probe 30, the test board 40 and the embedded memory 50 is completed, the main control terminal 10 can start to test the embedded memory 50. During testing, the master control end 10 can send a test instruction to the test board 40 through the serial port tool 64. After the test board 40 receives the test instruction, it can control the embedded memory 50 to work, and at this time, the embedded memory 50 can generate different intermediate data based on the test instruction.
Further, since the embedded memory 50 can generate a large amount of intermediate data according to the test instructions, a part of the intermediate data is unnecessary for the oscilloscope 20, and only the appropriate intermediate data needs to be selected from the intermediate data. Therefore, the oscilloscope 20 needs to preset corresponding test items according to the embedded memory 50 to complete the signal test of the embedded memory 50. For example, when a certain test item needs to measure Data and Clock Data simultaneously, the Data channel and Clock channel in the prober 30 need to be opened at this time, so as to complete the synchronous measurement of the Data and Clock Data. For another example, when another test item needs to measure the Command data and the Clock data simultaneously, the Command channel and the Clock channel in the probe 30 need to be turned on at this time, so as to complete the synchronous measurement of the Command data and the Clock data. Accordingly, oscilloscope 20 may select corresponding intermediate data from the intermediate data generated by embedded memory 50 based on a preset test item. In the oscilloscope 20, data is mostly displayed in graphic form. Thus, the oscilloscope 20 can convert the intermediate data into corresponding test data based on the built test environment. The test data may be displayed graphically on the oscilloscope 20. Parameters such as a horizontal axis coordinate scale, a vertical axis coordinate scale, a sampling rate, a trigger channel, a trigger mode and the like of the test data can be displayed on the graph.
The test board 40 can also be used to respond to the termination instruction of the main control terminal 10, the test board 40 stops testing, and the oscilloscope 20 sends the test data to the main control terminal 10. Specifically, when the signal test of the embedded memory 50 is finished, the master control terminal 10 may send a termination instruction to the test board 40. After receiving the termination instruction, the test board 40 stops the signal test on the embedded memory 50. At the same time, the test board 40 can send corresponding end instructions to the oscilloscope 20 via the probe 30. After receiving the end instruction, the oscilloscope 20 uniformly transmits all the stored test data to the main control terminal 10, and performs corresponding processing in the main control terminal 10.
In one embodiment of the present invention, after the master 10 receives the test data, the master 10 may derive the test result based on the test data. For example, the master 10 may assign different variables based on different test data. Thereafter, the master 10 may aggregate all variables, denoted as test results, and derive them. Specifically, after all the test data are acquired by the VBA program 11 in the master 10, in order to facilitate the display of the test data, different variables may be assigned to different test data based on the VBA program 11. The variable is a specified memory location in the programming language of VBA program 11 to hold values that can be changed during script execution. The oscilloscope 20 tests the completed test data, and returns a value, which is assigned to this variable, through a control command written in the VBA program 11. After the VBA program 11 assigns corresponding variables to all the test data, the master 10 may aggregate all the variables to represent the test result and derive the test result. The test result may be exported in an excel table, and each variable may occupy a cell in the excel table, so as to realize automatic exporting of the chip model integrity test data of the embedded memory 50. Of course, the test results may also be derived in other forms, such as mail, pdf.
Referring to fig. 2, the present invention also provides a signal testing method of the memory, where the testing method corresponds to the testing system in the above embodiment one by one. The test method may include the steps of:
step S10, responding to a debugging instruction of a main control end to build a corresponding test environment on an oscilloscope, wherein the debugging instruction comprises a setting instruction and a detection instruction;
step S20, responding to a test instruction of the main control end, testing the embedded memory by the test board based on the test instruction, and generating test data in the oscilloscope;
step S30, responding to a termination instruction of the main control end, stopping testing by the test board, and sending test data to the main control end by the oscilloscope;
and step S40, the main control terminal derives a test result based on the test data.
Referring to fig. 3, in one embodiment of the present invention, when step S10 is performed, specifically, step S10 may include the following steps:
step S11, responding to a setting instruction of a main control end to build a corresponding test environment on the oscilloscope, wherein the test environment comprises a transverse axis coordinate scale, a longitudinal axis coordinate scale, a sampling rate, a trigger channel and a trigger mode of the oscilloscope;
and step S12, responding to a detection instruction of the main control end so as to enable the oscilloscope to enter a normal state.
In one embodiment of the present invention, when step S11 is performed, the master control terminal 10 may be a computer device capable of running a computer program, such as a tablet computer, a notebook computer, a desktop computer, a server, or the like. VBA program 11 may be run within master 10. The main control terminal 10 can be in communication connection with the oscilloscope 20 through the network cable 61, and then the main control terminal 10 can send an instruction for connecting the oscilloscope 20 through a standard I/O function library programmed by the oscilloscope 20 so as to realize the communication between the VBA program 11 in the main control terminal 10 and the oscilloscope 20.
Specifically, after the main control terminal 10 is communicatively connected to the oscilloscope 20 through the network cable 61, a setting instruction may be sent to the oscilloscope 20 through the VBA program 11 installed in the main control terminal 10. After the oscilloscope 20 receives the setting instruction, corresponding setting is performed based on the setting instruction, so as to build a corresponding test environment. For example, parameters such as a horizontal axis coordinate scale, a vertical axis coordinate scale, a sampling rate, a trigger channel, a trigger mode, etc. may be configured on the oscilloscope 20, so that corresponding test data can be displayed when the embedded memory 50 is tested later.
Referring to fig. 4, in one embodiment of the present invention, when step S12 is performed, specifically, step S12 may include the following steps:
step S121, responding to a detection instruction of a main control end, and judging whether the oscilloscope is in a normal state or not;
step S122, if the oscilloscope is in a normal state, the test environment is successfully built;
step S123, if the oscilloscope is in an abnormal state, the test environment is built up and fails, and the main control terminal repeatedly sends a setting instruction to the oscilloscope until the oscilloscope is in a normal state, and at the moment, the test environment is built up successfully.
In one embodiment of the present invention, after a test environment is initially built on the oscilloscope 20, the oscilloscope 20 needs to be detected to determine whether the oscilloscope 20 can enter a normal working state. The problem of display error is prevented when the data of the embedded memory 50 is displayed by the oscilloscope 20 later. Specifically, after the preliminary setting up of the test environment is completed, the master control terminal 10 may issue a detection instruction through the VBA program 11. The detection instructions may be transmitted to the oscilloscope 20 via the network cable 61. After the oscilloscope 20 receives the detection instruction from the main control terminal 10, the oscilloscope 20 can communicate with the main control terminal 10 to judge whether the oscilloscope 20 is in a normal state. When the oscilloscope 20 is in a normal state, it indicates that the oscilloscope 20 can perform testing normally, and the test environment of the oscilloscope 20 is successfully built. When the oscilloscope 20 is in an abnormal state, it indicates that the oscilloscope 20 cannot perform the test normally, and the test environment of the oscilloscope 20 fails to be built.
Further, after the oscilloscope 20 is in the abnormal state, the oscilloscope 20 will feed back a failure instruction to the main control terminal 10. After receiving the failure instruction, the master control terminal 10 may issue a setting instruction to the oscilloscope 20 again. After the oscilloscope 20 receives the setting instruction, a corresponding test environment is rebuilt based on the setting instruction. After the test environment is completed, the main control terminal 10 will send a detection instruction to the oscilloscope 20 again, and determine whether the oscilloscope is in a normal state again. If the oscilloscope 20 is in a normal state, the test environment of the oscilloscope 20 is successfully built. If the oscilloscope 20 is in an abnormal state, the test environment of the oscilloscope 20 is failed to be built. At this time, the main control terminal 10 repeatedly sends a setting instruction and a detection instruction to the oscilloscope 20 until the oscilloscope is in a normal state, which indicates that the test environment of the oscilloscope 20 is successfully built.
Referring to fig. 5, in one embodiment of the present invention, when step S20 is performed, specifically, step S20 may include the following steps:
step S21, responding to a test instruction of the main control end, testing the embedded memory by the test board based on the test instruction, and transmitting the generated intermediate data to the oscilloscope through a corresponding test channel;
step S22, the oscilloscope selects corresponding intermediate data based on a preset test item;
and S23, the oscilloscope generates test data based on the selected intermediate data.
In one embodiment of the present invention, when the testing of the embedded memory 50 is required in step S21, the embedded memory 50 may be communicatively connected to the test board 40 through the interface 62 to complete the testing in the test board 40. The test board 40 may be in communication with the main control terminal 10. For example, the test board 40 may be communicatively connected to the serial port tool 64 on the master control terminal 10 through the asynchronous transceiver 63, and further the VBA program 11 in the master control terminal 10 may issue a test instruction to the test board 40. The test plate 40 may also be communicatively coupled to the probe 30 via a probe 65, and the probe 30 may be communicatively coupled to the oscilloscope 20 via a communication interface 66.
After the communication connection of the main control terminal 10, the oscilloscope 20, the probe 30, the test board 40 and the embedded memory 50 is completed, the main control terminal 10 can start to test the embedded memory 50. During testing, the master control end 10 can send a test instruction to the test board 40 through the serial port tool 64. After the test board 40 receives the test instruction, it can control the embedded memory 50 to work, and at this time, the embedded memory 50 can generate different intermediate data based on the test instruction. During testing of embedded memory 50, it is necessary to communicatively connect all channels in embedded memory 50 to probe 30. For example, when the embedded memory 50 is emmc5.1, emmc5.1 has 8 Data channels, 1 Command channel, 1 Clock channel, and 1 Data strobe channel, so it is necessary to pass through the test board 40 to communicatively connect the probe 30 with all channels in the embedded memory 50, thereby facilitating the transfer of intermediate Data from the corresponding channels into the oscilloscope 20.
When step S22 is performed, in particular, since the embedded memory 50 can generate a large amount of intermediate data according to the test instruction. For the oscilloscope 20, a portion of the intermediate data is unnecessary, and only the appropriate intermediate data need be selected from the intermediate data. Therefore, the oscilloscope 20 needs to preset corresponding test items according to the embedded memory 50 to complete the signal test of the embedded memory 50. For example, when a certain test item needs to measure Data and Clock Data simultaneously, the Data channel and Clock channel in the prober 30 need to be opened at this time, so as to complete the synchronous measurement of the Data and Clock Data. For another example, when another test item needs to measure the Command data and the Clock data simultaneously, the Command channel and the Clock channel in the probe 30 need to be turned on at this time, so as to complete the synchronous measurement of the Command data and the Clock data. Accordingly, the oscilloscope 20 selects corresponding intermediate data from the intermediate data generated by the embedded memory 50 based on the preset test items.
Further, when step S23 is performed, data is displayed in the form of a graphic in the oscilloscope 20 in most cases. Thus, the oscilloscope 20 can convert the intermediate data into corresponding test data based on the built test environment. The test data may be displayed on the oscilloscope 20 in a graphical form, where parameters such as a horizontal axis coordinate scale, a vertical axis coordinate scale, a sampling rate, a trigger channel, a trigger mode, etc. of the test data may be displayed on the graph.
In one embodiment of the present invention, when step S30 is performed, specifically, when the signal test of the embedded memory 50 is finished, the master 10 may issue a termination instruction to the test board 40. After receiving the termination instruction, the test board 40 stops the signal test on the embedded memory 50. At the same time, the test board 40 can send corresponding end instructions to the oscilloscope 20 via the probe 30. After receiving the end instruction, the oscilloscope 20 uniformly transmits all the stored test data to the main control terminal 10, and performs corresponding processing in the main control terminal 10.
Referring to fig. 6, in one embodiment of the present invention, when step S40 is performed, specifically, step S40 may include the following steps:
step S41, the main control terminal endows different variables based on different test data;
step S42, the master control terminal gathers all variables, and the variables are expressed as test results and are exported.
In one embodiment of the present invention, after all the test data are acquired by the VBA program 11 in the master 10, different variables may be given to different test data based on the VBA program 11 in order to facilitate the display of the test data. The variable is a specified memory location in the programming language of VBA program 11 to hold values that can be changed during script execution. The oscilloscope 20 tests the completed test data, and returns a value, which is assigned to this variable, through a control command written in the VBA program 11. After the VBA program 11 assigns corresponding variables to all the test data, the master 10 may aggregate all the variables to represent the test result and derive the test result. The test result may be exported in an excel table, and each variable may occupy a cell in the excel table, so as to realize automatic exporting of the chip model integrity test data of the embedded memory 50. Of course, the test results may also be derived in other forms, such as mail, pdf.
Therefore, in the scheme, the signal test of the embedded memory can be automatically completed, and the signal test efficiency can be effectively improved. Meanwhile, the test result is automatically exported, so that errors can be avoided when the test result is manually recorded, and the accuracy of the test result is ensured.
The foregoing embodiments are merely illustrative of the principles of the present invention and their effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
In the description herein, numerous specific details are provided, such as examples of components and/or methods, to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that an embodiment of the invention can be practiced without one or more of the specific details, or with other apparatus, systems, components, methods, components, materials, parts, and so forth. In other instances, well-known structures, materials, or operations are not specifically shown or described in detail to avoid obscuring aspects of embodiments of the invention.
Reference throughout this specification to "one embodiment," "an embodiment," or "a particular embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment, and not necessarily all embodiments, of the present invention. Thus, the appearances of the phrases "in one embodiment," "in an embodiment," or "in a specific embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics of any specific embodiment of the present invention may be combined in any suitable manner with one or more other embodiments. It will be appreciated that other variations and modifications of the embodiments of the invention described and illustrated herein are possible in light of the teachings herein and are to be considered as part of the spirit and scope of the invention.
It will also be appreciated that one or more of the elements shown in the figures may also be implemented in a more separated or integrated manner, or even removed because of inoperability in certain circumstances or provided because it may be useful depending on the particular application.
In addition, any labeled arrows in the drawings/figures should be considered only as exemplary, and not limiting, unless otherwise specifically indicated. Furthermore, the term "or" as used herein is generally intended to mean "and/or" unless specified otherwise. Combinations of parts or steps will also be considered as being noted where terminology is foreseen as rendering the ability to separate or combine is unclear.
As used in the description herein and throughout the claims that follow, unless otherwise indicated, "a", "an", and "the" include plural references. Also, as used in the description herein and throughout the claims that follow, unless otherwise indicated, the meaning of "in …" includes "in …" and "on …".
The above description of illustrated embodiments of the invention, including what is described in the abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed herein. Although specific embodiments of, and examples for, the invention are described herein for illustrative purposes only, various equivalent modifications are possible within the spirit and scope of the present invention, as those skilled in the relevant art will recognize and appreciate. As noted, these modifications can be made to the present invention in light of the foregoing description of illustrated embodiments of the present invention and are to be included within the spirit and scope of the present invention.
The systems and methods have been described herein in general terms as being helpful in understanding the details of the present invention. Furthermore, various specific details have been set forth in order to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that an embodiment of the invention can be practiced without one or more of the specific details, or with other apparatus, systems, assemblies, methods, components, materials, parts, and/or the like. In other instances, well-known structures, materials, and/or operations are not specifically shown or described in detail to avoid obscuring aspects of embodiments of the invention.
Thus, although the invention has been described herein with reference to particular embodiments thereof, a latitude of modification, various changes and substitutions are intended in the foregoing disclosures, and it will be appreciated that in some instances some features of the invention will be employed without a corresponding use of other features without departing from the scope and spirit of the invention as set forth. Therefore, many modifications may be made to adapt a particular situation or material to the essential scope and spirit of the present invention. It is intended that the invention not be limited to the particular terms used in following claims and/or to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include any and all embodiments and equivalents falling within the scope of the appended claims. Accordingly, the scope of the invention should be determined only by the following claims.
Claims (7)
1. A signal testing system for a memory, comprising:
the main control end is used for sending out a debugging instruction, a testing instruction and a termination instruction;
the oscilloscope is connected with the main control end in a communication way and used for building a corresponding test environment according to the debugging instruction; and
the test board is in communication connection with the main control end and the oscilloscope, the embedded memory is in communication connection with the test board, and the test board tests the embedded memory according to the test instruction and generates test data in the oscilloscope;
the detector is in communication connection with the test board and the oscilloscope, and the oscilloscope selects a corresponding test channel between the detector and the test board based on a preset test item;
the test board is further used for responding to the test instruction, testing the embedded memory based on the test instruction, transmitting the generated intermediate data to the oscilloscope through a corresponding test channel, selecting the corresponding intermediate data based on a preset test item, and generating test data based on the selected intermediate data;
and after the main control end sends out the termination instruction, the test board stops testing, and the oscilloscope sends the test data to the main control end.
2. The signal testing system of claim 1, wherein the debug instructions include a set instruction and a detect instruction, the oscilloscope is configured to respond to the set instruction to set a corresponding test environment, and the oscilloscope is configured to respond to the detect instruction to enter a normal state.
3. The signal testing system of claim 1, wherein said master is further configured to assign different variables based on different test data, aggregate all of said variables, represent test results, and derive.
4. A method for testing signals of a memory, comprising:
responding to a debugging instruction of the main control end to set a corresponding test environment on the oscilloscope;
responding to the test instruction of the main control end, testing the embedded memory by the test board based on the test instruction, and transmitting the generated intermediate data to the oscilloscope through a corresponding test channel;
the oscilloscope selects corresponding intermediate data based on a preset test item;
the oscilloscope generates test data based on the selected intermediate data;
and responding to a termination instruction of the main control end, stopping testing by the test board, and sending the test data to the main control end by the oscilloscope.
5. The method according to claim 4, wherein the step of setting the corresponding test environment on the oscilloscope in response to the debug instruction of the master terminal comprises:
responding to a setting instruction of the main control end to set a corresponding test environment on the oscilloscope;
responding to the detection instruction of the main control end so as to enable the oscilloscope to enter a normal state.
6. The method according to claim 5, wherein the step of responding to the detection instruction of the master terminal to cause the oscilloscope to enter the normal state comprises:
responding to the detection instruction of the main control end, and judging whether the oscilloscope is in a normal state or not;
if the oscilloscope is in a normal state, the test environment is successfully built;
if the oscilloscope is in an abnormal state, the test environment is built up and fails, and the main control end repeatedly sends the setting instruction to the oscilloscope until the oscilloscope is in a normal state, and at the moment, the test environment is built up successfully.
7. The method according to claim 4, wherein after the step of stopping the test by the test board in response to the termination instruction of the main control terminal, the oscilloscope transmits the test data to the main control terminal, further comprising:
the main control terminal gives different variables based on different test data;
and the main control terminal gathers all the variables, represents the variables as test results and exports the variables.
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Denomination of invention: A Signal Testing System and Testing Method for Memory Granted publication date: 20230922 Pledgee: Hefei SME financing Company limited by guarantee Pledgor: Hefei kangxinwei Storage Technology Co.,Ltd. Registration number: Y2024980005508 |