CN109656756B - Multi-core CPU board debugging method and device and mobile storage medium - Google Patents
Multi-core CPU board debugging method and device and mobile storage medium Download PDFInfo
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- CN109656756B CN109656756B CN201811341241.7A CN201811341241A CN109656756B CN 109656756 B CN109656756 B CN 109656756B CN 201811341241 A CN201811341241 A CN 201811341241A CN 109656756 B CN109656756 B CN 109656756B
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- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
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Abstract
The invention discloses a debugging method of a CPU board card of a multi-core central processing unit, which is characterized by comprising the following steps: the method comprises the following steps: connecting the multi-core CPU board card to be tested with a memory in which a test program and a production program are stored; the CPU core in the multi-core CPU board card reads and runs the test program from the memory to acquire the execution result of at least one test item; determining a test result of the multi-core CPU board card according to the execution result; and if the test result is qualified, the multi-core CPU board card reads from the memory and stores the production program. The invention also discloses a debugging device of the CPU board card of the multi-core central processing unit and a mobile storage medium.
Description
Technical Field
The invention relates to a multi-core processor, in particular to a method and a device for debugging a CPU board card of a multi-core central processing unit and a mobile storage medium.
Background
Currently, the debugging of multi-core CPU board cards which are applied more mainly includes the following two types:
(1) and downloading a test program to the multi-core CPU board card through the programmer, and downloading a formal production program to the multi-core CPU board card through the programmer after the test is finished.
(2) And inserting the boot erasable memory written with the boot program into a chip holder of the multi-core CPU board card, connecting a PC through an Ethernet after the boot erasable memory is powered on, downloading the test program to the multi-core CPU board card by using the PC, and downloading the production program to the multi-core CPU board card by using the PC after the test is finished.
Both of the above test methods have significant disadvantages:
the method (1) needs to frequently use the erasing and writing program of the programmer, and production debugging personnel needs to use the programmer to connect the programmer on different board cards, download the test program, observe the test result, download the production program and disconnect the programmer, so that the correctness of operation is difficult to ensure, the quality of products is affected, and the production working efficiency is greatly limited. The method (2) omits the complicated procedure of continuously plugging and unplugging the programmer, but needs to operate a PC to finish the same repeated work, and increases the networking complexity; when a plurality of board cards of the same type are connected to a network at the same time, the situation of network address conflict can occur, so that the test fails; if the board cards are provided with different IPs, a plurality of boot memories are required to be prepared for the board cards of the same type, and the situations of wrong testing and production procedures are easy to occur.
Disclosure of Invention
The embodiment of the invention provides a method and a device for debugging a multi-core CPU board card and a mobile storage medium.
The technical scheme of the invention is realized as follows:
on one hand, the method for debugging the multi-core CPU board card comprises the following steps:
connecting the multi-core CPU board card to be tested with a memory in which a test program and a production program are stored;
the CPU core in the multi-core CPU board card reads and runs the test program from the memory to acquire the execution result of at least one test item;
determining a test result of the multi-core CPU board card according to the execution result;
and if the test result is qualified, reading the production program from the memory by the multi-core CPU board card and storing the production program.
Further, before the CPU core in the multi-core CPU board reads and runs the test program from the memory to obtain the execution result of the at least one test item, the method further includes:
and the CPU core in the multi-core CPU board card reads and runs the system program from the memory, and monitors the running of the test program through the running of the system program.
Further, the method further comprises:
acquiring the execution state information of the test program by using the system program;
displaying the execution state information on a user interface;
detecting a user instruction acting on the execution state information;
the monitoring the operation of the test program through the operation of the system program includes:
and controlling the running of the test program according to the user instruction.
Further, the reading and running of the system program from the memory by the CPU core in the multi-core CPU board includes:
reading and running the system program from the memory by a first CPU core of the multi-core CPU board card;
the reading and running of the test program from the memory by the CPU core in the multi-core CPU board card comprises the following steps:
reading and running a test program from the memory by a second CPU core in the multi-core CPU board card; wherein the second CPU core is different from the first CPU core.
Further, the reading and running of the system program from the memory by the first CPU core of the multi-core CPU board includes:
reading and running the system program from the first partition of the memory by the first CUP core;
the reading and running of the test program from the memory by the second CPU core in the multi-core CPU board includes:
reading and running, by the second CPU core, a test program from a second partition of the memory;
wherein the first partition and the second partition are different; and/or the partition formats of the first partition and the second partition are different.
Further, the reading and running of the test program from the memory by the CPU core in the multi-core CPU board to obtain the execution result of the at least one test item includes:
and selecting a test element matched with the tested function module of the multi-core CPU board card from the test program, and testing the tested function module.
Further, the selecting a test element adapted to the tested function module of the multi-core CPU board from the test program to test the tested function module includes at least one of:
selecting a test element matched with the tested function module of the multi-core CPU board card from the test program, and testing the tested function module, wherein the test element comprises at least one of the following components:
selecting a communication element from the test program, and testing a functional module which receives a user instruction and performs corresponding operation;
selecting a test program of a sampling element from the test programs, and testing a functional module for detecting the sampling precision of the multi-core CPU board card;
selecting an input/output (IO) element from the test program, and testing a functional module for detecting general input/output (GPIO) hardware and an extended IO pin of the multi-core CPU board card;
selecting a memory test element from the test program, and testing a functional module for detecting the performance of the storage equipment on the multi-core CPU board card;
and selecting an interface element from the test program, and testing the functional module for detecting the plug-in of the multi-core CPU board card and an external interface.
Further, the method further comprises:
and if the test result is unqualified, determining the fault reason.
The invention also provides a multi-core CPU board card debugging device, which comprises:
the connection module is used for connecting the multi-core CPU board card to be tested with a memory in which a test program and a production program are stored;
the running module is used for reading and running the test program from the memory to acquire an execution result of at least one test item by a CPU core in the multi-core CPU board card;
the determining module is used for determining the test result of the multi-core CPU board card according to the execution result;
and the downloading module is used for reading the multi-core CPU board card from the memory and storing the production program if the test result is qualified.
The present invention also provides a portable storage medium, which stores the following program:
the test program is used for testing the performance of the multi-core CPU board card;
the production program is a program code stored on a storage medium of a multi-core CPU board card after leaving a factory;
and the system program is used for scheduling the test program, receiving the execution result of the test program and downloading the production program to a storage medium of the CPU board card.
The invention provides a method and a device for debugging a multi-core CPU board card, which are characterized in that the multi-core CPU board card to be tested is connected with a memory in which a test program and a production program are stored; the CPU core in the multi-core CPU board card reads and runs the test program from the memory to acquire the execution result of at least one test item; determining a test result of the multi-core CPU board card according to the execution result; and if the test result is qualified, reading the production program from the memory by the multi-core CPU board card and storing the production program. The related debugging method for the multi-core CPU board usually needs to repeatedly download a test program and a production program from a network or an external storage, or needs to connect a PC (personal computer) through a peripheral network so as to finish the debugging of the multi-core CPU board through the PC. The method and the device have the advantages that the memory is connected with the multi-core CPU board card to be tested, and the test program and the production program are stored in the memory, compared with the related method, the link of repeatedly downloading the test program and the production program from a network or external storage is omitted, the peripheral networking cost is saved, the debugging efficiency of the multi-core CPU board card is improved, the labor cost is saved, and the reliability and the safety of the source of the test program and the source of the production program for debugging the multi-core CPU board card are ensured.
Drawings
Fig. 1 is a schematic flowchart of a method for debugging a multi-core CPU board according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a multicore CPU board debugging apparatus according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a composition structure of a removable storage medium according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a multi-core CPU board debugging device according to an embodiment of the present invention;
fig. 5 is a schematic flowchart of another method for debugging a multi-core CPU board according to an embodiment of the present invention.
Detailed Description
In various embodiments of the invention, the memory is connected with the multi-core CPU board card to be tested, and the test program and the production program are stored in the memory, compared with the related method, the link of repeatedly downloading the test program and the production program from a network or an external memory is omitted, and the peripheral networking cost is also saved.
Fig. 1 is a schematic flowchart of a method for debugging a multi-core CPU board according to an embodiment of the present invention, where as shown in fig. 1, the method for debugging a multi-core CPU board includes the following steps:
step 101: connecting the multi-core CPU board card to be tested with a memory in which a test program and a production program are stored;
step 102: the CPU core in the multi-core CPU board card reads and runs the test program from the memory to acquire the execution result of at least one test item;
step 103: determining a test result of the multi-core CPU board card according to the execution result;
step 104: and if the test result is qualified, reading the production program from the memory by the multi-core CPU board card and storing the production program.
The test program is used for testing the performance of the multi-core CPU board card. The test program can be developed based on an element form, the test program comprises at least one test element, the test element is a function to be tested or is divided by the type of a module to be tested, the purpose of realizing a specific test function is achieved, the test program does not depend on specific bottom hardware, has better normativity and universality, and can be conveniently transplanted to single board test and program downloading of other types of board cards.
The test elements mainly include communication elements, sampling elements, IO (Input/Output) test elements, memory test elements, interface elements, and the like. The communication element is used for receiving the debugging instruction of the management board and carrying out corresponding operation; the sampling element is mainly used for calibrating the sampling characteristic of the board and ensuring that the sampling precision of the board card meets the requirements of on-site protection and measurement; the IO test element has the function of detecting whether GPIO (General Purpose Input/Output) hardware and an extended IO pin of the CPU card can work normally; the memory test element ensures that the performance of the storage equipment on the multi-core CPU board card reaches the standard; the interface element tests whether the multi-core CPU board card plug-in and an external interface work normally.
The production program is a program code stored in a storage medium on a multi-core CPU board after shipment, and the program code may be used for application of the multi-core CPU board after shipment.
The multi-core CPU board card is connected with the memory and can read data on the memory. The memory is a storage device in a physical form, and can adopt a mobile storage device, such as: the device comprises a U disk, an SD (Secure Digital Memory) card, a mobile hard disk and the like, wherein the U disk and the mobile hard disk are inserted into a USB interface on the multi-core CPU board card detection equipment to be detected, and the SD card is inserted into an SD card base of the multi-core CPU board card detection equipment to be detected. Compared with fixed storage equipment, the mobile storage equipment is adopted, and the same mobile storage equipment with the test program and the generation program stored therein can be used for debugging a plurality of multi-core CPU board cards of the same model, so that the utilization rate of the mobile storage equipment is improved, and possibility is provided for the design of the standardized debugging process of the multi-core CPU board cards.
The execution result is a test result of one functional module obtained by running the test program. The function module determines a test unit according to the model of the multi-core CPU board card to be tested and each specific function to be tested, and the test unit is the minimum execution unit when the test program is scheduled. The model of each multi-core CPU board card corresponds to a plurality of different functional modules. When the test result of each functional module corresponding to the model is qualified, the test result of the multi-core CPU board to be tested is qualified; and when at least one of the test results of the functional modules corresponding to the models of the multi-core CPU board card to be tested is unqualified, the test result of the multi-core CPU board card to be tested is unqualified.
The functional module can include: receiving a user instruction and performing corresponding operation function test; performing a function test for detecting whether the sampling precision of the multi-core CPU board card meets the requirement; testing the function of detecting whether the GPIO hardware and the expansion IO pins of the multi-core CPU board card work normally; the function test is carried out on whether the performance of the storage equipment on the multi-core CPU board card meets the requirement or not; and testing the function of detecting whether the plug-in of the multi-core CPU board card and an external interface work normally.
Further, before the CPU core in the multi-core CPU board reads and runs the test program from the memory to obtain the execution result of the at least one test item, the method further includes:
and the CPU core in the multi-core CPU board card reads and runs the system program from the memory, and monitors the running of the test program through the running of the system program.
The system program is mainly used for: carry out instruction transmission with debugging appearance management board, include: acquiring an instruction from a debugging instrument management board, controlling the running of a test program according to the instruction, and feeding back the running state information of the test program to the debugging instrument management board; a boot test program, the boot test program comprising: controlling the running of the test program, and receiving state information returned by the test program; and when receiving a corresponding instruction sent by the management board, downloading the production program.
Further, the method further comprises:
acquiring the execution state information of the test program by using the system program;
displaying the execution state information on a user interface;
detecting a user instruction acting on the execution state information;
the monitoring the operation of the test program through the operation of the system program includes:
and controlling the running of the test program according to the user instruction.
The user interface is displayed in the debugging instrument management board, and can receive the instruction of the user and feed back the execution result of the test program.
The user instruction can be an automatically-running control program compiled based on different models of the multi-core CPU board card; or an instruction sent manually to control the running of the test program on the multi-core CPU board card to be tested.
Further, the reading and running of the system program from the memory by the CPU core in the multi-core CPU board includes:
reading and running the system program from the memory by a first CPU core of the multi-core CPU board card;
the reading and running of the test program from the memory by the CPU core in the multi-core CPU board card comprises the following steps:
reading and running a test program from the memory by a second CPU core in the multi-core CPU board card; wherein the second CPU core is different from the first CPU core.
In the debugging process of the multi-core CPU board card, although different CPU cores run simultaneously and extra transmission resources are consumed, the system program and the test program are respectively run by the different CPU cores of the multi-core CPU board card to be tested because the system program and the test program need to consume larger CPU resources, compared with the case that the system program and the test program are run by the same CPU core simultaneously, the debugging time of a single multi-core CPU board card is still shortened, and the debugging efficiency of the multi-core CPU board card is further improved.
Further, the reading and running of the system program from the memory by the first CPU core of the multi-core CPU board includes:
reading and running the system program from the first partition of the memory by the first CUP core;
the reading and running of the test program from the memory by the second CPU core in the multi-core CPU board includes:
reading and running, by the second CPU core, a test program from a second partition of the memory;
wherein the first partition and the second partition are different; and/or the partition formats of the first partition and the second partition are different.
Dividing the memory into different areas according to the capacity of the memory and the file sizes (sizes) of the system program, the test program and the production program, and respectively storing the system program, the test program and the production program so as to facilitate the reading, writing and management of the programs; the memory can be divided into different partitions according to the actual operating environment and the coding requirement, and the system program, the test program and the production program are stored in different partitions, so that the development, operation and maintenance are facilitated. A memory partitionable partition comprising: NTFS (New Technology File System) partition, FAT32(File Allocation Table) partition, linux partition, and the like.
Further, the reading and running of the test program from the memory by the CPU core in the multi-core CPU board to obtain the execution result of the at least one test item includes:
and selecting a test program of the test element matched with the tested function module of the multi-core CPU board card from the test programs, and testing the tested function module.
Further, the selecting a test program of a test element adapted to the tested function module of the multi-core CPU board from the test programs to test the tested function module includes at least one of:
selecting a test program of the communication element from the test programs, and testing the functional module which receives the user instruction and performs corresponding operation;
selecting a test program of a sampling element from the test programs, and testing a functional module for detecting whether the sampling precision of the multi-core CPU board card meets the requirement;
selecting a test program of an input/output (IO) element from the test programs, and testing a functional module for detecting whether the general input/output (GPIO) hardware of the multi-core CPU board card and the expansion IO pin work normally;
selecting a test program of a memory test element from the test programs, and testing a functional module for detecting whether the performance of the storage equipment on the multi-core CPU board meets the requirement;
and selecting a test program of an interface element from the test programs, and testing the functional module for detecting whether the plug-in of the multi-core CPU board card and an external interface work normally.
Further, the method further comprises:
and if the test result is unqualified, determining the fault reason.
The fault reason can be determined based on an abnormal report detected by the multi-core CPU board card. Since the test program is developed based on an element form, the test program includes at least one test element, and therefore, the exception report of the multi-core CPU board detection obtained by the test program is a report of the result of the detection performed based on each test element. And through the abnormal report detected by the multi-core CPU board card, the fault element can be positioned and repaired. For example:
the communication element is in failure, and relevant components which receive the user instruction and carry out corresponding operation are repaired;
when the sampling element fails, repairing related components sampled by the multi-core CPU board card;
repairing GPIO hardware and extended IO pins of the multi-core CPU board card when the IO element fails;
the memory test element fails, and the storage equipment on the multi-core CPU board card is repaired;
and if the interface element fails, modifying and debugging the plug-in of the multi-core CPU board card.
Fig. 2 is a schematic structural diagram of a multi-core CPU board debugging device provided in an embodiment of the present invention, including:
the connection module 201 is used for connecting the multi-core CPU board to be tested with a memory in which a test program and a production program are stored;
the running module 202 is configured to read and run the test program from the memory to obtain an execution result of at least one test item for a CPU core in the multi-core CPU board;
a determining module 203, configured to determine a test result of the multi-core CPU board according to the execution result;
and a downloading module 204, configured to, if the test result is qualified, read the production program from the memory by the multi-core CPU board, and store the production program.
Fig. 3 is a schematic diagram of a composition structure of a removable storage medium according to an embodiment of the present invention, where the storage medium stores the following programs:
a test program 301, a program code for testing the performance of the multicore CPU board;
a production program 302, which is a program code stored in a storage medium of a multi-core CPU board after leaving the factory;
and the system program 303 is configured to schedule the test program, receive an execution result of the test program, and download the production program to the storage medium of the CPU board.
Fig. 4 is a schematic structural diagram of a multi-core CPU board debugging device according to an embodiment of the present invention, and as shown in fig. 4, the multi-core CPU board debugging device includes a management board, a multi-core CPU board, and an SD card selecting and reading/writing circuit. The management board and the multi-core CPU board are communicated through a CAN-FD (Controller area network with Flexible Data rate) bus, and the communication rate CAN reach 5-10 Mbps. When the CPU board card is electrified, the SD card selection and read-write circuit is activated, and the core 1 of the multi-core CPU board card of the CPU automatically loads a test program from the SD card.
The testing method mainly comprises the steps that the core 1 of the multi-core CPU board card and the core 2 of the multi-core CPU board card independently run respective programs and are developed based on modular testing.
And the core 1 of the multi-core CPU board card runs a system program, provides a bottom layer driving interface for an application program code, guides a test program, reads a production program from the SD card when receiving a corresponding instruction of the management board, and carries the production program to the flash memory of the multi-core CPU board card to realize the automatic downloading function of the program.
The core 2 of the multi-core CPU board card runs a test program and is developed based on modularization, each functional module does not depend on specific bottom hardware, and the multi-core CPU board card has better normativity and universality and can be conveniently transplanted to single board tests and program downloads of other types of board cards. The test elements mainly comprise communication elements, sampling elements, IO test elements, memory test elements, interface elements and the like. The communication element is used for receiving the debugging instruction of the management board and carrying out corresponding operation; the sampling element is mainly used for calibrating the sampling characteristic of the board and ensuring that the sampling precision of the board card meets the requirements of on-site protection and measurement; the IO test element has the function of detecting whether the GPIO hardware and the extended IO pin of the CPU card can work normally or not; the memory test element ensures that the performance of the storage equipment on the board card reaches the standard; the interface element tests whether the plug-in of the multi-core CPU board card and an external interface work normally.
Fig. 5 is a schematic flowchart of another method for debugging a multi-core CPU board according to an embodiment of the present invention, as shown in fig. 5:
step 501: the multi-core CPU board card is connected with a power supply;
step 502: the kernel 1 of the multi-kernel CPU board card runs a bootstrap program from the SD card;
step 503: and performing modular test on the cores 2 of the multi-core CPU board card. If the test result is up to standard, the step 504 is executed; if the test result is not up to standard, the step 507 is operated;
step 504: downloading a production program by the multi-core CPU board card;
step 505: generating a normal test report;
step 506: the multi-core CPU board card can be normally used;
step 507: generating an abnormal test report;
step 508: and maintaining the multi-core CPU board card. The repair is performed based on the exception test report generated in step 507.
The embodiment of the invention provides a debugging method flow of a multi-core CPU board card, which comprises the following steps:
(1) preparing a common SD card which is divided into two partitions of FAT32 and Linux;
(2) storing a boot program and a production program on a FAT32 partition of the SD card, and storing a test program in a Linux partition;
(3) inserting the SD card into an SD card base of a multi-core CPU board card to be tested;
(4) after the power is on, the SD card selection circuit is activated, and a bootstrap program in the SD card automatically guides the CPU board card to run a test program;
(5) a core 1 of the multi-core CPU board card runs a system program, and a core 2 of the multi-core CPU board card runs a DSP (Digital Signal Processing) test program;
(6) the debugging instrument management board interacts with the CPU board card through the CAN-FD bus to complete the control of each test element;
(7) automatically downloading a production program after the test is qualified, and forming a standardized test report;
(8) the unqualified test board card actively finishes the test operation, automatically locates the fault reason, forms a standardized test report and reminds production personnel to check and analyze;
(9) the test is ended.
The system program operated by the core 1 of the multi-core CPU board card mainly provides a bottom layer driving interface for an application program code, guides a test program, reads a production program from the SD card when receiving a corresponding instruction of the management board, and carries the production program to the flash memory of the CPU board card to realize a program downloading function.
The DSP test program is developed based on an element form, is divided by functional module types to realize specific test functions, does not depend on specific bottom hardware, has better normativity and universality, and can be conveniently transplanted to single board test and program download of other types of board cards.
The test elements mainly comprise communication elements, sampling elements, IO test elements, memory test elements, interface elements and the like. The communication element is used for receiving the debugging instruction of the management board and carrying out corresponding operation; the sampling element is mainly used for calibrating the sampling characteristic of the board and ensuring that the sampling precision of the board card meets the requirements of on-site protection and measurement; the IO test element has the function of detecting whether the GPIO hardware and the extended IO pin of the multi-core CPU board card can work normally or not; the memory test element ensures that the performance of the storage equipment on the multi-core CPU board card reaches the standard; the interface element tests whether the plug-in of the multi-core CPU and an external interface work normally.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.
Claims (10)
1. A multi-core central processing unit CPU board card debugging method is characterized in that: the method comprises the following steps:
connecting the multi-core CPU board card to be tested with a memory in which a test program and a production program are stored; the production program refers to a program code stored on a storage medium of a multi-core CPU board card after leaving a factory; the test program is used for testing the performance of the multi-core CPU board card;
the memory refers to a mobile storage device in a physical form;
the CPU core in the multi-core CPU board card reads and runs the test program from the memory to acquire the execution result of at least one test item;
determining a test result of the multi-core CPU board card according to the execution result;
and if the test result is qualified, reading the production program from the memory by the multi-core CPU board card and storing the production program.
2. The method according to claim 1, characterized in that:
before the CPU core in the multi-core CPU board reads and runs the test program from the memory to obtain the execution result of the at least one test item, the method further includes:
and the CPU core in the multi-core CPU board card reads and runs the system program from the memory, and monitors the running of the test program through the running of the system program.
3. The method of claim 2, further comprising:
acquiring the execution state information of the test program by using the system program;
displaying the execution state information on a user interface;
detecting a user instruction acting on the execution state information;
the monitoring the operation of the test program through the operation of the system program includes:
and controlling the running of the test program according to the user instruction.
4. The method according to claim 2, characterized in that: the reading and running of the system program from the memory by the CPU core in the multi-core CPU board card comprises the following steps:
reading and running the system program from the memory by a first CPU core of the multi-core CPU board card;
the reading and running of the test program from the memory by the CPU core in the multi-core CPU board card comprises the following steps:
reading and running a test program from the memory by a second CPU core in the multi-core CPU board card; wherein the second CPU core is different from the first CPU core.
5. The method of claim 4, wherein reading and running the system program from the memory by the first CPU core of the multi-core CPU board comprises:
reading and running the system program from the first partition of the memory by the first CPU core;
the reading and running of the test program from the memory by the second CPU core in the multi-core CPU board includes:
reading and running, by the second CPU core, a test program from a second partition of the memory;
wherein the first partition and the second partition are different; and/or the partition formats of the first partition and the second partition are different.
6. The method according to claim 1, characterized in that: the reading and running of the test program from the memory to obtain the execution result of at least one test item by the CPU core in the multi-core CPU board includes:
and selecting a test element matched with the tested function module of the multi-core CPU board card from the test program, and testing the tested function module.
7. The method of claim 6,
selecting a test element matched with the tested function module of the multi-core CPU board card from the test program, and testing the tested function module, wherein the test element comprises at least one of the following components:
selecting a communication element from the test program, and testing a functional module which receives a user instruction and performs corresponding operation;
selecting a test program of a sampling element from the test programs, and testing a functional module for detecting the sampling precision of the multi-core CPU board card;
selecting an input/output (IO) element from the test program, and testing a functional module for detecting general input/output (GPIO) hardware and an extended IO pin of the multi-core CPU board card;
selecting a memory test element from the test program, and testing a functional module for detecting the performance of the storage equipment on the multi-core CPU board card;
and selecting an interface element from the test program, and testing the functional module for detecting the plug-in of the multi-core CPU board card and an external interface.
8. The method according to claim 1, characterized in that: the method further comprises the following steps:
and if the test result is unqualified, determining the fault reason.
9. A multicore CPU integrated circuit board debugging device which characterized in that: the device comprises:
the connection module is used for connecting the multi-core CPU board card to be tested with a memory in which a test program and a production program are stored; the production program refers to a program code stored on a storage medium of a multi-core CPU board card after leaving a factory; the test program is used for testing the performance of the multi-core CPU board card; the memory refers to a mobile storage device in a physical form;
the running module is used for reading and running the test program from the memory to acquire an execution result of at least one test item by a CPU core in the multi-core CPU board card;
the determining module is used for determining the test result of the multi-core CPU board card according to the execution result;
and the downloading module is used for reading the multi-core CPU board card from the memory and storing the production program if the test result is qualified.
10. A removable storage medium characterized by: the storage medium stores the following programs:
the test program is used for testing the performance of the multi-core CPU board card;
the production program is a program code stored on a storage medium of a multi-core CPU board card after leaving a factory;
the system program is used for scheduling the test program, receiving the execution result of the test program and downloading the production program to a storage medium of the CPU board card;
the storage medium further stores a program that can execute the CPU board debugging method provided in any one of claims 1 to 8.
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