CN116346084B - High-frequency noise suppression circuit - Google Patents

High-frequency noise suppression circuit Download PDF

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Publication number
CN116346084B
CN116346084B CN202310246271.4A CN202310246271A CN116346084B CN 116346084 B CN116346084 B CN 116346084B CN 202310246271 A CN202310246271 A CN 202310246271A CN 116346084 B CN116346084 B CN 116346084B
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monitoring
tube
nmos tube
signal
pmos tube
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CN116346084A (en
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王青松
李妍
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Yaoxin Microelectronics Technology Shanghai Co ltd
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Yaoxin Microelectronics Technology Shanghai Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/04—Frequency selective two-port networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/26—Time-delay networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

The present application provides a high-frequency noise suppression circuit including: the first monitoring module or the second monitoring module is enabled to carry out time delay operation by monitoring state change of an input signal and duration time of an output signal; the second control module outputs a corresponding second control signal based on the enabling operation of the first monitoring signal or the second monitoring signal; the first control module generates an output signal with the first control signal and the high-frequency noise suppressed by comparing the input signal with the second control signal. By adding delay operation to the high-frequency noise, the operation of suppressing the high-frequency noise is completed on the premise of not influencing the low-frequency signal, and the adverse effect on the whole circuit system is avoided. Simple structure, easy and simple to handle, have extensive suitability.

Description

High-frequency noise suppression circuit
Technical Field
The present application relates to the field of integrated circuit design and application technology, and in particular, to a high frequency noise suppression circuit.
Background
A filter is a circuit that suppresses all unwanted frequency components in an electrical signal. In the existing RC low-pass filter circuit, a resistor and a capacitor are connected in series in a signal path, and a high-frequency signal to be cut off is filtered by utilizing the principle of capacitance absorption by utilizing the principle of capacitance passing high-frequency resistance low frequency. For a low-frequency signal to be passed, the low-frequency signal is passed by utilizing the characteristic that the capacitor has high resistance; at low frequency, the capacitance of the capacitor C is large without shunt effect, and the low frequency signal is directly output through the resistor R. At high frequency, the capacitance of the capacitor C is very small, and the high-frequency signal passing through the resistor R is shunted to the reference ground by the capacitor C without output, so that the low-pass purpose is achieved. However, in practical circuits, RC low pass filter circuits are not very useful because the terms "high frequency" and "low frequency" are very ambiguous; the RC low pass filter circuit always transitions gradually from the pass band to the stop band, meaning that it cannot identify one frequency at which the filter stops passing the signal and begins blocking the signal. Meanwhile, the RC low-pass filter circuit may cause delay to low frequency components and high frequency components in the signal due to the charge and discharge process of the capacitor.
It should be noted that the foregoing description of the background art is only for the purpose of providing a clear and complete description of the technical solution of the present application and is presented for the convenience of understanding by those skilled in the art. The above-described solutions are not considered to be known to the person skilled in the art simply because they are set forth in the background of the application section.
Disclosure of Invention
In view of the above-described drawbacks of the prior art, an object of the present application is to provide a high-frequency noise suppression circuit for solving the problem of how to suppress high-frequency noise by increasing the delay operation of the high-frequency noise without affecting the low-frequency signal in the prior art.
To achieve the above and other related objects, the present application provides a high-frequency noise suppression circuit including at least: the system comprises a first monitoring module, a second monitoring module, a first control module and a second control module, wherein:
the input end of the first monitoring module is connected with the first port, the input end of the second monitoring module is connected with the second port, the first monitoring module or the second monitoring module is enabled to carry out time delay operation by monitoring the state change of an input signal and the duration of an output signal, the first monitoring module outputs a first monitoring signal, the second monitoring module outputs a second monitoring signal, the first port is connected with the input signal, the second port is connected with the output signal, and the first monitoring module comprises: the first monitoring unit, the first capacitance unit and the first adjusting unit, wherein: the input end of the first monitoring unit is connected with the first port; the first end of the first capacitor unit is connected with the output end of the first monitoring unit; the first adjusting unit is connected with the second end of the first capacitance unit, wherein the first monitoring unit comprises: the first PMOS tube, the second PMOS tube, the first NMOS tube and the first NOT gate, wherein: the input end of the first NOT gate is connected with the first port; the source electrode of the first PMOS tube is connected with the working voltage, and the grid electrode of the first PMOS tube is connected with the output end of the first NOT gate; the source electrode of the second PMOS tube is connected with the drain electrode of the first PMOS tube, and the grid electrode of the second PMOS tube is connected with the output end of the first NOT gate; the drain electrode of the first NMOS tube is connected with the drain electrode of the second PMOS tube, the grid electrode of the first NMOS tube is connected with the output end of the first NOT gate, the source electrode of the first NMOS tube is connected with the reference ground, wherein the first capacitor unit comprises a second NMOS tube and a third NMOS tube, and the first capacitor unit comprises: the grid electrode of the second NMOS tube is connected with the output end of the first monitoring unit, and the drain electrode and the source electrode of the second NMOS tube are both connected with the reference ground; the grid electrode of the third NMOS tube is connected with the grid electrode of the second NMOS tube, the drain electrode and the source electrode of the third NMOS tube are both connected with the reference ground, wherein the first regulating unit comprises a third PMOS tube and a fourth NMOS tube, and the first regulating unit comprises the following components: the source electrode of the third PMOS tube is connected with the working voltage, and the grid electrode of the third PMOS tube is connected with the second end of the first capacitance unit; the drain electrode of the fourth NMOS tube is connected with the drain electrode of the third PMOS tube, the grid electrode of the fourth NMOS tube is connected with the grid electrode of the third PMOS tube, the source electrode of the fourth NMOS tube is connected with the reference ground, wherein the second monitoring module comprises: the second monitoring unit, the second capacitance unit and the second regulating unit, wherein: the input end of the second monitoring unit is connected with the second port; the first end of the second capacitor unit is connected with the output end of the second monitoring unit; the second adjusting unit is connected with the second end of the second capacitance unit, wherein the second monitoring unit comprises: fourth PMOS pipe, fifth PMOS pipe and fifth NMOS pipe, wherein: the source electrode of the fourth PMOS tube is connected with the working voltage, and the grid electrode of the fourth PMOS tube is connected with the second port; the source electrode of the fifth PMOS tube is connected with the drain electrode of the fourth PMOS tube, and the grid electrode of the fifth PMOS tube is connected with the second port; the drain electrode of the fifth NMOS tube is connected with the drain electrode of the fifth PMOS tube, the grid electrode of the fifth NMOS tube is connected with the second port, the source electrode of the fifth NMOS tube is connected with the reference ground, wherein the second capacitor unit comprises a sixth NMOS tube and a seventh NMOS tube, and the second capacitor unit comprises: the grid electrode of the sixth NMOS tube is connected with the output end of the second monitoring unit, and the drain electrode and the source electrode of the sixth NMOS tube are both connected with the reference ground; the grid electrode of the seventh NMOS tube is connected with the grid electrode of the sixth NMOS tube, and the drain electrode and the source electrode of the seventh NMOS tube are both connected with the reference ground, wherein the second regulating unit comprises a sixth PMOS tube and an eighth NMOS tube, and the second regulating unit comprises the following components: the source electrode of the sixth PMOS tube is connected with the working voltage, and the grid electrode of the sixth PMOS tube is connected with the second end of the second capacitance unit; the drain electrode of the eighth NMOS tube is connected with the drain electrode of the sixth PMOS tube, the grid electrode of the eighth NMOS tube is connected with the grid electrode of the sixth PMOS tube, and the source electrode of the eighth NMOS tube is connected with the reference ground;
the input end of the second control module is connected with a first control signal, the output end of the first monitoring module and the output end of the second monitoring module, and a corresponding second control signal is output based on enabling operation of the first monitoring signal or the second monitoring signal;
the input end of the first control module is connected with the output end of the second control module and the first port, and the output signal with the first control signal and the high-frequency noise suppressed is generated by comparing the input signal with the second control signal.
Optionally, the first control module includes a first nand gate and a second nand gate, wherein: the input end of the first NAND gate is connected with the output end of the second control module and the first port, wherein the first control signal is generated through the output end of the first NAND gate; the input end of the second NOT gate is connected with the output end of the first NOT gate.
Optionally, the second control module includes a second nand gate, where an input end of the second nand gate is connected to the first control signal, an output end of the first monitoring module, and an output end of the second monitoring module.
As described above, the high-frequency noise suppression circuit of the present application has the following advantageous effects:
1) According to the high-frequency noise suppression circuit, delay operation is added to high-frequency noise, so that the high-frequency noise is suppressed on the premise that low-frequency signals are not affected, and the whole circuit system is not affected.
2) The high-frequency noise suppression circuit is simple in structure, simple and convenient to operate and wide in applicability.
Drawings
Fig. 1 shows a schematic diagram of a high frequency noise suppression circuit of the present application.
Description of the reference numerals
1 high frequency noise suppression circuit
11 first monitoring module
111 first monitoring unit
112 first capacitor unit
113 first adjusting unit
12 second monitoring module
121 second monitoring unit
122 second capacitor unit
123 second adjusting unit
13 first control module
14 second control module
Detailed Description
Other advantages and effects of the present application will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present application with reference to specific examples. The application may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present application.
Please refer to fig. 1. It should be noted that the illustrations provided in the present embodiment merely illustrate the basic concept of the present application by way of illustration, and only the components related to the present application are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
As shown in fig. 1, the present embodiment provides a high-frequency noise suppression circuit 1, the high-frequency noise suppression circuit 1 including: the first monitoring module 11, the second monitoring module 12, the first control module 13 and the second control module 14, wherein:
as shown in fig. 1, the INPUT end of the first monitoring module 11 is connected to the first port INPUT, the INPUT end of the second monitoring module 12 is connected to the second port OUTPUT, the first monitoring module 11 or the second monitoring module 12 is enabled to perform a delay operation by monitoring the state change of the INPUT signal and the duration of the OUTPUT signal, and the first monitoring module 11 OUTPUTs a first monitoring signal DS1 and the second monitoring module 12 OUTPUTs a second monitoring signal DS2, wherein the first port INPUT is connected to the INPUT signal, and the second port OUTPUT is connected to the OUTPUT signal.
Specifically, as an example, as shown in fig. 1, the first monitoring module 11 includes: a first monitoring unit 111, a first capacitance unit 112, and a first adjusting unit 113, wherein: the INPUT end of the first monitoring unit 111 is connected with the first port INPUT; a first end of the first capacitor unit 112 is connected to an output end of the first monitoring unit 111; the first regulating unit 113 is connected to the second terminal of the first capacitive unit 112, wherein the first monitoring signal DS1 is generated via the output terminal of the first regulating unit 113.
More specifically, as shown in fig. 1, the first monitoring unit 111 includes: the first PMOS tube PM1, the second PMOS tube PM2, the first NMOS tube NM1 and the first NOT gate NOT1, wherein: the INPUT end of the first NOT gate NOT1 is connected with the first port INPUT; the source electrode of the first PMOS tube PM1 is connected with the working voltage VDD, and the grid electrode of the first PMOS tube PM1 is connected with the output end of the first NOT 1; the source electrode of the second PMOS tube PM2 is connected with the drain electrode of the first PMOS tube PM1, and the grid electrode of the second PMOS tube PM2 is connected with the output end of the first NOT 1; the drain electrode of the first NMOS tube NM1 is connected with the drain electrode of the second PMOS tube PM2, the grid electrode of the first NMOS tube NM1 is connected with the output end of the first NOT gate NOT1, and the source electrode of the first NMOS tube NM1 is connected with the ground GND. It should be noted that, as an example, the aspect ratio of the first PMOS tube PM1 to the second PMOS tube PM2 is smaller than 1, and the first PMOS tube PM1 and the second PMOS tube PM2 are arranged as inverted ratio tubes, so when the first PMOS tube PM1 and the second PMOS tube PM2 are turned on, the first PMOS tube PM1 and the second PMOS tube PM2 can be equivalent to resistors; when the first PMOS tube PM1 and the second PMOS tube PM2 are turned on, the working voltage VDD charges the first capacitor unit 112, so that the first PMOS tube PM1, the second PMOS tube PM2 and the first capacitor unit 112 form an RC delay circuit, and the first capacitor unit 112 is not formed by a conventional capacitor, but a capacitor is formed by using MOS tubes, which is specifically implemented as follows:
more specifically, as shown in fig. 1, the first capacitor unit 112 includes a second NMOS transistor NM2 and a third NMOS transistor NM3, wherein: the gate of the second NMOS transistor NM2 is connected to the output end of the first monitoring unit 111, that is, the gate of the second NMOS transistor NM2 is connected to the drain of the second PMOS transistor PM2, and the drain and the source of the second NMOS transistor NM2 are both connected to the ground GND; the gate of the third NMOS transistor NM3 is connected with the gate of the second NMOS transistor NM2, and the drain and the source of the third NMOS transistor NM3 are connected with the ground GND.
The main principle of forming the capacitor by the MOS tube is to use gate oxide between the gate and the channel as an insulating medium, the gate as an upper polar plate, and the source, the drain and the substrate are short-circuited together to form a lower polar plate. In this embodiment, the sources, drains and substrates of the second NMOS transistor NM2 and the third NMOS transistor NM3 are connected to the ground GND, when the first PMOS transistor PM1 and the second PMOS transistor PM2 are turned on, a high potential is presented at the node D, an equivalent voltage source is formed on the gates of the second NMOS transistor NM2 and the third NMOS transistor NM3, and when the voltage of the gates exceeds the threshold voltage, an inversion layer, i.e., a channel is formed between the source and the drain (i.e., short for the source and the drain), so that the gate oxide serves as an insulating medium between the gate and the channel, and a capacitor is formed. The MOS capacitor has the main advantages of saving area and being convenient to operate, and the MOS capacitor is essentially a "voltage-controlled capacitor", in this embodiment, because the first PMOS tube PM1 and the second PMOS tube PM2 are arranged in an inverted ratio tube, when the first PMOS tube PM1 and the second PMOS tube PM2 are turned on, the first PMOS tube PM1 and the second PMOS tube PM2 are equivalent to resistors, so that the first PMOS tube PM1, the second PMOS tube PM2, the second NMOS tube NM2 and the third NMOS tube NM3 form an equivalent RC delay circuit network, and further, the RC charge-discharge principle is utilized to perform delay operation on high-frequency noise.
More specifically, as shown in fig. 1, the first adjusting unit 113 includes a third PMOS tube PM3 and a fourth NMOS tube NM4, where: the source electrode of the third PMOS tube PM3 is connected with the working voltage VDD, the grid electrode of the third PMOS tube PM3 is connected with the second end of the first capacitance unit 112, and the grid electrode of the third PMOS tube PM3 is connected with the grid electrode of the third NMOS tube NM 3; the drain electrode of the fourth NMOS tube NM4 is connected to the drain electrode of the third PMOS tube PM3, where the first monitor signal DS1 is output through the drain electrode of the fourth NMOS tube NM4, the gate electrode of the fourth NMOS tube NM4 is connected to the gate electrode of the third PMOS tube PM3, and the source electrode of the fourth NMOS tube NM4 is connected to the ground GND.
It should be noted that, the third PMOS transistor PM3 and the fourth NMOS transistor NM4 form an inverter circuit structure, the potential of the node D and the potential of the first monitor signal DS1 are opposite to each other, when the potential of the node D is a high potential, the MOS capacitor formed by the second NMOS transistor NM2 and the third NMOS transistor NM3 enters a charged state, the potential of the first monitor signal DS1 is pulled down, the second port OUTPUT is in a low level in a previous state, the duration of the low level is short (for example, the duration is less than 1 microsecond), and when the current potential of the first port INPUT is a high level, the low potential of the first monitor signal DS1 can affect the potential of the second port OUTPUT.
Specifically, as an example, as shown in fig. 1, the second monitoring module 12 includes: the second monitoring unit 121, the second capacitance unit 122, and the second adjusting unit 123, wherein: the input end of the second monitoring unit 121 is connected with the second port OUTPUT; the first end of the second capacitor unit 122 is connected with the output end of the second monitoring unit 121; the second regulating unit 123 is connected to a second terminal of the second capacitive unit 122, wherein the second monitoring signal DS2 is generated via an output terminal of the second regulating unit 123.
More specifically, as shown in fig. 1, the second monitoring unit 121 includes: fourth PMOS pipe PM4, fifth PMOS pipe PM5 and fifth NMOS pipe NM5, wherein: the source electrode of the fourth PMOS tube PM4 is connected with the working voltage VDD, and the grid electrode of the fourth PMOS tube PM4 is connected with the second port; the source electrode of the fifth PMOS tube PM5 is connected with the drain electrode of the fourth PMOS tube PM4, and the grid electrode of the fifth PMOS tube PM5 is connected with the second port OUTPUT; the drain electrode of the fifth NMOS tube NM5 is connected with the drain electrode of the second port OUTPUT, the grid electrode of the fifth NMOS tube NM5 is connected with the second port OUTPUT, and the source electrode of the fifth NMOS tube NM5 is connected with the ground GND. It should be noted that, as an example, the aspect ratio of the fourth PMOS transistor PM4 to the fifth PMOS transistor PM5 is smaller than 1, and the fourth PMOS transistor PM4 and the fifth PMOS transistor PM5 are arranged as an inverted ratio transistor, so when the fourth PMOS transistor PM4 and the fifth PMOS transistor PM5 are turned on, the fourth PMOS transistor PM4 and the fifth PMOS transistor PM5 can be equivalent to a resistor; when the fourth PMOS transistor PM4 and the fifth PMOS transistor PM5 are turned on, the working voltage VDD charges the second capacitor unit 122, so that the fourth PMOS transistor PM4, the fifth PMOS transistor PM5 and the second capacitor unit 122 form an RC delay circuit, and the second capacitor unit 122 is not formed by a conventional capacitor, but a capacitor is formed by using a MOS transistor, which is specifically implemented as follows:
more specifically, as shown in fig. 1, the second capacitor unit 122 includes a sixth NMOS transistor NM6 and a seventh NMOS transistor NM7, wherein: the gate of the sixth NMOS transistor NM6 is connected to the output end of the second monitoring unit 121, that is, the gate of the sixth NMOS transistor NM6 is connected to the drain of the fifth PMOS transistor PM5, and the drain and the source of the sixth NMOS transistor NM6 are both connected to the ground GND; the gate of the seventh NMOS transistor NM7 is connected with the gate of the sixth NMOS transistor NM6, and the drain and the source of the seventh NMOS transistor NM7 are connected with the ground GND.
The sixth NMOS transistor NM6 and the seventh NMOS transistor NM7 form a MOS capacitor, wherein gates of the sixth NMOS transistor NM6 and the seventh NMOS transistor NM7 form an upper plate of the MOS capacitor, the sixth NMOS transistor NM6, a source, a drain, and a substrate of the seventh NMOS transistor NM7 are connected together to form a lower plate of the MOS capacitor, the fourth PMOS transistor PM4 and the fifth PMOS transistor PM5 are provided as inverse ratio transistors, and when the fourth PMOS transistor PM4 and the fifth PMOS transistor PM5 are turned on, the fourth PMOS transistor PM4 and the fifth PMOS transistor PM5 are equivalent to resistors, thereby forming an equivalent RC delay circuit network by the fourth PMOS transistor PM4 and the fifth PMOS transistor PM5, the sixth NMOS transistor NM6, and the seventh NMOS transistor NM 7.
Specifically, as shown in fig. 1, when the second port OUTPUT is at a low level in the previous state and the duration of the low level is short (for example, the duration is less than 1 microsecond, it should be noted that the high-frequency noise is usually a spike signal, the duration is short, and the spike signal with a period less than 1 microsecond is usually referred to as high-frequency noise), and the first port INPUT is at a high level, the node D is pulled up to a high level, so as to charge the MOS capacitor formed by the NMOS transistor NM2 and the third NMOS transistor NM3, to increase the delay, then the first adjusting unit 113 makes the first monitoring signal DS1 at a low level, and the first monitoring signal DS1 at a low level determines that the second control module 14 OUTPUTs the high level, and then makes the second port OUTPUT at a high level, which is equivalent to that the "spike" in the high-frequency noise cannot OUTPUT the high level from the first port INPUT to the second port OUTPUT. Due to the delay increase, the OUTPUT of the second port OUTPUT is regulated only by the first monitoring signal DS1, and the delay effect of an equivalent RC delay circuit network is formed by the first PMOS tube PM1, the second PMOS tube PM2, the second NMOS tube NM2 and the third NMOS tube NM3, so that the peak component in high-frequency noise is equivalently restrained.
When the second port OUTPUT is at a low level in the previous state and the duration of the low level is long (for example, the duration exceeds 1 microsecond), and the first port INPUT is at a high level in the current potential, because the node F is pulled up to the high level due to the low level of the second port OUTPUT, the MOS capacitor formed by the sixth NMOS transistor NM6 and the seventh NMOS transistor NM7 is charged first to increase the delay, the second monitoring signal DS2 is made to be at the low level through the second adjusting unit 123, the second monitoring signal DS2 is made to be at the low level, so that the second control module 14 OUTPUTs the high level, and the second port OUTPUT is made to OUTPUT the high level, which is equivalent to that the "spike" in the high frequency noise cannot be outputted from the first port INPUT to the second port OUTPUT. Due to the delay increase, the OUTPUT of the second port OUTPUT is regulated only by the second monitoring signal DS2, and the delay effect of an equivalent RC delay circuit network is formed by the fourth PMOS tube PM4, the fifth PMOS tube PM5, the sixth NMOS tube NM6 and the seventh NMOS tube NM7, so that the peak component in the high-frequency noise is equivalently restrained.
More specifically, as shown in fig. 1, the second adjusting unit 123 includes a sixth PMOS transistor PM6 and an eighth NMOS transistor NM8, where: the source electrode of the sixth PMOS tube PM6 is connected to the working voltage VDD, and the gate electrode of the sixth PMOS tube PM6 is connected to the second end of the second capacitance unit 122, that is, the gate electrode of the sixth PMOS tube PM6 is connected to the gate electrode of the seventh NMOS tube NM 7; the drain electrode of the eighth NMOS transistor NM8 is connected to the drain electrode of the gate electrode of the sixth PMOS transistor PM6, wherein the second monitor signal DS2 is output through the drain electrode of the eighth NMOS transistor NM8, the gate electrode of the eighth NMOS transistor NM8 is connected to the gate electrode of the sixth PMOS transistor PM6, and the source electrode of the eighth NMOS transistor NM8 is connected to the ground GND.
It should be noted that, the sixth PMOS transistor PM6 and the eighth NMOS transistor NM8 form an inverter circuit structure, the potential of the node F and the potential of the second monitor signal DS2 are opposite to each other, when the potential of the node F is a high potential, the potential of the second monitor signal DS2 is pulled down when the MOS capacitor formed by the sixth NMOS transistor NM6 and the seventh NMOS transistor NM7 enters a charged state, the second port OUTPUT is in a low level in a previous state, the duration of the low level is long (for example, the duration exceeds 1 microsecond), and when the current potential of the first port INPUT is in a high level, the low potential of the second monitor signal DS2 can affect the potential of the second port OUTPUT.
It should be further noted that, the first monitoring module 11 and the second monitoring module 12 may also be configured in the forms of a gate control circuit, an application specific integrated circuit (Application Specific Integrated Circuit, abbreviated as ASIC), etc., so long as the state change of the input signal and the duration of the output signal can be monitored, the corresponding delay operation is performed, and the peak component in the high-frequency noise is equivalently suppressed, the configuration of any of the first monitoring module 11 and the second monitoring module 12 is not limited to the embodiment.
As shown in fig. 1, the input end of the second control module 14 is connected to the first control signal CS1, the output end of the first monitoring module 11, and the output end of the second monitoring module 12, and outputs a corresponding second control signal CS2 based on the enabling operation of the first monitoring signal DS1 or the second monitoring signal DS 2; the INPUT end of the first control module 13 is connected to the output end of the second control module 14 and the first port INPUT, and the INPUT signal is compared with the second control signal CS2 to generate the first control signal CS1 and an output signal with suppressed high frequency noise.
Specifically, as an example, as shown in fig. 1, the first control module 13 includes a first NAND gate NAND1 and a second NOT gate NOT2, in which: the INPUT end of the first NAND gate NAND1 is connected with the OUTPUT end of the second control module 14 and the first port INPUT (i.e. the INPUT end of the first NAND gate NAND1 is connected with the OUTPUT end of the second NAND gate NAND2 and the first port INPUT), wherein the first control signal CS1 is generated through the OUTPUT end of the first NAND gate NAND1, the INPUT end of the second NAND gate NOT2 is connected with the OUTPUT end of the first NAND gate NAND1, when the current state of the first port INPUT is at the low level, the first control signal CS1 is at the high level, the first control signal CS1 is NOT affected by the second control signal CS2, the first control signal CS1 is transmitted through the second NAND gate NOT2, and the second port OUTPUT is at the low level; the second control module 14 includes a second NAND gate NAND2, where an input end of the second NAND gate NAND2 is connected to the first control signal CS1, an OUTPUT end of the first monitoring module 11, and an OUTPUT end of the second monitoring module 12, and the second NAND gate NAND2 is enabled by the first monitoring signal DS1 or the second monitoring signal DS2, so that an OUTPUT of the second port OUTPUT is adjusted, and a specific implementation process is not described herein.
It should be noted that, as an example, one period of the signal includes a high level component and a low level component, when the current state of the first port INPUT connected to the INPUT terminal of the first monitoring module 11 is a high level, and the previous state of the second port OUTPUT connected to the OUTPUT terminal of the second monitoring module 12 is a low level, as long as the duration of the high level of the first port INPUT or the low level of the second port OUTPUT reaches a requirement (for example, the duration exceeds 1 microsecond), the second control signal CS2 OUTPUT by the second NAND gate NAND2 in the second control module 14 is a high level, and the second control signal CS2 is transmitted to the second INPUT terminal of the first NAND gate NAND1 in the first control module 13, so that the first control signal CS1 generated by the OUTPUT terminal of the first NAND gate NAND1 releases the previous state of the second port OUTPUT.
It should be further noted that, the first control module 13 and the second control module 14 may be configured in a gate circuit, an application specific integrated circuit (Application Specific Integrated Circuit, abbreviated as ASIC), or the like, so long as the first control module 13 can ultimately generate an output signal with suppressed high frequency noise, the second control module 14 outputs a corresponding second control signal CS2, and any configuration of the first control module 13 and the second control module 14 is not limited to this embodiment.
In summary, a high frequency noise suppression circuit of the present application at least includes: the system comprises a first monitoring module, a second monitoring module, a first control module and a second control module, wherein: the input end of the first monitoring module is connected with the first port, the input end of the second monitoring module is connected with the second port, the first monitoring module or the second monitoring module is enabled to perform time delay operation by monitoring the state change of an input signal and the duration time of an output signal, the first monitoring module outputs a first monitoring signal, the second monitoring module outputs a second monitoring signal, and the first port is connected with the input signal and the second port is connected with the output signal; the input end of the second control module is connected with a first control signal, the output end of the first monitoring module and the output end of the second monitoring module, and a corresponding second control signal is output based on enabling operation of the first monitoring signal or the second monitoring signal; the input end of the first control module is connected with the output end of the second control module and the first port, and the output signal with the first control signal and the high-frequency noise suppressed is generated by comparing the input signal with the second control signal. According to the high-frequency noise suppression circuit, delay operation is added to high-frequency noise, so that the high-frequency noise is suppressed on the premise that low-frequency signals are not affected, and the whole circuit system is not affected. The high-frequency noise suppression circuit is simple in structure, simple and convenient to operate and wide in applicability. Therefore, the application effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present application and its effectiveness, and are not intended to limit the application. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the application. Accordingly, it is intended that all equivalent modifications and variations of the application be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (3)

1. A high-frequency noise suppression circuit, characterized in that the high-frequency noise suppression circuit comprises at least: the system comprises a first monitoring module, a second monitoring module, a first control module and a second control module, wherein:
the input end of the first monitoring module is connected with the first port, the input end of the second monitoring module is connected with the second port, the first monitoring module or the second monitoring module is enabled to carry out time delay operation by monitoring the state change of an input signal and the duration of an output signal, the first monitoring module outputs a first monitoring signal, the second monitoring module outputs a second monitoring signal, the first port is connected with the input signal, the second port is connected with the output signal, and the first monitoring module comprises: the first monitoring unit, the first capacitance unit and the first adjusting unit, wherein: the input end of the first monitoring unit is connected with the first port; the first end of the first capacitor unit is connected with the output end of the first monitoring unit; the first adjusting unit is connected with the second end of the first capacitance unit, wherein the first monitoring unit comprises: the first PMOS tube, the second PMOS tube, the first NMOS tube and the first NOT gate, wherein: the input end of the first NOT gate is connected with the first port; the source electrode of the first PMOS tube is connected with the working voltage, and the grid electrode of the first PMOS tube is connected with the output end of the first NOT gate; the source electrode of the second PMOS tube is connected with the drain electrode of the first PMOS tube, and the grid electrode of the second PMOS tube is connected with the output end of the first NOT gate; the drain electrode of the first NMOS tube is connected with the drain electrode of the second PMOS tube, the grid electrode of the first NMOS tube is connected with the output end of the first NOT gate, the source electrode of the first NMOS tube is connected with the reference ground, wherein the first capacitor unit comprises a second NMOS tube and a third NMOS tube, and the first capacitor unit comprises: the grid electrode of the second NMOS tube is connected with the output end of the first monitoring unit, and the drain electrode and the source electrode of the second NMOS tube are both connected with the reference ground; the grid electrode of the third NMOS tube is connected with the grid electrode of the second NMOS tube, the drain electrode and the source electrode of the third NMOS tube are both connected with the reference ground, wherein the first regulating unit comprises a third PMOS tube and a fourth NMOS tube, and the first regulating unit comprises the following components: the source electrode of the third PMOS tube is connected with the working voltage, and the grid electrode of the third PMOS tube is connected with the second end of the first capacitance unit; the drain electrode of the fourth NMOS tube is connected with the drain electrode of the third PMOS tube, the grid electrode of the fourth NMOS tube is connected with the grid electrode of the third PMOS tube, the source electrode of the fourth NMOS tube is connected with the reference ground, wherein the second monitoring module comprises: the second monitoring unit, the second capacitance unit and the second regulating unit, wherein: the input end of the second monitoring unit is connected with the second port; the first end of the second capacitor unit is connected with the output end of the second monitoring unit; the second adjusting unit is connected with the second end of the second capacitance unit, wherein the second monitoring unit comprises: fourth PMOS pipe, fifth PMOS pipe and fifth NMOS pipe, wherein: the source electrode of the fourth PMOS tube is connected with the working voltage, and the grid electrode of the fourth PMOS tube is connected with the second port; the source electrode of the fifth PMOS tube is connected with the drain electrode of the fourth PMOS tube, and the grid electrode of the fifth PMOS tube is connected with the second port; the drain electrode of the fifth NMOS tube is connected with the drain electrode of the fifth PMOS tube, the grid electrode of the fifth NMOS tube is connected with the second port, the source electrode of the fifth NMOS tube is connected with the reference ground, wherein the second capacitor unit comprises a sixth NMOS tube and a seventh NMOS tube, and the second capacitor unit comprises: the grid electrode of the sixth NMOS tube is connected with the output end of the second monitoring unit, and the drain electrode and the source electrode of the sixth NMOS tube are both connected with the reference ground; the grid electrode of the seventh NMOS tube is connected with the grid electrode of the sixth NMOS tube, and the drain electrode and the source electrode of the seventh NMOS tube are both connected with the reference ground, wherein the second regulating unit comprises a sixth PMOS tube and an eighth NMOS tube, and the second regulating unit comprises the following components: the source electrode of the sixth PMOS tube is connected with the working voltage, and the grid electrode of the sixth PMOS tube is connected with the second end of the second capacitance unit; the drain electrode of the eighth NMOS tube is connected with the drain electrode of the sixth PMOS tube, the grid electrode of the eighth NMOS tube is connected with the grid electrode of the sixth PMOS tube, and the source electrode of the eighth NMOS tube is connected with the reference ground;
the input end of the second control module is connected with a first control signal, the output end of the first monitoring module and the output end of the second monitoring module, and a corresponding second control signal is output based on enabling operation of the first monitoring signal or the second monitoring signal;
the input end of the first control module is connected with the output end of the second control module and the first port, and the output signal with the first control signal and the high-frequency noise suppressed is generated by comparing the input signal with the second control signal.
2. The high frequency noise suppression circuit according to claim 1, wherein: the first control module comprises a first NAND gate and a second NAND gate, wherein: the input end of the first NAND gate is connected with the output end of the second control module and the first port, wherein the first control signal is generated through the output end of the first NAND gate; the input end of the second NOT gate is connected with the output end of the first NOT gate.
3. The high frequency noise suppression circuit according to claim 1, wherein: the second control module comprises a second NAND gate, wherein the input end of the second NAND gate is connected with the first control signal, the output end of the first monitoring module and the output end of the second monitoring module.
CN202310246271.4A 2023-03-14 2023-03-14 High-frequency noise suppression circuit Active CN116346084B (en)

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CN108563254A (en) * 2018-03-21 2018-09-21 中国人民解放军海军工程大学 A kind of active control system for multifrequency time-varying narrow band vibration noise
CN110048711A (en) * 2019-05-15 2019-07-23 苏州锴威特半导体有限公司 A kind of digital signal processing circuit for resisting ground and power bounce noise
CN111124032A (en) * 2019-12-20 2020-05-08 睿兴科技(南京)有限公司 Filter circuit for suppressing noise interference and micro control system
CN115483912A (en) * 2022-10-08 2022-12-16 聆思半导体技术(苏州)有限公司 Noise suppression delay circuit

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5614858A (en) * 1993-01-29 1997-03-25 Sgs-Thomson Microelectronics S.R.L. Time delayed filter monolithically integratable
KR20020010994A (en) * 2000-07-31 2002-02-07 박종섭 Noise cancel circuit in using the same pahse
CN105827237A (en) * 2015-01-06 2016-08-03 中芯国际集成电路制造(上海)有限公司 Time delay circuit and voltage-controlled oscillator
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CN110048711A (en) * 2019-05-15 2019-07-23 苏州锴威特半导体有限公司 A kind of digital signal processing circuit for resisting ground and power bounce noise
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CN115483912A (en) * 2022-10-08 2022-12-16 聆思半导体技术(苏州)有限公司 Noise suppression delay circuit

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