CN115483912A - Noise suppression delay circuit - Google Patents
Noise suppression delay circuit Download PDFInfo
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- CN115483912A CN115483912A CN202211221944.2A CN202211221944A CN115483912A CN 115483912 A CN115483912 A CN 115483912A CN 202211221944 A CN202211221944 A CN 202211221944A CN 115483912 A CN115483912 A CN 115483912A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/0015—Layout of the delay element
- H03K2005/00195—Layout of the delay element using FET's
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- Nonlinear Science (AREA)
- Manipulation Of Pulses (AREA)
Abstract
The invention relates to a delay circuit, in particular to a noise suppression delay circuit, which comprises an RC (resistor-capacitor) charging and discharging circuit, a quick charging and discharging circuit and a logic control circuit, wherein the logic control circuit outputs a control signal to the quick charging and discharging circuit based on an output signal of the RC charging and discharging circuit, and the quick charging and discharging circuit constructs a quick charging and discharging path for the RC charging and discharging circuit according to the control signal; the technical scheme provided by the invention can effectively overcome the defect of larger error of an output signal caused by RC charge accumulation effect due to lack of a rapid charge-discharge path in the prior art.
Description
Technical Field
The present invention relates to a delay circuit, and more particularly, to a noise suppression delay circuit.
Background
In the conventional delay circuit (as shown in fig. 3), the circuit does not provide a delay late fast charge-discharge path for the RC charge-discharge module, and the previous RC charge generated by the input delay is accumulated to the next input, so that a large deviation occurs in the delay value (as shown in fig. 4).
Furthermore, when the input signal width T1 is smaller than the set delay value T0 and the input signal is a periodic signal, the output signal may have a level change (as shown in fig. 5) which should not occur after several input periods due to the accumulation effect of the RC charges.
Disclosure of Invention
Technical problem to be solved
Aiming at the defects in the prior art, the invention provides a noise suppression delay circuit which can effectively overcome the defect that the output signal error is larger due to the RC charge accumulation effect caused by the lack of a rapid charge-discharge path in the prior art.
(II) technical scheme
In order to achieve the purpose, the invention is realized by the following technical scheme:
a noise suppression delay circuit comprises an RC (resistor-capacitor) charging and discharging circuit, a rapid charging and discharging circuit and a logic control circuit, wherein the logic control circuit outputs a control signal to the rapid charging and discharging circuit based on an output signal of the RC charging and discharging circuit, and the rapid charging and discharging circuit constructs a rapid charging and discharging path for the RC charging and discharging circuit according to the control signal.
Preferably, the rapid charging and discharging circuit comprises a P-type field effect transistor P2 and an N-type field effect transistor N2, a drain electrode of the P-type field effect transistor P2 is connected with a drain electrode of the N-type field effect transistor N2, a capacitor C5 is connected between the drain electrodes of the P-type field effect transistor P2 and the N-type field effect transistor N2, and gates of the P-type field effect transistor P2 and the N-type field effect transistor N2 are connected to the logic control circuit.
Preferably, the logic control circuit comprises an exclusive nor chip U3, an nand chip U1 and an and chip U2, wherein the input end of the exclusive nor chip U3 is respectively connected to the capacitor C5 and the input signal, and the output end of the exclusive nor chip U3 is respectively connected to the input ends of the nand chip U1 and the and chip U2;
the input end of the NAND gate chip U1 is connected with a capacitor C5, and the output end of the NAND gate chip U1 is connected with the grid of a P-type field effect transistor P2;
the input end of the AND gate chip U2 is connected with the capacitor C5 through a NOT gate, and the output end of the AND gate chip U2 is connected with the grid electrode of the N-type field effect transistor N2.
Preferably, the logic control circuit further comprises a D-type flip-flop U4, an input end of the D-type flip-flop U4 is connected to an output end of the exclusive nor chip U3, and an output end of the D-type flip-flop U4 is connected to input ends of the nand chip U1 and the and chip U2, respectively.
Preferably, the RC charging and discharging circuit includes a P-type field effect transistor P1 and an N-type field effect transistor N1, a drain of the P-type field effect transistor P1 is connected to a drain of the N-type field effect transistor N1 through resistors R1 and R2, gates of the P-type field effect transistor P1 and the N-type field effect transistor N1 are connected to an input signal, and a capacitor C5 is connected between the resistors R1 and R2.
(III) advantageous effects
Compared with the prior art, the noise suppression delay circuit provided by the invention has the following beneficial effects:
1) The auxiliary field effect transistor is adopted to accelerate the charging and discharging of the RC charging and discharging circuit after the delay, so that the RC charge accumulation effect in the circuit is prevented, and the output delay is accurate;
2) Carrying out delay output on the input signal with a larger set delay value; the input signal with a smaller set delay value is not reacted; for input signals with approximate set delay values, false burrs and peak waveforms are not generated, and the false waveforms are prevented from triggering subsequent circuits by mistake;
3) And a clock circuit is not used, so that the output signal glitch phenomenon is effectively solved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
FIG. 1 is a circuit diagram of the present invention;
FIG. 2 is a schematic diagram of the burr suppression of the present invention;
FIG. 3 is a circuit diagram of a conventional delay circuit;
FIG. 4 is a diagram illustrating a large deviation of delay values due to RC charge accumulation effect in a conventional delay circuit;
fig. 5 is a diagram illustrating a level error variation caused by the RC charge accumulation effect in a conventional delay circuit.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive step based on the embodiments of the present invention, are within the scope of protection of the present invention.
A noise suppression delay circuit is shown in figure 1 and comprises an RC (resistor-capacitor) charging and discharging circuit, a rapid charging and discharging circuit and a logic control circuit, wherein the logic control circuit outputs a control signal to the rapid charging and discharging circuit based on an output signal of the RC charging and discharging circuit, and the rapid charging and discharging circuit constructs a rapid charging and discharging path for the RC charging and discharging circuit according to the control signal.
(1) The RC charge-discharge circuit comprises a P-type field effect transistor P1 and an N-type field effect transistor N1, wherein the drain electrode of the P-type field effect transistor P1 is connected with the drain electrode of the N-type field effect transistor N1 through resistors R1 and R2, the grid electrodes of the P-type field effect transistor P1 and the N-type field effect transistor N1 are connected with an input signal, and a capacitor C5 is connected between the resistors R1 and R2.
(2) The rapid charging and discharging circuit comprises a P-type field effect transistor P2 and an N-type field effect transistor N2, wherein the drain electrode of the P-type field effect transistor P2 is connected with the drain electrode of the N-type field effect transistor N2, a capacitor C5 is connected between the drain electrodes of the P-type field effect transistor P2 and the N-type field effect transistor N2, and the grid electrodes of the P-type field effect transistor P2 and the N-type field effect transistor N2 are connected with a logic control circuit.
(3) The logic control circuit comprises an exclusive-nor gate chip U3, a NAND gate chip U1 and an AND gate chip U2, wherein the input end of the exclusive-nor gate chip U3 is respectively connected with a capacitor C5 and an input signal, and the output end of the exclusive-nor gate chip U3 is respectively connected with the input ends of the NAND gate chip U1 and the AND gate chip U2;
the input end of the NAND gate chip U1 is connected with the capacitor C5, and the output end of the NAND gate chip U1 is connected with the grid electrode of the P-type field effect transistor P2;
the input end of the AND gate chip U2 is connected with the capacitor C5 through a NOT gate, and the output end of the AND gate chip U2 is connected with the grid electrode of the N-type field effect transistor N2.
(4) The logic control circuit further comprises a D-type trigger U4, the input end of the D-type trigger U4 is connected to the output end of the XNOR gate chip U3, and the output end of the D-type trigger U4 is respectively connected with the input ends of the NAND gate chip U1 and the AND gate chip U2.
In the technical scheme of the application, after the delay reaches the set delay value T0, a strong pull control signal is given to the capacitor C5 of the RC charge-discharge circuit to control the strong pull driving MOS (P-type field effect transistor P2 and N-type field effect transistor N2) so as to accelerate the delayed later-stage charge-discharge of the capacitor C5.
The input signal jumps from low level to high level, and when the output signal is low level, the N-type field effect transistor N2 is opened to accelerate the discharge of the capacitor C5; when the input signal jumps from high level to low level and the output signal is high level, the P-type field effect transistor P2 is turned on to accelerate the charging of the capacitor C5.
Because the detection circuit has reaction time, when the input signal width T1 is shortened and is close to the set delay value T0, the output signal is sent out, the strong pull driving MOS (P-type field effect transistor P2 and N-type field effect transistor N2) is started, but the input signal changes the original state, the strong pull driving MOS and the strong pull driving MOS compete with the P-type field effect transistor P1 and the N-type field effect transistor N1, and the signal formed at the output end of the NOR gate chip U3 has uncertainty. When the input drive is enhanced, a 'burr phenomenon' (as shown in fig. 2) is generated, and a D-type trigger U4 is added, so that burrs on a signal output path can be effectively isolated, and clear signals are provided for the forced pull drive MOS (P-type field effect transistor P2 and N-type field effect transistor N2).
The above examples are only intended to illustrate the technical solution of the present invention, and not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (5)
1. A noise suppression delay circuit, characterized by: the fast charging and discharging circuit comprises an RC charging and discharging circuit, a fast charging and discharging circuit and a logic control circuit, wherein the logic control circuit outputs a control signal to the fast charging and discharging circuit based on an output signal of the RC charging and discharging circuit, and the fast charging and discharging circuit constructs a fast charging and discharging path for the RC charging and discharging circuit according to the control signal.
2. The noise-suppressing delay circuit of claim 1, wherein: the rapid charging and discharging circuit comprises a P-type field effect tube P2 and an N-type field effect tube N2, wherein the drain electrode of the P-type field effect tube P2 is connected with the drain electrode of the N-type field effect tube N2, a capacitor C5 is connected between the drain electrodes of the P-type field effect tube P2 and the N-type field effect tube N2, and the grid electrodes of the P-type field effect tube P2 and the N-type field effect tube N2 are connected into a logic control circuit.
3. The noise-suppressing delay circuit of claim 2, wherein: the logic control circuit comprises an exclusive-nor gate chip U3, a NAND gate chip U1 and an AND gate chip U2, wherein the input end of the exclusive-nor gate chip U3 is respectively connected with a capacitor C5 and an input signal, and the output end of the exclusive-nor gate chip U3 is respectively connected with the input ends of the NAND gate chip U1 and the AND gate chip U2;
the input end of the NAND gate chip U1 is connected with a capacitor C5, and the output end of the NAND gate chip U1 is connected with the grid electrode of a P-type field effect transistor P2;
the input end of the AND gate chip U2 is connected with the capacitor C5 through a NOT gate, and the output end of the AND gate chip U2 is connected with the grid electrode of the N-type field effect transistor N2.
4. The noise-suppressing delay circuit of claim 3, wherein: the logic control circuit further comprises a D-type trigger U4, the input end of the D-type trigger U4 is connected to the output end of the XNOR gate chip U3, and the output end of the D-type trigger U4 is respectively connected with the input ends of the NAND gate chip U1 and the AND gate chip U2.
5. The noise-suppressing delay circuit of any one of claims 1-4, wherein: the RC charge-discharge circuit comprises a P-type field effect transistor P1 and an N-type field effect transistor N1, wherein the drain electrode of the P-type field effect transistor P1 is connected with the drain electrode of the N-type field effect transistor N1 through resistors R1 and R2, the grid electrodes of the P-type field effect transistor P1 and the N-type field effect transistor N1 are connected with an input signal, and a capacitor C5 is connected between the resistors R1 and R2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211221944.2A CN115483912A (en) | 2022-10-08 | 2022-10-08 | Noise suppression delay circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211221944.2A CN115483912A (en) | 2022-10-08 | 2022-10-08 | Noise suppression delay circuit |
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| Publication Number | Publication Date |
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| CN115483912A true CN115483912A (en) | 2022-12-16 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202211221944.2A Pending CN115483912A (en) | 2022-10-08 | 2022-10-08 | Noise suppression delay circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116346084A (en) * | 2023-03-14 | 2023-06-27 | 瑶芯微电子科技(上海)有限公司 | High-frequency noise suppression circuit |
| CN116647215A (en) * | 2023-05-18 | 2023-08-25 | 成都电科星拓科技有限公司 | Burr eliminating method and circuit in switching process of differential clock driving circuit |
-
2022
- 2022-10-08 CN CN202211221944.2A patent/CN115483912A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116346084A (en) * | 2023-03-14 | 2023-06-27 | 瑶芯微电子科技(上海)有限公司 | High-frequency noise suppression circuit |
| CN116346084B (en) * | 2023-03-14 | 2023-10-20 | 瑶芯微电子科技(上海)有限公司 | High-frequency noise suppression circuit |
| CN116647215A (en) * | 2023-05-18 | 2023-08-25 | 成都电科星拓科技有限公司 | Burr eliminating method and circuit in switching process of differential clock driving circuit |
| CN116647215B (en) * | 2023-05-18 | 2024-01-26 | 成都电科星拓科技有限公司 | Burr eliminating method and circuit in switching process of differential clock driving circuit |
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