CN105827237A - Time delay circuit and voltage-controlled oscillator - Google Patents
Time delay circuit and voltage-controlled oscillator Download PDFInfo
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- CN105827237A CN105827237A CN201510006052.4A CN201510006052A CN105827237A CN 105827237 A CN105827237 A CN 105827237A CN 201510006052 A CN201510006052 A CN 201510006052A CN 105827237 A CN105827237 A CN 105827237A
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Abstract
The invention relates to a time delay circuit and a voltage-controlled oscillator. The time delay circuit comprises an amplifying unit, a regulating unit and a load unit, wherein the amplifying unit is coupled to an input end and an output end of the time delay circuit, the regulating unit is coupled to the output end of the time delay circuit, power supply voltage and control voltage respectively, and the load unit is coupled to the output end of the time delay circuit and the power supply voltage; the regulating unit is suitable for regulating charging and discharging current of the time delay circuit; the amplifying unit is suitable for amplifying output voltage of the time delay circuit; and the load unit is suitable for providing negative impedance for the regulating unit. Through the time delay circuit and the voltage-controlled oscillator, phase noises of the time delay circuit can be reduced, and low voltage gain is realized.
Description
Technical field
The present invention relates to electronic circuit technology field, particularly relate to a kind of delay circuit and voltage controlled oscillator.
Background technology
Phaselocked loop (Phase-LockedLoop, PLL) is the core circuit in various types of communication, clock chip, and the pectrum noise of its output signal, shake, the index such as spuious can be directly connected to systematic function.Voltage controlled oscillator is the important component part in PLL.When controlling voltage and changing within the specific limits, the signal output in the range of cline frequency can be obtained.Ring oscillator is the main implementation of one of which, and by being joined end to end by delay circuit, formation feedback control loop produces oscillatory voltage signals.Ring oscillator includes single-ended and two kinds of circuit structures of difference.
Input is controlled voltage by the delay circuit of existing ring oscillator design and is converted to the regulation cell mesh of electric current, it is difficult to when covering required frequency range, it is achieved less phase noise.
Summary of the invention
The problem that the embodiment of the present invention solves is how to reduce the phase noise of delay circuit.
For solving the problems referred to above, the embodiment of the present invention provides a kind of delay circuit, including: amplifying unit, regulation unit and load unit；Described amplifying unit is coupled to input and the outfan of described delay circuit, described regulation unit is respectively coupled to the outfan of described delay circuit, supply voltage and controls voltage, and described load unit is respectively coupled to outfan and the supply voltage of described delay circuit；Regulation unit, is suitable to regulate the charging and discharging currents of described delay circuit；Amplifying unit, is suitable to amplify the output voltage of described delay circuit；Load unit, is suitable for described regulation unit and provides negative impedance.
Optionally, described regulation unit includes: the first regulon unit and the second regulon unit；Described first regulon unit is coupled to the first outfan of described control voltage, supply voltage and described delay circuit；Described second regulon unit is coupled to the second outfan of described control voltage, supply voltage and described delay circuit.
Optionally, described first regulon unit includes: the first transistor and transistor seconds；The control end of described the first transistor is coupled to described control voltage, and input is coupled to supply voltage, and outfan is coupled to the first outfan of described delay circuit；The control end of described transistor seconds is coupled to described control voltage, and input is coupled to the first outfan of described delay circuit, output head grounding.
Optionally, described second regulon unit includes: third transistor and the 4th transistor；The control end of described third transistor is coupled to described control voltage, and input is coupled to supply voltage, and outfan is coupled to the second outfan of described delay circuit；The control end of described 4th transistor is coupled to described control voltage, and input is coupled to the second outfan of described delay circuit, output head grounding.
Optionally, described load unit includes: the 5th transistor and the 6th transistor；The end that controls of described 5th transistor is coupled to the second outfan of described delay circuit, and input is coupled to supply voltage, and outfan is coupled to the first outfan of described delay circuit；The end that controls of described 6th transistor is coupled to the first outfan of described delay circuit, and input is coupled to supply voltage, and outfan is coupled to the second outfan of described delay circuit.
Optionally, described load unit also includes: the 7th transistor and the 8th transistor；The end that controls of described 7th transistor is coupled to the second outfan of described delay circuit, and input end grounding, outfan is coupled to the first outfan of described delay circuit；The end that controls of described 8th transistor is coupled to the first outfan of described delay circuit, and input end grounding, outfan is coupled to the second outfan of described delay circuit.
Optionally, described amplifying unit includes: the 9th transistor；The end that controls of described 9th transistor is coupled to the first input end of described delay circuit, and input end grounding, outfan is coupled to the first outfan of described delay circuit.
Optionally, described amplifying unit also includes: the tenth transistor；The end that controls of described tenth transistor is coupled to the second input of described delay circuit, and input end grounding, outfan is coupled to the second outfan of described delay circuit.
In order to solve above-mentioned technical problem, the embodiment of the invention also discloses a kind of voltage controlled oscillator, including above-mentioned delay circuit；Described at least two delay circuit joins end to end into positive feedback.
Compared with prior art, the technical scheme of the embodiment of the present invention has the advantage that
The regulation unit being described delay circuit by load unit provides negative impedance, enhance the described delay circuit equiva lent impedance at outfan, thus enhance the gain when the intermediateness that output voltage overturns of the described delay circuit, the upset point slope making described delay circuit is precipitous, achieve quickly upset, therefore can produce relatively low phase noise.
Further, by being regulated the discharge and recharge time of described delay circuit by two transistors in regulon unit, it is achieved that low voltage controlled gain.
Accompanying drawing explanation
Fig. 1 is existing a kind of delay circuit structural representation；
Fig. 2 is the structural representation of a kind of delay circuit of the embodiment of the present invention；
Fig. 3 is the electrical block diagram of a kind of delay circuit with differential configuration of the embodiment of the present invention；
Fig. 4 is the structural representation of a kind of voltage controlled oscillator of the embodiment of the present invention.
Detailed description of the invention
Fig. 1 show a kind of delay circuit structure.It regulates the RC constant of output node ON and OP by VVC voltage variable capacitance, to realize Variable delay, and reduces delay circuit to temperature and the sensitivity of supply voltage by the resistive device being connected on phase inverter 810 and phase inverter 820 drain electrode.But the introducing of this resistive device can cause the deterioration of oscillator phase.Input is controlled voltage by this delay circuit and is converted to the regulation cell mesh of electric current, it is difficult to when covering required frequency range, it is achieved less phase noise.
Fig. 2 shows the structural representation of a kind of delay circuit in the embodiment of the present invention.As in figure 2 it is shown, described delay circuit may include that amplifying unit 101, regulation unit 102 and load unit 103.Described amplifying unit 101 is coupled to the input IN and outfan OUT of described delay circuit, described regulation unit 102 is respectively coupled to the outfan OUT of described delay circuit, supply voltage Vdd and controls voltage Vc, and described load unit 103 is respectively coupled to the outfan OUT and supply voltage Vdd of described delay circuit.
Amplifying unit 101, is suitable to amplify the output voltage of described delay circuit.
Regulation unit 102, is suitable to regulate the charging and discharging currents of described delay circuit, and then correspondingly realizes regulating the RC charge constant of described delay circuit.
Load unit 103, is suitable for described regulation unit 102 and provides negative impedance.The regulation unit being described delay circuit by described load unit 103 provides negative impedance, the described delay circuit equiva lent impedance at outfan OUT can be strengthened, thus strengthen the gain when the intermediateness that output voltage overturns of the described delay circuit, the upset point slope making described delay circuit is precipitous, achieve quickly upset, therefore can produce relatively low phase noise.
In being embodied as, described delay circuit can apply in the voltage controlled oscillator of PLL.Ring oscillator is a kind of main implementation of voltage controlled oscillator, including single-ended and two kinds of circuit structures of difference.Owing to differential configuration has preferable noise resisting ability, therefore the described delay circuit of the embodiment of the present invention can use differential configuration, to be preferably applied in high-speed pll.
Fig. 3 shows the structural representation of a kind of delay circuit with differential configuration in the embodiment of the present invention.As it is shown on figure 3, described delay circuit can include regulating unit, load unit 303 and amplifying unit 304.The regulation unit of described delay circuit can include the first regulon unit 301 and the second regulon unit 302, and described first regulon unit 301 is coupled to control voltage Vc, supply voltage Vdd and the first outfan OUTn of described delay circuit；Described second regulon unit 302 is coupled to control voltage Vc, supply voltage Vdd and the second outfan OUTp of described delay circuit.
The input voltage of the first input end INp of described delay circuit and the output voltage of the first outfan OUTn are the relation that difference is anti-phase.Accordingly, the input voltage of the second input INn of described delay circuit and the output voltage of the second outfan OUTp are also the relation that difference is anti-phase.
In being embodied as, described first regulon unit 301 may include that the first transistor M1 and transistor seconds M2.The control end of described the first transistor M1 is coupled to control voltage Vc, and input is coupled to supply voltage Vdd, and outfan is coupled to the first outfan OUTn of described delay circuit.The control end of described transistor seconds M2 is coupled to control voltage Vc, and input is coupled to the first outfan OUTn of described delay circuit, output head grounding.
In above-mentioned being embodied as, described the first transistor M1 can be PMOS, and described transistor seconds M2 can be NMOS tube.
In being embodied as, corresponding with described first regulon unit 301, described second regulon unit 302 may include that third transistor M3 and the 4th transistor M4；The control end of described third transistor M3 is coupled to control voltage Vc, and input is coupled to supply voltage Vdd, and outfan is coupled to the second outfan OUTp of described delay circuit；The control end of described 4th transistor M4 is coupled to control voltage Vc, and input is coupled to the second outfan OUTp of described delay circuit, output head grounding.
In above-mentioned being embodied as, described third transistor M3 can be PMOS, and described 4th transistor M4 can be NMOS tube.
Described control voltage Vc is a continuously varying analog signal, can be controlled the delay time of described delay circuit, i.e. discharge and recharge time constant RC by described first regulon unit 301 and described second regulon unit 302.Change along with described control voltage Vc magnitude of voltage, described the first transistor M1, transistor seconds M2, third transistor M3 and the mutual conductance Gm of the 4th transistor M4, output impedance Ro will change, thus regulate the first outfan OUTn and the discharge and recharge time constant of the second outfan OUTp of described delay circuit.
In being embodied as, the load unit 303 of described delay circuit may include that the 5th transistor M5 and the 6th transistor M6；The end that controls of described 5th transistor M5 is coupled to the second outfan OUTp of described delay circuit, and input is coupled to supply voltage Vdd, and outfan is coupled to the first outfan OUTn of described delay circuit；The end that controls of described 6th transistor M6 is coupled to the first outfan OUTn of described delay circuit, and input is coupled to supply voltage Vdd, and outfan is coupled to the second outfan OUTp of described delay circuit.Described 5th transistor M5 and described 6th transistor M6 cross-couplings, be functionally equivalent to a negative resistance, as the load of described delay circuit amplifying unit 304, together decides on and adjust the reversal rate of described delay circuit.
In above-mentioned being embodied as, described 5th transistor M5 and shown 6th transistor M6 can be PMOS.
In being embodied as, described load unit 303 can also include: the 7th transistor M7 and the 8th transistor M8.The end that controls of described 7th transistor M7 is coupled to the second outfan OUTp of described delay circuit, and input end grounding, outfan is coupled to the first outfan OUTn of described delay circuit；The end that controls of described 8th transistor M8 is coupled to the first outfan OUTn of described delay circuit, and input end grounding, outfan is coupled to the second outfan OUTp of described delay circuit.Described 7th transistor M7 and described 8th transistor M8 constitutes negative resistance to pipe, can play the high frequency reversal rate strengthening time-delay unit circuit, improve the effect of agitator starting of oscillation ability.
In above-mentioned being embodied as, described 7th transistor M7 can be NMOS tube, and described 8th transistor M8 can be NMOS tube, forms NMOS negative resistance to pipe.
In being embodied as, described amplifying unit 304 may include that the 9th transistor M9；The end that controls of described 9th transistor M9 is coupled to the first input end INp of described delay circuit, and input end grounding, outfan is coupled to the first outfan OUTn of described delay circuit.
In being embodied as, accordingly, described amplifying unit 304 can also include: the tenth transistor M10；The end that controls of described tenth transistor M10 is coupled to the second input INn of described delay circuit, and input end grounding, outfan is coupled to the second outfan OUTp of described delay circuit.
Described 9th transistor M9 and described tenth transistor M10 to pipe, amplifies the output voltage of described delay circuit as input mutual conductance.In being embodied as, described 9th transistor M9 can be NMOS tube, and described tenth transistor M10 can be NMOS tube.
Hereafter by two states residing for described delay circuit the low phase noise achieved by described delay circuit and low voltage-controlled gain effect it is described:
(1) when the input voltage of first input end INp, the input voltage of the second input INnInn, the output voltage of the first outfan OUTn and the output voltage approximately equal of the second outfan OUTp of described delay circuit, and during all close to VDD/2, the most described delay circuit is in the upset critical state of output voltage, and all of transistor is all in saturation region.As a example by the left half of circuit including the first transistor M1, transistor seconds M2, the 5th transistor M5, the 6th transistor M6, the 7th transistor M7M7, the 8th transistor M8M8, the 9th transistor M9, circuit small-signal gain is Gm9*Zoutn.Wherein, Gm9 is the mutual conductance of the 9th transistor M9, and Zoutn is the equiva lent impedance of described delay circuit the first outfan OUTn outfan.Because now the first transistor M1 and transistor seconds M2 is all in saturation region, therefore there is higher resistance.Simultaneously because two groups of negative resistances are to pipe the 5th transistor M5 and the 6th transistor M6,7th transistor M7M7 and the 8th transistor M8M8 introduces negative impedance, thus further enhancing equiva lent impedance Zoutn of the first outfan OUTn of described delay circuit, so that described delay circuit has the strongest gain in the intermediateness of upset, this quick switching process, precipitous upset point slope bring relatively low phase noise accordingly.
(2) as the high level VDD that the input voltage of the first input end INp of described delay circuit is approximation supply voltage Vdd, the output voltage of the first outfan OUTn is approximation low level GND, when the left-half of the most above-mentioned delay circuit is in charged state, the first transistor M1 turns on, and makes described supply voltage Vdd be charged to the first outfan OUTn of described delay circuit by M1.The current formula of MOSFET saturation region is:
Wherein U is the migration rate of transistor carrier, and Cox is transistor unit area gate oxide capacitance, and W/L is transistor breadth length ratio, and Vgs-Vth is overdrive voltage.The most now breadth length ratio W/L of the first transistor M1 determines the size of charging current, namely charge constant.In like manner, discharge time constant is determined by transistor seconds M2 pipe.Described charging and discharging time constant has together decided on the frequency of oscillation of agitator.
The most to sum up, the size of described delay circuit charging current can be controlled by arranging the wide W and long L of described the first transistor M1 and described transistor seconds M2, obtain less voltage controlled gain.Additionally, in the delay circuit of existing ring oscillator, control voltage Vc and only control a transistor, such as the grid of NMOS or PMOS.The control voltage Vc of the embodiment of the present invention controls the first transistor M1 and transistor seconds M2 simultaneously, therefore can regulate the W/L parameter of M1 Yu M2 in proportion to realize described control voltage Vc in big voltage range, as good linear in all having in 0～VDD.
In being embodied as, described the first transistor M1 and described transistor seconds M2 width W and long L parameter can be arranged and type selecting according to the analog result of circuit simulation, make described delay circuit have low voltage controlled gain and the good linearity.
The type of above-mentioned transistor is not limited to the type shown by the present embodiment, and it can need change, as long as being capable of same control logic according to what reality was applied.It is understood that the transistor types shown in the present embodiment or other change belong to protection scope of the present invention.
The embodiment of the invention also discloses a kind of voltage controlled oscillator.Described voltage controlled oscillator includes the delay circuit that at least two is above-mentioned.Described at least two delay circuit joins end to end into positive feedback.As shown in Figure 4, for the voltage controlled oscillator being made up of two delay circuits 401 and 402.
In being embodied as, corresponding setting can be done in described voltage controlled oscillator according to the needs of application.Such as require the output waveform of described voltage controlled oscillator be dutycycle close to 50% square wave time, corresponding Shape correction can be carried out by arranging one-level phase inverter.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (9)
1. a delay circuit, it is characterised in that including: amplifying unit, regulation unit and load unit；
Described amplifying unit is coupled to input and the outfan of described delay circuit, described regulation unit is respectively coupled to the outfan of described delay circuit, supply voltage and controls voltage, and described load unit is respectively coupled to outfan and the supply voltage of described delay circuit；
Regulation unit, is suitable to regulate the charging and discharging currents of described delay circuit；
Amplifying unit, is suitable to amplify the output voltage of described delay circuit；
Load unit, is suitable for described regulation unit and provides negative impedance.
2. delay circuit as claimed in claim 1, it is characterised in that described regulation unit includes: the first regulon unit and the second regulon unit；Described first regulon unit is coupled to the first outfan of described control voltage, supply voltage and described delay circuit；Described second regulon unit is coupled to the second outfan of described control voltage, supply voltage and described delay circuit.
3. delay circuit as claimed in claim 2, it is characterised in that described first regulon unit includes: the first transistor and transistor seconds；
The control end of described the first transistor is coupled to described control voltage, and input is coupled to supply voltage, and outfan is coupled to the first outfan of described delay circuit；
The control end of described transistor seconds is coupled to described control voltage, and input is coupled to the first outfan of described delay circuit, output head grounding.
4. delay circuit as claimed in claim 2, it is characterised in that described second regulon unit includes:
Third transistor and the 4th transistor；
The control end of described third transistor is coupled to described control voltage, and input is coupled to supply voltage, and outfan is coupled to the second outfan of described delay circuit；
The control end of described 4th transistor is coupled to described control voltage, and input is coupled to the second outfan of described delay circuit, output head grounding.
5. delay circuit as claimed in claim 1, it is characterised in that described load unit includes: the 5th transistor and the 6th transistor；
The end that controls of described 5th transistor is coupled to the second outfan of described delay circuit, and input is coupled to supply voltage, and outfan is coupled to the first outfan of described delay circuit；
The end that controls of described 6th transistor is coupled to the first outfan of described delay circuit, and input is coupled to supply voltage, and outfan is coupled to the second outfan of described delay circuit.
6. delay circuit as claimed in claim 5, it is characterised in that described load unit also includes: the 7th transistor and the 8th transistor；
The end that controls of described 7th transistor is coupled to the second outfan of described delay circuit, and input end grounding, outfan is coupled to the first outfan of described delay circuit；
The end that controls of described 8th transistor is coupled to the first outfan of described delay circuit, and input end grounding, outfan is coupled to the second outfan of described delay circuit.
7. delay circuit as claimed in claim 1, it is characterised in that described amplifying unit includes: the 9th transistor；
The end that controls of described 9th transistor is coupled to the first input end of described delay circuit, and input end grounding, outfan is coupled to the first outfan of described delay circuit.
8. delay circuit as claimed in claim 7, it is characterised in that described amplifying unit also includes: the tenth transistor；
The end that controls of described tenth transistor is coupled to the second input of described delay circuit, and input end grounding, outfan is coupled to the second outfan of described delay circuit.
9. a voltage controlled oscillator, it is characterised in that include at least two delay circuit as described in any one of claim 1-8；Described at least two delay circuit joins end to end into positive feedback.
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| CN201510006052.4A CN105827237B (en) | 2015-01-06 | 2015-01-06 | delay circuit and voltage controlled oscillator |
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| CN201510006052.4A CN105827237B (en) | 2015-01-06 | 2015-01-06 | delay circuit and voltage controlled oscillator |
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| CN105827237A true CN105827237A (en) | 2016-08-03 |
| CN105827237B CN105827237B (en) | 2018-09-07 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110518884A (en) * | 2019-08-20 | 2019-11-29 | 上海交通大学 | Be delayed amplifier |
| CN116346084A (en) * | 2023-03-14 | 2023-06-27 | 瑶芯微电子科技(上海)有限公司 | High-frequency noise suppression circuit |
| CN117559915A (en) * | 2024-01-12 | 2024-02-13 | 西北工业大学 | Dual-path inductance-based dual-mode oscillator |
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| CN101557213A (en) * | 2009-03-27 | 2009-10-14 | 华为技术有限公司 | Delay unit, annular oscillator and PLL circuit |
| CN101567679A (en) * | 2009-05-22 | 2009-10-28 | 清华大学 | Differential voltage-controlled adjustable time delay unit with full swing |
| US20130181781A1 (en) * | 2012-01-12 | 2013-07-18 | Chun Geik Tan | Differential ring oscillator and method for calibrating the differential ring oscillator |
| CN103812503A (en) * | 2012-11-15 | 2014-05-21 | 安凯(广州)微电子技术有限公司 | Differential delay unit circuit and ring oscillator |
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| CN101132167A (en) * | 2006-08-25 | 2008-02-27 | 松下电器产业株式会社 | Ring oscillator and semiconductor integrated circuit and electronic device including the same |
| CN101557213A (en) * | 2009-03-27 | 2009-10-14 | 华为技术有限公司 | Delay unit, annular oscillator and PLL circuit |
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| US20130181781A1 (en) * | 2012-01-12 | 2013-07-18 | Chun Geik Tan | Differential ring oscillator and method for calibrating the differential ring oscillator |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110518884A (en) * | 2019-08-20 | 2019-11-29 | 上海交通大学 | Be delayed amplifier |
| CN110518884B (en) * | 2019-08-20 | 2021-03-09 | 上海交通大学 | Time-delay amplifier |
| CN116346084A (en) * | 2023-03-14 | 2023-06-27 | 瑶芯微电子科技(上海)有限公司 | High-frequency noise suppression circuit |
| CN116346084B (en) * | 2023-03-14 | 2023-10-20 | 瑶芯微电子科技(上海)有限公司 | High-frequency noise suppression circuit |
| CN117559915A (en) * | 2024-01-12 | 2024-02-13 | 西北工业大学 | Dual-path inductance-based dual-mode oscillator |
| CN117559915B (en) * | 2024-01-12 | 2024-03-26 | 西北工业大学 | Dual-path inductance-based dual-mode oscillator |
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| CN105827237B (en) | 2018-09-07 |
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