CN115458611A - 下沉式封装结构 - Google Patents

下沉式封装结构 Download PDF

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CN115458611A
CN115458611A CN202211021317.4A CN202211021317A CN115458611A CN 115458611 A CN115458611 A CN 115458611A CN 202211021317 A CN202211021317 A CN 202211021317A CN 115458611 A CN115458611 A CN 115458611A
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chip
sensing
light source
substrate
light
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邓仲豪
黄建谕
陈怡永
吴高彬
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Eminent Electronic Technology Corp
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Abstract

本发明公开一种下沉式封装结构，包括一基板、一光学感测芯片及一壳体。该基板具有一凹洞，该凹洞具有第一深度。该光学感测芯片设置在该凹洞中，且电性连接该基板，该光学感测芯片表面具有一第一感测区域，用以感测光线。该壳体覆盖该基板与该光学感测芯片，该壳体包括一透光部分位于该第一感测区域的上方。

Description

下沉式封装结构
技术领域
本发明是有关一种光学传感器的封装结构，特别是关于一种光学传感器的下沉式封装结构。
背景技术
光学传感器可用于各式穿戴设备或移动装置中来感测光线。根据光学传感器的感测结果，穿戴设备或移动装置可以判断环境光强度、物件距离或使用者的心率等。由于穿戴设备及移动装置(例如，真无线耳机(TWS)以及智能手表(Smart watch))的空间相当有限，因此光学传感器的封装尺寸一直是各家厂商所注重的重点之一。
图1显示传统用以感测距离的光学传感器封装结构10，光学传感器封装结构10包括一基板11、一光源芯片12、一光学感测芯片15以及一壳体18。光源芯片12及光学感测芯片15通过黏着剂13及16固定在基板11上。打线14及17分别将光源芯片12及光学感测芯片15电性连接至基板11的导体垫片111及112。壳体18在基板11上，容纳及覆盖光源芯片12及光学感测芯片15。
传统缩小光学传感器封装结构10的尺寸的方法约可分为三种：(1)优化光学感测芯片15的设计，以降低芯片面积；(2)薄型化光源芯片12以降低芯片厚度；(3)提升制程能力以缩小封装公差。然而，优化光学感测芯片15的设计需要耗费大量的人力及时间成本或是需要采用更先进的制程，换言之，优化光学感测芯片15的方法需要较高的成本。薄型化光源芯片12则可能造成性能下降以及光源厂商执行困难等问题。缩小封装公差对于封装厂而言，是增加生产风险以及成本的改动，而且现有的封装制程已经不适合再继续将封装公差缩小。
如上所述，现有的缩小光学传感器封装结构10的尺寸的方法，需要所有供货商的配合，使得实际执行上窒碍难行，而且成本一直居高不下。
发明内容
本发明的目的，在于提出一种光学传感器的下沉式封装结构。
为达成上述目的，本发明的一种光学传感器的下沉式封装结构包括一基板、一光学感测芯片及一壳体。该基板具有一凹洞，该凹洞具有第一深度。该光学感测芯片设置在该凹洞中，且电性连接该基板，该光学感测芯片表面具有一第一感测区域，用以感测光线。该壳体覆盖该基板与该光学感测芯片，该壳体包括一透光部分位于该第一感测区域的上方。
由于本发明是将光学感测芯片放置在该基板的该凹洞中，因此可以缩小光学传感器的尺寸。
附图说明
图1显示传统的光学传感器封装结构。
图2显示本发明的下沉式封装结构应用在近接传感器的第一实施例。
图3显示图2的壳体的另一实施例。
图4显示本发明的下沉式封装结构应用在近接传感器的第二实施例。
图5显示本发明的下沉式封装结构应用在环境光传感器的第一实施例。
图6显示本发明的下沉式封装结构应用在环境光传感器的第二实施例。
图7显示本发明的下沉式封装结构应用在心率传感器的实施例。
附图标记说明：10-光学传感器封装结构；11-基板；111-导体垫片；112-导体垫片；12-光源芯片；13-黏着剂；14-打线；15-光学感测芯片；16-黏着剂；17-打线；18-壳体；20-近接传感器；21-基板；211-凹洞；212-防焊层；213-导体垫片；214-导体垫片；215-导体垫片；216-导体垫片；217-导体垫片；218-导体垫片；219-导体垫片；22-光源芯片；23-黏着剂；24-打线；25-光学感测芯片；251-第一感测区域；26-黏着剂；27-打线；28-金属膜层；29-壳体；291-挡墙；30-近接传感器；31-接地垫；32-打线；33-打线；40-环境光传感器；41-打线；42-打线；50-环境光传感器；51-光学感测芯片；511-第一感测区域；512-第二感测区域；52-第一偏振片；53-第二偏振片；54-四分之一波片；55-打线；56-打线；60-心率传感器；61-第一光源芯片；62-黏着剂；63-打线；64-第二光源芯片；65-黏着剂；66-打线；67-壳体；671-透光部分；672-透光部分；673-透光部分；674-挡墙；675-挡墙；68-打线；69-打线。
具体实施方式
图2显示本发明的下沉式封装结构应用在近接传感器(Proximity Sensor)的第一实施例。图2的近接传感器20包括一基板21、一光源芯片22、一光学感测芯片25、一金属膜层28及一壳体29。基板21具有一凹洞211，其中凹洞211具有第一深度d1。金属膜层28形成于凹洞211的各个内壁及底部的表面，用以降低环境电磁干扰(EMI)及来自基板21的光学串扰，进而增加光学感测芯片25的感测性能。光源芯片22及光学感测芯片25是设置在凹洞211中。光源芯片22通过黏着剂23固定在凹洞211的底部的金属膜层28上，并且通过打线24电性连接基板21上的导体垫片213。光源芯片22可以是但不限于LED芯片或垂直腔面射型激光器(Vertical-Cavity Surface-Emitting Laser；VCSEL)芯片。光学感测芯片25通过黏着剂26固定在凹洞211的底部的金属膜层28上，并且通过打线27电性连接基板21上的导体垫片214。光学感测芯片25的表面具有一第一感测区域251用以感测光线。壳体29覆盖基板21、光源芯片22与光学感测芯片25。在图2的实施例中，壳体29为全透明的封装，换言之，整个壳体29都可视为供光线通过的透光部分。在另一实施例中，壳体29也可以是不透明的封装材料，壳体29在光源芯片22及第一感测区域251上方设置有孔洞作为透光部分供光线通过。在一实施例中，光源芯片22为垂直腔面射型激光器，光源芯片22发射的光线经过壳体29的孔洞(即透光部分)发送到近接传感器20的外部。光源芯片22发射的光线在碰到物体后反射回到近接传感器20。反射的光线经过壳体29的透光部分进入光学感测芯片25的第一感测区域251。光学感测芯片25根据反射的光线产生一感测值供判断该物体的距离或位置。在其他实施例中，壳体29的孔洞设置有透镜以作为透光部份亦是可能的。相较于图1的传统的光学传感器封装结构10，图2所示的下沉式封装结构让光源芯片22和光学感测芯片25在基板21的凹洞211中，因此近接传感器20的厚度可以减少，进而缩小近接传感器20的尺寸。在图2的实施例中，光源芯片22和光学感测芯片25具有相同的厚度d2，且厚度d2小于或等于凹洞211的第一深度d1，但本发明不限于此。在其他实施例中，光源芯片22和光学感测芯片25的厚度可以不相同，而光源芯片22或光学感测芯片25的厚度也可以大于凹洞211的第一深度d1。在一实施例中，第一深度d1为T/2±30um，其中T为基板21的厚度。
在图2中，基板21上具有防焊层(solder mask)212用以保护基板21上的走线(图中未示)。防焊层212的边缘与凹洞211的边缘之间的距离A大于或等于200um。凹洞211的边缘与光源芯片22或光学感测芯片25的边缘之间的距离B大于或等于75um。凹洞211的边缘与近接传感器20或下沉式封装结构的边缘之间的距离C大于或等于100um。
在图2中，从光源芯片22的侧边射出的光线可能进入光学感测芯片25，进而影响光学感测芯片25的感测结果。在一实施例中，为了降低光源芯片22对光学感测芯片25的干扰，光源芯片22的中心点与第一感测区域251的中心点之间的距离D大于或等于0.8mm。图3显示图2的壳体29的另一实施例，图2与图3的近接传感器20的差别在于，图3的壳体29具有不透光的一挡墙291，设置在光源芯片22与光学感测芯片25之间，用以遮挡光源芯片22的侧边射出的光线，以防止光源芯片22对光学感测芯片25可能造成的干扰。在图3的实施例中，由于挡墙291的存在，因此光源芯片22的中心点与第一感测区域251的中心点之间的距离D可以小于0.8mm。
图4显示本发明的下沉式封装结构应用在近接传感器的第二实施例。类似于图2的近接传感器20，图4的近接传感器30同样包括一基板21、一光源芯片22、一光学感测芯片25、一金属膜层28及一壳体29。近接传感器20与近接传感器30的差别在于，光源芯片22与光学感测芯片25堆叠，并且增加一接地垫31。在图4中，接地垫31设置在光学感测芯片25上，与光学感测芯片25的第一感测区域251相邻。光源芯片22通过黏着剂23固定在接地垫31上，并通过打线32与光学感测芯片25电连接。光学感测芯片25通过黏着剂26固定在凹洞211的底部的金属膜层28上，并且通过打线33电性连接基板21上的导体垫片215。相较于图1的传统的光学传感器封装结构10，图4的近接传感器30在Y方向上的厚度略小或相等，但在X方向上的长度缩小，因此近接传感器30的尺寸较小。此外，在壳体29为全透明封装材料的情况下，相较于图1及图2的架构，由于图4的光源芯片22是堆叠在光学感测芯片25上，因此光源芯片22对光学感测芯片25的光学串扰会比较小。
在一实施例中，为了降低光源芯片22对第一感测区域251的干扰，图4的光源芯片22的中心点与第一感测区域251的中心点之间的距离D大于或等于0.8mm。在另一实施例中，图4的壳体29可以具有一挡墙(图中未示)在光源芯片22与第一感测区域251之间，以防止光源芯片22对第一感测区域251的干扰。
图5显示本发明的下沉式封装结构应用在环境光传感器的第一实施例。图5的环境光传感器40具有一基板21、一光学感测芯片25、一金属膜层28及一壳体29。基板21上具有防焊层212用以保护基板21上的走线(图中未示)。金属膜层28形成于基板21的凹洞211的各个内壁及底部的表面，用以降低环境电磁干扰及来自基板21的光学串扰。光学感测芯片25是设置在凹洞211中，并且通过黏着剂26固定在凹洞211的底部的金属膜层28上。光学感测芯片25通过打线41及42电性连接基板21上的导体垫片216及217。光学感测芯片25的表面具有一第一感测区域251。第一感测区域251感测进入环境光传感器40的光线以产生一感测值，以供判断环境光强度。壳体29覆盖基板21与光学感测芯片25。在图5的实施例中，壳体29为全透明的封装壳体，换言之，整个壳体29都可视为供光线通过的透光部分。在另一实施例中，壳体29也可以是不透明的封装材料，壳体29在第一感测区域251上方设置有孔洞作为透光部分供外部的光线进入。在其他实施例中，壳体29的孔洞设置有透镜以作为透光部份亦是可能的。相较于传统的环境光传感器10，图5所示的下沉式封装结构让光学感测芯片25在基板21的凹洞211中，因此图5的环境光传感器40的厚度可以减少，进而缩小环境光传感器40的尺寸。
图6显示本发明的下沉式封装结构应用在环境光传感器的第二实施例。图6的环境光传感器50具有一基板21、一光学感测芯片51、一金属膜层28、一第一偏振片52、一第二偏振片53及一四分之一波片54。金属膜层28形成于基板21的凹洞211的各个内壁及底部的表面，用以降低环境电磁干扰及来自基板21的光学串扰。光学感测芯片51是设置在凹洞211中，并且通过黏着剂26固定在凹洞211的底部的金属膜层28上。光学感测芯片51通过打线55及56电性连接基板21上的导体垫片218及219。光学感测芯片51具有一第一感测区域511及一第二感测区域512，光学感测芯片51依据第一感测区域511感测光线所产生的第一感测值以及第二感测区域512感测光线所产生的第二感测值判断环境光强度。第一偏振片52设置在光学感测芯片51上且覆盖第一感测区域511。第二偏振片53设置在光学感测芯片51上且覆盖第二感测区域512。第一偏振片52及第二偏振片53分别具有一第一偏振方向及一第二偏振方向以过滤光线，其中该第一偏振方向垂直于该第二偏振方向。四分之一波片54位于第一偏振片52及第二偏振片53的上方，作为封装的壳体。由于四分之一波片54为透光元件，因此四分之一波片54可视为环境光传感器50的封装壳体中供光线通过的透光部分。相较于图1所示的传统环境光传感器10，图6所示的下沉式封装结构让光学感测芯片51在基板21的凹洞211中，因此图6的环境光传感器50的厚度可以减少，进而缩小环境光传感器50的尺寸。
图7显示本发明的下沉式封装结构应用在心率传感器的实施例。图7的心率传感器60具有一基板21、一光学感测芯片25、一第一光源芯片61、一第二光源芯片64、一金属膜层28及一壳体67。基板21上具有防焊层212用以保护基板211上的走线(图中未示)。金属膜层28形成于基板21的凹洞211的各个内壁及底部的表面，用以降低环境电磁干扰及来自基板21的光学串扰。光学感测芯片25是设置在凹洞211中，并且通过黏着剂26固定在凹洞211的底部的金属膜层28上。光学感测芯片25通过打线63及66电性连接基板21上的导体垫片216及217。第一光源芯片61通过黏着剂62固定在光学感测芯片25上，并通过一打线68电性连接光学感测芯片25。第二光源芯片64通过黏着剂65固定在光学感测芯片25上，并通过一打线69电性连接光学感测芯片25。第一光源芯片61与第二光源芯片64所发出的光线具有不同波长。壳体67是不透明的封装材料，壳体67设置有透光部分671、672及673分别对应第一光源芯片61、光学感测芯片25的第一感测区域251以及第二光源芯片64。在一实施例中，透光部分671、672及673可以是孔洞或透镜。壳体67的挡墙674在第一感测区域251与第一光源芯片61之间，以防止第一光源芯片61对第一感测区域251可能造成的干扰。壳体67的挡墙675在第一感测区域251与第二光源芯片64之间，以防止第二光源芯片64对第一感测区域251可能造成的干扰。第一光源芯片61及第二光源64所发出的光线分别经透光部分671及673打到人体上。光线经人体的皮肤或血管反射后经透光部分672进入第一感测区域251。第一感测区域251感测光线以产生一感测值，以供判断心率值。相较于传统的心率传感器，图7所示的下沉式封装结构让光学感测芯片25在基板21的凹洞211中，且第一光源芯片61及第二光源64堆叠在光学感测芯片25上，因此图7的心率传感器60的厚度可以减少，进而缩小心率传感器60的尺寸。
在一实施例中，图7的壳体67可以不需要挡墙674及675，在此情况下，为了降低第一光源芯片61及第二光源芯片64对光学感测芯片25可能造成的干扰，第一光源芯片61的中心点与第一感测区域251的中心点之间的距离大于或等于0.8mm，第二光源芯片64的中心点与第一感测区域251的中心点之间的距离也大于或等于0.8mm。
在上述实施例中，基板21可以是但不限于无芯式(coreless)载板。
在上述实施例中，基板21的凹洞211中铺设了金属膜层28，但在其他实施例中，也可以省略金属膜层28。
在上述实施例中，只以近接传感器、环境传感器及心率传感器为例，但本发明不限于此，其他的光学传感器也可以使用本发明的下沉式封装结构。
以上所述仅是本发明的实施例而已，并非对本发明做任何形式上的限制，虽然本发明已以实施例公开如上，然而并非用以限定本发明，任何所属技术领域中具有通常知识者，在不脱离本发明技术方案的范围内，当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例，但凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本发明技术方案的范围内。

Claims (11)

1.一种下沉式封装结构，其特征在于，包括：
一基板，具有一凹洞，该凹洞具有第一深度；
一光学感测芯片，设置在该凹洞中，且电性连接该基板，该光学感测芯片表面具有一第一感测区域，用以感测光线；以及
一壳体，覆盖该基板与该光学感测芯片，该壳体包括一透光部分位于该第一感测区域的上方。
2.如权利要求1所述的下沉式封装结构，其特征在于，更包括一金属膜层形成于该凹洞的各个内壁及底部的表面，其中该光学感测芯片设置在该金属膜层上。
3.如权利要求1所述的下沉式封装结构，其特征在于，更包括：
一接地垫，设置在该光学感测芯片上，相邻该第一感测区域；以及
一光源芯片，设置在该接地垫上，用以发出光线，该光源芯片与该接地垫电连接。
4.如权利要求3所述的下沉式封装结构，其特征在于，该壳体包括一挡墙，位于该第一感测区域及该光源芯片之间。
5.如权利要求3所述的下沉式封装结构，其特征在于，该光源芯片的中心点与该第一感测区域的中心点之间的距离大于或等于0.8mm。
6.如权利要求2所述的下沉式封装结构，其特征在于，更包括：
一光源芯片，设置在该金属膜层上，用以发出光线；
其中，该壳体包括一挡墙位于该光学感测芯片及该光源芯片之间。
7.如权利要求1所述的下沉式封装结构，其特征在于，该光学感测芯片的表面更包括一第二感测区域，用以感测光线，该下沉式封装结构更包括：
一第一偏振片，覆盖该第一感测区域，具有一第一偏振方向；
一第二偏振片，覆盖该第二感测区域，具有垂直于该第一偏振方向的第二偏振方向；
其中，该透光部分包含一四分之一波片，且该四分之一波片位于该第一偏振片及该第二偏振片的上方。
8.如权利要求1所述的下沉式封装结构，其特征在于，该基板的防焊层的边缘与该凹洞的边缘之间的距离大于或等于200um，该凹洞的边缘与该光学感测芯片的边缘之间的距离大于或等于75um，该凹洞的边缘与该下沉式封装结构的边缘之间的距离大于或等于100um。
9.如权利要求1所述的下沉式封装结构，其特征在于，该基板的厚度为T，该第一深度为T/2±30um。
10.如权利要求1所述的下沉式封装结构，其特征在于，该基板为无芯式载板。
11.如权利要求1所述的下沉式封装结构，其特征在于，该光学感测芯片的厚度小于或等于该第一深度。
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