CN115440269B

CN115440269B - Data transmission circuit, data processing circuit and memory

Info

Publication number: CN115440269B
Application number: CN202110609555.6A
Authority: CN
Inventors: 尚为兵; 李红文; 冀康灵; 何军; 龚园媛; 应战
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2021-06-01
Filing date: 2021-06-01
Publication date: 2024-05-14
Anticipated expiration: 2041-06-01
Also published as: CN115440269A

Abstract

The embodiment of the application relates to a data transmission circuit, a data processing circuit and a memory. The data transmission circuit includes: the data writing circuit is used for transmitting data to be written to the global data line; the check write circuit is used for transmitting check data to the global data line, and the check write circuit and the data write circuit are both first circuits; the first circuit generates a pull-up enable signal in response to the precharge enable signal, and enables the valid pull-up enable signal to control the first pull-up circuit to output a global data signal; the first circuit also responds to the write enable signal, generates a pull-up enable signal and a pull-down enable signal according to data to be written, transmits a global data signal to a global data line, and enables the effective pull-down enable signal to control the first pull-down circuit to output the global data signal; the driving capability of the first pull-up circuit in the data write circuit is equal to that of the first pull-down circuit in the check write circuit, and the driving capability of the first pull-down circuit in the check write circuit is stronger than that of the first pull-down circuit in the data write circuit.

Description

Data transmission circuit, data processing circuit and memory

Technical Field

The embodiment of the application relates to the technical field of memories, in particular to a data transmission circuit, a data processing circuit and a memory.

Background

A semiconductor memory is a memory which is accessed using a semiconductor circuit, and among them, a dynamic random access memory (Dynamic Random Access Memory, DRAM) is widely used in various fields with its fast memory speed and high integration. In order to obtain higher data read-write reliability, a verification-related circuit needs to be arranged in the semiconductor memory to verify whether the read data is accurate, but the introduction of the verification-related circuit may cause the read-write speed of the memory to be slow, and the performance of the semiconductor memory is affected.

Disclosure of Invention

The embodiment of the application provides a data transmission circuit, a data processing circuit and a memory, which can optimize the read-write speed of the memory.

A data transmission circuit, comprising:

The data writing circuit is used for transmitting data to be written to a global data line connected with the data storage unit;

the verification write circuit is used for transmitting verification data to a global data line connected with the verification storage unit, the verification data corresponds to data to be written, and the verification write circuit and the data write circuit are both first circuits;

the first circuit includes: a first pull-up circuit and a first pull-down circuit;

The first circuit is used for responding to the precharge enable signal, generating a pull-up enable signal, and enabling the valid pull-up enable signal to control the first pull-up circuit to output a global data signal; the first circuit is also used for responding to the write enable signal, generating a pull-up enable signal and a pull-down enable signal according to the data to be written, transmitting a global data signal to a global data line, and enabling the effective pull-down enable signal to control the first pull-down circuit to output the global data signal, wherein the pull-up enable signal and the pull-down enable signal are effective in time sharing;

The driving capability of the first pull-up circuit in the data write circuit is equal to the driving capability of the first pull-up circuit in the verification write circuit, and the driving capability of the first pull-down circuit in the verification write circuit is stronger than the driving capability of the first pull-down circuit in the data write circuit.

In one embodiment, the electrical parameters of the devices corresponding to the first pull-down circuit in the data write circuit and the verification write circuit are not identical, so that the driving capability of the first pull-down circuit in the verification write circuit is stronger than that of the first pull-down circuit in the data write circuit.

In one embodiment, the first pull-up circuit comprises a first pull-up transistor, the first pull-up transistor is turned on at a low level, a control terminal of the first pull-up transistor is used for receiving an inverted signal of data to be written, and a first terminal of the first pull-up transistor is connected with a power supply voltage terminal;

The first pull-down circuit comprises a first pull-down transistor, the first pull-down transistor is conducted at a high level, the control end of the first pull-down transistor is used for receiving an inverted signal of data to be written, the first end of the first pull-down transistor is connected with the grounding end, and the second end of the first pull-down transistor is connected with the second end of the first pull-up transistor;

the channel width-to-length ratio of the first pull-down transistor in the verification write circuit is larger than that of the first pull-down transistor in the data write circuit.

In one embodiment, the channel width to length ratio of the first pull-up transistor in the verify write circuit is equal to the channel width to length ratio of the first pull-up transistor in the data write circuit.

In one embodiment, the threshold voltage of the first pull-up transistor in the verify write circuit is equal to the threshold voltage of the first pull-up transistor in the verify write circuit.

In one embodiment, the threshold voltage of the first pull-down transistor in the verify write circuit is less than the threshold voltage of the first pull-down transistor in the verify write circuit.

In one embodiment, the data transfer circuit is configured with a precharge phase in which the precharge enable signal is active and a data write phase in which the write enable signal is active, the first circuit further comprising:

And the logic operation unit is respectively connected with the first pull-up transistor and the first pull-down transistor and is used for responding to the write enable signal in the data writing stage to generate an inversion signal of data to be written.

And the NOT circuit is connected with the logic operation unit and is used for receiving the precharge enabling signal and controlling the logic operation unit to output a low-level signal in the precharge stage.

In one embodiment, the logic operation unit includes:

The first input end of the AND gate circuit is used for receiving data to be written, and the second input end of the AND gate circuit is used for receiving a write enable signal;

And the first input end of the first NOR gate circuit is connected with the output end of the AND gate circuit, the second input end of the first NOR gate circuit is connected with the output end of the NOR gate circuit, the precharge enable signal is used for switching the data transmission circuit to the precharge stage or the data writing stage, and the output end of the first NOR gate circuit is connected with the control end of the first pull-up transistor.

In one embodiment, the output terminal of the first nor gate is further connected to the control terminal of the first pull-down transistor.

In one embodiment, the logic operation unit further includes:

The first input end of the NAND gate circuit is used for receiving a precharge enabling signal, and the second input end of the NAND gate circuit is used for receiving a write enabling signal;

And the first input end of the second NOR gate circuit is used for receiving data to be written, the second input end of the second NOR gate circuit is connected with the output end of the NAND gate circuit, and the output end of the second NOR gate circuit is connected with the control end of the first pull-down circuit.

In one embodiment, the data write circuit and the verify write circuit respectively transmit global data signals to corresponding global data lines in response to the same write enable signal.

In one embodiment, the data transmission circuit further comprises:

The data reading circuit is used for acquiring stored data to be read from the global data line connected with the data storage unit so as to read the data to be read;

The verification reading circuit is used for acquiring stored verification data from the global data line connected with the verification storage unit so as to read the stored verification data, wherein the stored verification data corresponds to the stored data to be read;

wherein, the driving capability of the verification reading circuit is equal to the driving capability of the data reading circuit.

In one embodiment, the circuit structures of the data reading circuit and the verification reading circuit are both second circuits, and the electrical parameters of the corresponding devices in the data reading circuit and the verification reading circuit are the same, so that the driving capability of the verification reading circuit is equal to the driving capability of the data reading circuit.

In one embodiment, the global data line is further configured to transmit a read signal, the level state of the read signal is the same as the level state of the data to be read, and the second circuit includes:

an input unit for receiving a global data signal in response to a read enable signal;

a reference unit for receiving a reference data signal in response to a read enable signal;

The precharge unit is connected with the input unit and the first node, and connected with the reference unit and the second node, and is used for respectively precharging the first node and the second node to a preset level in response to a precharge enabling signal;

And the output unit is connected with the input unit and the reference unit respectively and is used for generating a read-out data signal according to the global data signal and the reference data signal.

A data processing circuit, comprising:

a data transmission circuit as described above;

and the verification generating circuit is connected with the verification writing circuit and is used for acquiring the data to be written, generating corresponding verification data according to the data to be written and transmitting the verification data to the verification writing circuit.

A memory, comprising: a data storage unit, a check storage unit and a data processing circuit as described above.

In the above data transmission circuit, the data processing circuit, and the memory, the data transmission circuit includes: the data writing circuit is used for transmitting data to be written to a global data line connected with the data storage unit; the verification write circuit is used for transmitting verification data to a global data line connected with the verification storage unit, the verification data corresponds to data to be written, and the verification write circuit and the data write circuit are both first circuits; the first circuit includes: a first pull-up circuit and a first pull-down circuit; the first circuit is used for responding to the precharge enable signal, generating a pull-up enable signal, and enabling the valid pull-up enable signal to control the first pull-up circuit to output a global data signal; the first circuit is also used for responding to the write enable signal, generating a pull-up enable signal and a pull-down enable signal according to the data to be written, transmitting a global data signal to a global data line, and enabling the effective pull-down enable signal to control the first pull-down circuit to output the global data signal, wherein the pull-up enable signal and the pull-down enable signal are effective in time sharing; the driving capability of the first pull-up circuit in the data write circuit is equal to the driving capability of the first pull-up circuit in the verification write circuit, and the driving capability of the first pull-down circuit in the verification write circuit is stronger than the driving capability of the first pull-down circuit in the data write circuit. The first pull-up circuit in the verification write circuit and the data write circuit is arranged to respond to the precharge enabling signal to generate a pull-up enabling signal, the effective pull-up enabling signal is enabled to control the first pull-up circuit to output a global data signal, the first circuit responds to the write enabling signal to generate the pull-up enabling signal and the pull-down enabling signal according to data to be written and transmit the global data signal to a global data line, the effective pull-down enabling signal is enabled to control the first pull-down circuit to output the global data signal, the driving capacity of the first pull-up circuit in the data write circuit is equal to the driving capacity of the first pull-up circuit in the verification write circuit, the driving capacity of the first pull-down circuit in the verification write circuit is higher than the driving capacity of the first pull-down circuit in the data write circuit, and the transmission speed of verification data can be higher than that of the data to be stored.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the related art, the drawings that are required to be used in the embodiments or the related technical descriptions will be briefly described, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.

FIG. 1 is one of the block diagrams of a data processing circuit according to an embodiment;

FIG. 2 is one of the block diagrams of the first circuit of an embodiment;

FIG. 3 is a second block diagram of a first circuit according to an embodiment;

FIG. 4 is a timing diagram of writing data to be stored and verification data according to an embodiment;

FIG. 5 is a second block diagram of a data processing circuit according to an embodiment;

FIG. 6 is one of the block diagrams of the second circuit of an embodiment;

FIG. 7 is a schematic diagram of a partial structure of a second circuit according to an embodiment;

FIG. 8 is a timing diagram of signals in the PWM unit of the embodiment of FIG. 7;

FIG. 9 is a schematic diagram of a first control circuit according to an embodiment;

FIG. 10 is a schematic diagram of a second control circuit according to an embodiment;

FIG. 11 is a schematic diagram of an output unit according to an embodiment;

FIG. 12 is a second schematic diagram of an output unit according to an embodiment;

FIG. 13 is a second schematic diagram of a partial structure of a second circuit according to an embodiment.

Reference numerals illustrate:

10. A data transmission circuit; 100. a data writing circuit; 200. a verification write circuit; 300. a first circuit; 302. a first pull-up circuit; 304. a first pull-down circuit; 306. a logic operation unit; 308. a NOT circuit; 310. an AND gate circuit; 312. a first nor gate; 314. a NAND gate circuit; 316. a second nor gate; 400. a data storage unit; 500. verifying the storage unit; 600. a data reading circuit; 700. a verification read circuit; 800. a second circuit; 802. an input unit; 8021. a first switch; 8022. a first control circuit; 804. a reference unit; 8041. a second control circuit; 8042. a second switch; 806. a pre-charging unit; 808. an output unit; 8081. a first output circuit 8081; 8082. a second output circuit; 810. a pulse width adjusting unit; 20. and a check generating circuit.

Detailed Description

In order to facilitate an understanding of the embodiments of the present application, the embodiments of the present application will be described more fully below with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. The embodiments of the application may, however, be embodied in many different forms and are not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which embodiments of the application belong. The terminology used in the description of the embodiments of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of embodiments of the application. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.

It will be understood that the terms first, second, etc. as used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element. For example, the first node YIONloc may be referred to as the second node YIOloc, and similarly, the second node YIOloc may be referred to as the first node YIONloc, without departing from the scope of the application. Both the first node YIONloc and the second node YIOloc are nodes, but they are not the same node.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise. In the description of the present application, the meaning of "several" means at least one, such as one, two, etc., unless specifically defined otherwise.

Fig. 1 is one of the block diagrams of a Data processing circuit according to an embodiment of the present application, and it should be noted that, the Data to be written Data shown in the drawings according to the embodiments of the present application refers to Data to be stored that actually needs to be stored for the Data writing circuit 100, and refers to check Data generated according to the Data to be stored for the check writing circuit 200. Referring to fig. 1, in the present embodiment, a data processing circuit includes a data transmission circuit 10 and a check generation circuit 20.

The check generation circuit 20 is configured to receive data to be stored, and generate check data according to the data to be stored. The check data is generated and stored in the data writing stage to determine whether an error occurs in the data reading stage, that is, whether an error occurs in the data reading and writing process of the data by determining whether the data read in the data storage unit 400 is identical to the data to be stored. The verification generating circuit 20 can be used for verifying data information of a plurality of storage arrays, so that the number of the verification generating circuits 20 is optimized, and a small-volume semiconductor memory is further provided. It is to be understood that the check generating circuit 20 may have any circuit configuration having a check data generating function, and the present embodiment is not limited to a specific type of the check generating circuit 20, and may have at least one of a parity check function, an error correction check function, and the like.

The memory array includes a plurality of data memory cells 400 for storing data signals and a plurality of check memory cells 500 for implementing a memory function of the semiconductor memory. The data storage unit 400 is used for storing data to be stored, which is externally input to the memory, and the verification storage unit 500 is used for storing verification data generated according to the data to be stored. Specifically, the memory cell further comprises a storage capacitor and a transistor, wherein the control end of the transistor is connected with the word line, the first end of the transistor is connected with the storage capacitor, and the second end of the transistor is connected with the bit line. When the word line control transistor is turned on, the storage capacitor is turned on with the bit line, so that reading and writing of data information are realized, namely, when the data information is read, the storage capacitor transmits the stored data information to the bit line; when writing data information, the bit line transmits the data information to be written to the storage capacitor.

The data transfer circuit 10 includes a data write circuit 100 and a verify write circuit 200. The data transmission circuit 10 is respectively connected to the check generating circuit 20 and the storage array, and is used for transmitting data to be stored to the data storage unit 400 and transmitting check data to the check storage unit 500. Specifically, the data writing circuit 100 is configured to transmit data to be written to a global data line connected to the data storage unit 400, so as to store the data to be written; the check writing circuit 200 is configured to transmit check data to a global data line connected to the check storage unit 500, so as to store the check data, where the check data corresponds to data to be written. The verification write circuit 200 and the data write circuit 100 are both the first circuit 300, and it is understood that the data write circuit 100 and each element in the verification write circuit 200 correspond to each other and have the same connection relationship. In this embodiment, by setting the data write circuit 100 and the verification write circuit 200 with the same circuit structure, the parameter optimization difficulty of the semiconductor memory can be reduced, so that the difficulty in the mask design process and the memory manufacturing process is reduced, and the preparation yield of the semiconductor memory is further improved.

The first circuit 300 includes: a first pull-up circuit 302 and a first pull-down circuit 304; the first circuit 300 is configured to generate a pull-up enable signal in response to the precharge enable signal EQ, and enable the active pull-up enable signal to control the first pull-up circuit 302 to output a global data signal; the first circuit 300 is further configured to generate a pull-up enable signal and a pull-down enable signal according to the Data to be written Data in response to the write enable signal WrEn, and transmit a global Data signal to the global Data line YIO, and enable the active pull-down enable signal to control the first pull-down circuit 304 to output the global Data signal. In this embodiment, the pull-up enable signal and the pull-down enable signal are enabled in a time-sharing manner, so that the global Data signal transmitted to the global Data line YIO has a certain level state, and the certain level state is specifically the same as the level state of the Data to be written. The global data signal includes a signal that is subsequently transmitted on the global data line, and it should be clear that the global data signal herein includes a high-level global data signal output by the first pull-up circuit 302 and a low-level global data signal output by the first pull-down circuit 304, and the high-level global data signal and the low-level global data signal are transmitted to the global data line in a time-sharing manner. Before receiving the Data to be written Data, the first circuit 300 has controlled the first pull-up circuit 302 to output a high-level global Data signal in response to the precharge enable signal EQ, if the first circuit 300 generates an enable valid pull-up enable signal according to the Data to be written Data, the first circuit 300 directly transmits the high-level global Data signal generated by controlling the first pull-up circuit 302 in response to the precharge enable signal EQ to the global Data line YIO, and controls the first pull-up circuit 302 to continue outputting the high-level global Data signal by enabling the valid pull-up enable signal, and if the first circuit 300 generates an enable valid pull-down enable signal according to the Data to be written Data, the first circuit 300 controls the first pull-down circuit 304 to output a low-level global Data signal and transmits the low-level global Data signal to the global Data line YIO.

The data write circuit 100 and the check write circuit 200 are used for synchronously transmitting data to the corresponding global data line YIO, and it should be clear that the synchronous transmission in this embodiment is not limited to the fact that two data must be written at the same time, and synchronous transmission means that the check data with the corresponding relationship and the data to be stored complete transmission in the same data writing period. For example, the writing process of the check data and the data to be stored may be performed in response to the same enable signal, so as to implement a synchronous transmission function, for example, the data writing circuit 100 and the check writing circuit 200 respectively transmit data to the corresponding global data line group in response to the same write enable signal WrEn, so that, on one hand, the number of signals required may be saved, and on the other hand, the writing synchronism of the data to be stored and the check data may be improved. In this embodiment, the driving capability of the first pull-up circuit 302 in the data write circuit 100 is equal to the driving capability of the first pull-up circuit 302 in the verification write circuit 200, and the driving capability of the first pull-down circuit 304 in the verification write circuit 200 is stronger than the driving capability of the first pull-down circuit 304 in the data write circuit 100, wherein the driving capability of the first pull-up circuit 302 and the first pull-down circuit 304 can be characterized by write currents, and therefore, the write current of the first pull-up circuit 302 in the verification write circuit 200 in this embodiment is equal to the write current of the first pull-up circuit 302 in the data write circuit 100, and the write current of the first pull-down circuit 304 in the verification write circuit 200 is greater than the write current of the first pull-down circuit 304 in the data write circuit 100.

The data to be stored can be directly written into the data storage unit 400 through the data writing circuit 100, and the verification data needs to be generated according to the data to be stored, so that the time for the verification data to reach the verification writing circuit 200 is necessarily later than the time for the data to be stored to reach the data writing circuit 100, and correspondingly, the time for the verification data to be written into the verification storage unit 500 is slightly later than the corresponding writing time of the data to be stored, thereby causing the problem of poor data writing synchronism and further increasing the writing speed. In this embodiment, the first circuit responds to the precharge enable signal, and controls the first pull-up circuit to output in advance the global data signal transmitted to the global data line according to the data to be written, and by setting the first pull-down circuit with stronger driving capability in the verification write circuit 200, the overall duration of the data writing of the verification write circuit 200 can be shortened, so that the transmission speed of the verification data is greater than the transmission speed of the data to be stored, thereby effectively compensating the time consumed in the process of generating the verification data, and further optimizing the writing speed of the stored data.

In one embodiment, the electrical parameters of the corresponding devices of the first pull-up circuit 302 in the data write circuit 100 and the verification write circuit 200 are identical, so that the driving capability of the first pull-up circuit 302 in the verification write circuit 200 is equal to the driving capability of the first pull-up circuit 302 in the data write circuit 100. The corresponding devices refer to two devices which are located at the same position in the two circuits and have the same connection relationship, and the types of the corresponding devices can be, but are not limited to, MOS transistors, triodes, diodes and the like, and it is understood that the devices in the embodiments of the present application are not limited to a single element, that is, the devices formed by connecting a plurality of elements together are also included.

In one embodiment, the electrical parameters of the corresponding devices of the first pull-down circuit 304 in the data write circuit 100 and the verification write circuit 200 are not identical, so that the driving capability of the first pull-down circuit 304 in the verification write circuit 200 is stronger than that of the first pull-down circuit 304 in the data write circuit 100.

Fig. 2 is one of the block diagrams of the first circuit of an embodiment, referring to fig. 2, in one embodiment, the first pull-up circuit 102 includes a first pull-up transistor T1, the first pull-down circuit 104 includes a first pull-down transistor T2, and the first pull-up transistor T1 and the first pull-down transistor T2 have different conduction types, one of which is turned on at a high level, and the other of which is turned on at a low level. Specifically, the first pull-up transistor T1 is turned on at a low level, the control terminal of the first pull-up transistor T1 is configured to receive an inversion signal of the Data to be written, and the first terminal of the first pull-up transistor T1 is connected to the power supply voltage terminal. The first pull-down transistor T2 is turned on at a high level, the control terminal of the first pull-down transistor T2 is configured to receive an inverted signal of the Data to be written, the first terminal of the first pull-down transistor T2 is connected to the ground terminal, and the second terminal of the first pull-down transistor T2 is connected to the second terminal of the first pull-up transistor T1. Specifically, in the precharge phase, the precharge enable signal EQ is at a low level, the first pull-up transistor T1 is turned on, and the output voltage is a global data signal of the power supply voltage, that is, a global data signal of a high level is output, thereby implementing precharge; in the Data writing stage, the precharge enable signal EQ is at a high level, the write enable signal WrEn is at a high level, the first circuit 300 is capable of performing Data writing according to the Data signal, and when the Data signal is at a high level, for example, signals received by the control terminal of the first pull-up transistor T1 and the control terminal of the second pull-up transistor T3 are both low-level signals, the first pull-up transistor T1 is turned on, the first pull-down transistor T2 is turned off, the sustain voltage is a global Data signal of a power supply voltage, and the power supply voltage is transmitted to the global Data line YIO, and at this time, the write signal is at a high level, so that a signal on the global Data line YIO is the same as a Data signal to be written.

The channel width-to-length ratio of the first pull-down transistor in the verification write circuit is greater than that of the first pull-down transistor in the data write circuit, and it can be understood that the greater the channel width-to-length ratio of the transistor is, the greater the write current thereof is, and accordingly the stronger the driving capability is, therefore, the driving capability of the first pull-down transistor T2 of the verification write circuit 200 is greater than that of the first pull-down transistor T2 of the data write circuit 100, thereby improving the data transmission speed of the global data signal output by the first pull-down transistor T2 in the verification write circuit 200, and further improving the writing speed of the semiconductor memory.

In one embodiment, the channel width to length ratio of the first pull-up transistor in the verify write circuit is equal to the channel width to length ratio of the first pull-up transistor in the data write circuit, so that the data transmission speed of the global data signal output by the first pull-up transistor T1 in the verify write circuit 200 is equal to the data transmission speed of the global data signal output by the first pull-up transistor T1 in the data write circuit 100.

In one embodiment, the threshold voltage of the first pull-up transistor in the verify write circuit is equal to the threshold voltage of the first pull-up transistor in the verify write circuit. It will be appreciated that the smaller the threshold voltage, the greater the write current thereof and correspondingly the stronger the drive capability, and therefore, the threshold voltage of the first pull-up transistor in the verify write circuit is equal to the threshold voltage of the first pull-up transistor in the data write circuit, so that the data transmission speed of the global data signal output by the first pull-up transistor T1 in the verify write circuit 200 is equal to the data transmission speed of the global data signal output by the first pull-up transistor T1 in the data write circuit 100. Alternatively, the threshold voltages of the transistors may be changed by adjusting the doping concentrations, that is, different doping concentrations are used to form the first pull-down transistor T2 of the verify write circuit 200 and the first pull-down transistor T2 of the data write circuit 100, respectively, to achieve different threshold voltages.

In one embodiment, the threshold voltage of the first pull-down transistor in the verify write circuit is less than the threshold voltage of the first pull-down transistor in the verify write circuit. Similarly to the above description, the smaller the threshold voltage, the larger the write current thereof, and accordingly the stronger the driving capability, so that the threshold voltage of the first pull-down transistor in the verify write circuit is smaller than the threshold voltage of the first pull-down transistor in the data write circuit, so that the driving capability of the first pull-down transistor T2 of the verify write circuit 200 is stronger than the driving capability of the first pull-down transistor T2 of the data write circuit 100, thereby improving the data transmission speed of the global data signal output by the first pull-down transistor T2 in the verify write circuit 200, and further improving the writing speed of the semiconductor memory. Alternatively, the threshold voltages of the transistors may be changed by adjusting the doping concentrations, that is, different doping concentrations are used to form the first pull-down transistor T2 of the verify write circuit 200 and the first pull-down transistor T2 of the data write circuit 100, respectively, to achieve different threshold voltages.

Referring to fig. 2, in one embodiment, the first circuit 300 further includes: a logic operation unit 306 and an inverter circuit 308. The logic operation unit 306 is connected to the first pull-up transistor T1 and the first pull-down transistor T2, respectively, for generating an inversion signal of the Data to be written in response to the write enable signal WrEn in the Data writing stage. The not gate 308 is connected to the logic operation unit 306, and is configured to receive the precharge enable signal EQ, and control the logic operation unit 306 to output a low level signal during the precharge phase. In this embodiment, the precharge enable signal EQ further acts on the first circuit 300, and when the precharge enable signal EQ is at a low level, the data transmission circuit is in a precharge phase, and under the effect of the not gate 308, the high-level inverted precharge enable signal EQ is transmitted to the logic operation unit 306, so as to control the logic operation unit 306 to keep the level state of the output signal unchanged during the precharge phase, thereby improving the stability and reliability of the circuit.

With continued reference to fig. 2, in one embodiment, the logic operation unit 306 includes an and circuit 310 and a first nor circuit 312. A first input terminal of the and circuit 310 is configured to receive Data to be written, and a second input terminal of the and circuit 310 is configured to receive a write enable signal WrEn; in the Data writing phase, the write enable signal WrEn is high, so the signal output by the and circuit 310 follows the Data signal input at the first input terminal. A first input terminal of the first nor gate 312 is connected to the output terminal of the and gate 310, a second input terminal of the first nor gate 312 is connected to the output terminal of the nor gate 308, and is configured to receive an inverted signal of a precharge enable signal EQ, where the precharge enable signal EQ is used to switch the data transmission circuit to the precharge phase or the data writing phase, and the output terminal of the first nor gate 312 is connected to the control terminal of the first pull-up transistor. Further, the output terminal of the first nor gate 312 may be further connected to the control terminal of the first pull-down transistor T2, so as to control the first pull-up transistor T1 and the first pull-down transistor T2 simultaneously based on one signal, thereby saving the number of signal wires. In the precharge phase, the precharge enable signal EQ is low, the output signal of the nor gate 308 is high, and if one input terminal of the first nor gate 312 is high, the output signal must be low, so that the write signals received by the control terminals of the first pull-up transistor T1 and the first pull-down transistor T2 are kept unchanged. In the Data write phase, both precharge enable signal EQ and write enable signal WrEn are high, thereby making the signal on global Data line YIO correspond to the Data signal.

Fig. 3 is a second block diagram of the first circuit according to an embodiment, referring to fig. 3, in one embodiment, the logic operation unit 306 further includes: a nand gate 314 and a second nor gate 316. A first input of the nand gate 314 is for receiving the precharge enable signal EQ, and a second input of the nand gate 314 is for receiving the write enable signal WrEn; the first input end of the second nor gate circuit 316 is used for receiving the Data to be written, the second input end of the second nor gate circuit 316 is connected to the output end of the nand gate circuit 314, and the output end of the second nor gate circuit 316 is connected to the control end of the first pull-down circuit T2. The first pull-up transistor T1 is controlled by the first nor gate 312, and the control method is as in the previous embodiment, and will not be described herein. In the precharge phase, the precharge enable signal EQ is low, the output signal of the nand gate 314 is high, and if one input terminal of the second nor gate 316 is high, the output signal must be low, so that the write signals received by the control terminals of the first pull-up transistor T1 and the first pull-down transistor T2 are kept unchanged. In the Data write phase, both precharge enable signal EQ and write enable signal WrEn are high, thereby making the signal on global Data line YIO correspond to the Data signal. In this embodiment, the control reliability of the first pull-up transistor T1 and the first pull-down transistor T2 can be effectively improved by controlling the first pull-up transistor T1 and the first pull-down transistor T2 in one-to-one correspondence with each other through two logic gates.

Fig. 4 is a write timing diagram of data to be stored and check data according to an embodiment, where the data write circuit 100 and the check write circuit 200 according to this embodiment each employ the first circuit 300 of the embodiment of fig. 3, referring to fig. 8, based on the first circuit 300 of the embodiment of fig. 3, a time tdp required for writing low-level check data is shorter than a time td required for writing low-level data to be stored, and the pre-charge phase makes the global data signal preset value high, and a time for outputting the global data signal according to the data to be written when transmitting the high-level check data and the high-level data to be stored is negligible, thereby improving a writing speed of the semiconductor memory.

FIG. 5 is a block diagram of a data processing circuit according to a second embodiment, and referring to FIG. 5, in one embodiment, the signal processing further includes a data reading circuit 600 and a verification reading circuit 700. The Data reading circuit 600 is configured to obtain Data to be read Data from the global Data line group connected to the Data storage unit 400, so as to read the Data to be read Data; the check reading circuit 700 is configured to obtain check Data from a global Data line connected to the check storage unit 500, so as to read stored check Data, where the stored check Data corresponds to Data to be read. Wherein the driving capability of the verify-read circuit 700 is equal to the driving capability of the data-read circuit 600. In the Data reading stage, since the read Data can be verified based on the verification Data after the read operation of the Data to be read Data is completed, the reading speeds of the Data reading circuit 600 and the verification reading circuit 700 are equivalent, and the reading speed of the semiconductor memory is not affected, but in the embodiment, the design difficulty and the manufacturing difficulty of the reading circuit can be reduced by adopting the verification reading circuit 700 and the Data reading circuit 600 with the same driving capability, so that the manufacturing yield of the semiconductor memory is improved.

In one embodiment, the circuit structures of the data reading circuit 600 and the verification reading circuit 700 are the second circuit 800, and the electrical parameters of the corresponding devices in the data reading circuit 600 and the verification reading circuit 700 are the same. Specifically, fig. 6 is one of the block diagrams of the second circuit according to an embodiment, referring to fig. 6, in this embodiment, the global Data line YIO is further used to transmit a read signal, where the level state of the read signal is the same as the Data to be read, and the second circuit 800 includes an input unit 802, a reference unit 804, a pre-charge unit 806, and an output unit 808.

The input unit 802 is configured to receive a global data signal YIO in response to an externally input read enable signal RdEn. The reference unit 804 is configured to receive a reference data signal Ref in response to a read enable signal RdEn. The pre-charge unit 806 and the input unit 802 are connected to the first node YIONloc and the reference unit 804 are connected to the second node YIOloc, and the pre-charge unit 806 is used for pre-charging the first node YIONloc and the second node YIOloc to predetermined levels in response to the pre-charge enable signal EQ before data reading. The output unit 808 is connected to the input unit 802 and the reference unit 804, respectively, for generating the read Data signal Data based on the global Data signal YIO and the reference Data signal Ref. In this embodiment, first, in the precharge phase, the first node YIONloc and the second node YIOloc are precharged to enable accurate and fast reading of the data to be read. Then, in the data reading stage, the process and result of reading data can be adjusted by the reference data signal Ref received by the reference unit 804, so as to improve the accuracy of data reading. The specific reference data signal Ref may be preset and stored in the semiconductor memory according to a performance test result before the semiconductor memory leaves the factory.

Fig. 7 is a schematic diagram of a partial structure of a second circuit according to an embodiment, referring to fig. 7, in this embodiment, the pre-charging unit 806 includes transistors T14 to T22. Specifically, the transistors T14 to T16 form a precharge circuit, the first terminal of the transistor T14 is connected to the power supply terminal, the first terminal of the transistor T15 is connected to the power supply terminal, the first terminal of the transistor T16 is connected to the second terminal of the transistor T14, the second terminal of the transistor T16 is connected to the second terminal of the transistor T15, and the control terminals of the three transistors simultaneously receive the precharge enable signal EQ, thereby realizing fast precharge. The transistors T17 to T20 together form a positive feedback circuit, i.e. the transistors T17 to T20 form an amplifying circuit, and in the data reading stage, the signals of the first node YIONloc and the second node YIOloc are amplified, so that the signal of the global data line YIO is transmitted to the subsequent output unit 808. Specifically, the control terminal of the transistor T17 and the control terminal of the transistor T19 are connected to the second terminal of the transistor T16, respectively, the control terminal of the transistor T18 and the control terminal of the transistor T20 are connected to the first terminal of the transistor T16, respectively, the first terminal of the transistor T17 and the first terminal of the transistor T18 are connected to the power supply terminal, respectively, the second terminal of the transistor T17 is connected to the first terminal of the transistor T19, the second terminal of the transistor T18 is connected to the first terminal of the transistor T20, and the second terminal of the transistor T19 and the second terminal of the transistor T20 are connected to the first terminal of the transistor T11, respectively. In some embodiments, the precharge circuit further includes a control terminal of the transistor T21 and a transistor T22, the control terminals of which respectively receive the precharge enable signal EQ, a first terminal of the transistor T21 and a first terminal of the transistor T22 are respectively connected to the power supply terminal, a second terminal of the transistor T21 is connected to the first node YIONloc, and a second terminal of the transistor T22 is connected to the second node YIOloc. It should be noted that the positive feedback circuit (amplifying circuit) in the embodiment of fig. 7 is only for illustration, and is not intended to limit the protection scope of the present application, and other positive feedback circuits with the same effect are also included in the protection scope of the present application. It should be noted that, in this embodiment, the amplifying circuit is assigned to the pre-charging unit 806 in fig. 7, which is only for convenience of description, and not limiting the scope of the present application, those skilled in the art should understand that the pre-charging circuit and the amplifying circuit are used to implement different functions, and the pre-charging circuit is operated and the amplifying circuit is not operated in the pre-charging stage, and the pre-charging circuit is not operated and the amplifying circuit is operated in the data reading stage, so as to amplify the global data signal.

With continued reference to fig. 7, in some of these embodiments, the second circuit 800 further includes a pulse width modulation unit 810. The pulse width adjusting unit 810 is respectively connected to the input unit 802 and the reference unit 804, and is configured to adjust the read enable signal RdEn according to the precharge enable signal EQ to generate an enable adjustment signal, and the input unit 802 and the reference unit 804 are respectively configured to generate corresponding data signals in response to the enable adjustment signal. That is, the input unit 802 controls the data signal of the first node YIONloc in response to the enable adjustment signal, and the reference unit 804 controls the data signal of the second node YIOloc in response to the enable adjustment signal. Fig. 8 is a signal timing diagram of the pulse width modulation unit of the embodiment of fig. 7, and referring to fig. 8, the pulse width of the enable adjustment signal is smaller than the pulse width of the read enable signal RdEn and smaller than the width of the precharge enable signal EQ enable disable. In the present embodiment, a signal having a pulse width of less than 500ps can be generated based on the wider read enable signal RdEn and the inverted precharge enable signal EQN, thereby realizing a more accurate signal generation function.

With continued reference to fig. 7, in one embodiment, the input unit 802 includes a first read transistor T01. The control terminal of the first read transistor T01 is configured to receive the global data signal YIO, the first terminal of the first read transistor T01 is connected to the pulse width modulation unit 810, and the second terminal of the first read transistor T01 is connected to the first node YIONloc. When the global data signal YIO is at a high level, the first read transistor T01 is turned on, and the first read transistor T01 transmits an enable adjustment signal to the first node YIONloc, wherein the level state of the enable adjustment signal can be adjusted by the switching structure in the pulse width adjusting unit 810, thereby controlling the signal transmitted to the first node YIONloc. When global data signal YIO is low, first read transistor T01 is turned off and the level state of first node YIONloc remains unchanged. Based on the above structure, the input unit 802 can transmit the data information carried by the global data signal YIO to the first node YIONloc.

Further, the input unit 802 further includes a second read transistor T02. The control terminal of the second read transistor T02 is configured to receive the global data signal YIO, the first terminal of the second read transistor T02 is connected to the first terminal of the first read transistor T01, and the second terminal of the second read transistor T02 is connected to the second terminal of the first read transistor T01. Still further, the input unit 802 further includes a first switch 8021. The first switch 8021 includes two first terminals and a second terminal, one first terminal of the first switch 8021 is configured to receive the global data signal YIO, the other first terminal of the first switch 8021 is grounded, the second terminal of the first switch 8021 is connected to the control terminal of the second read transistor T02, and the first switch 8021 is configured to selectively transmit the global data signal YIO or a ground signal to the control terminal of the second read transistor T02. If the first switch 8021 selects the ground path, the second reading transistor T02 is always turned off. If the first switch 8021 selects the global data signal YIO, the second read transistor T02 is turned on or off according to the level state of the global data signal YIO, that is, the second read transistor T02 and the first read transistor T01 are synchronous and correspond to each other, and transmit the same enable adjustment signal, so that the response speed to the global data signal YIO can be effectively improved. It is understood that the semiconductor memory includes a plurality of second circuits 800, and the signal transmission speeds of the different second circuits 800 are not identical due to the difference of the process steps. Therefore, by providing the first switch 8021, the response speed of the second circuit 800 can be flexibly adjusted, and the reading performance of the semiconductor memory can be improved.

In one embodiment, the input unit 802 further includes a first control circuit 8022 and a third read transistor T03. The first control circuit 8022 is configured to generate an adjustment control signal according to the global data signal YIO and the first control signal. Wherein the memory may include a plurality of fuses to configure the memory, and in some examples, the first control signal may be a signal correspondingly generated according to fuse states. In other examples, the first control signal may also be a signal input from outside the memory. The control terminal of the third read transistor T03 is connected to the first control circuit 8022, and is configured to receive the adjustment control signal, the first terminal of the third read transistor T03 is connected to the first terminal of the first read transistor T01, and the second terminal of the third read transistor T03 is connected to the second terminal of the first read transistor T01. Specifically, fig. 9 is a schematic structural diagram of a first control circuit according to an embodiment, referring to fig. 9, the first control circuit 8022 includes a pull-up transistor and a pull-down transistor, a first terminal of the pull-up transistor is connected to a power terminal, a second terminal of the pull-up transistor is connected to a first terminal of the pull-down transistor, a second terminal of the pull-down transistor is grounded, and the two transistors are enabled differently. The two transistors respectively receive the same first control signal and output corresponding adjusting control signals under the control of the first control signal. As shown in fig. 9, if the first control signal is a time-varying signal, the first control circuit 8022 also outputs different adjustment control signals YIO _opt1 and YIO _opt in a time-sharing manner through one output terminal. It is understood that the number of the first control signals corresponds to the number of the third reading transistors T03 in the input unit 802, and the level state of the first control signals may also be set according to the sensitivity requirement. In this embodiment, the sensitivity characteristic of the input unit 802 can be controlled more flexibly by using a plurality of first control signals, and defects can be fabricated by using a clamping process, thereby improving the reliability of the semiconductor memory.

With continued reference to fig. 7, in one embodiment, the reference cell 804 includes a fourth read transistor T04. The control terminal of the fourth read transistor T04 is configured to receive the reference data signal Ref, the first terminal of the fourth read transistor T04 is configured to receive the enable adjustment signal, and the second terminal of the fourth read transistor T04 is connected to the second node YIOloc, so as to adjust the voltage of the second node YIOloc according to the reference data signal Ref.

Further, the reference cell 804 also includes a second control circuit 8041 and a fifth read transistor T05. The second control circuit 8041 is configured to generate a reference control signal according to the second control signal. The control terminal of the fifth read transistor T05 is connected to the second control circuit 8041 for receiving the reference control signal, the first terminal of the fifth read transistor T05 is connected to the first terminal of the fourth read transistor T04, and the second terminal of the fifth read transistor T05 is connected to the second terminal of the fourth read transistor T04. Specifically, fig. 10 is a schematic diagram of a second control circuit according to an embodiment, referring to fig. 10, the second control circuit 8041 includes a pull-up transistor and a pull-down transistor, a first terminal of the pull-up transistor is connected to a power source terminal, a second terminal of the pull-up transistor is connected to a first terminal of the pull-down transistor, a second terminal of the pull-down transistor is grounded, and the two transistors are enabled differently. The two transistors respectively receive the same second control signal and output corresponding adjusting control signals under the control of the second control signal. As shown in fig. 10, if the second control signal is a signal with time-varying, the second control circuit 8041 also outputs different adjustment control signals ref_opt2, ref_opt1 and ref_opt in a time-varying manner through one output terminal. It is understood that the number of the second control signals corresponds to the number of the fourth reading transistors T04 in the reference unit 804, and the level states of the second control signals can also be set according to the sensitivity requirement. In this embodiment, the sensitivity characteristic of the reference unit 804 can be controlled more flexibly by using a plurality of second control signals, and defects can be fabricated by using a clamping process, so that the reliability of the semiconductor memory is improved.

Fig. 11 is one of schematic structural diagrams of an output unit according to an embodiment, referring to fig. 11, in this embodiment, the output unit 808 includes two signal output circuits. The two signal output circuits are respectively a first output circuit 8081 and a second output circuit 8082, and each signal output circuit respectively comprises a first input end, a second input end and an output end. A first input terminal of the first output circuit 8081 is connected to the first node YIONloc, a first input terminal of the second output circuit 8082 is connected to the second node YIOloc, an output terminal of the first output circuit 8081 is connected to a second input terminal of the second output circuit 8082, and a second input terminal of the first output circuit 8081 is connected to an output terminal of the second output circuit 8082. The node of the output end of the first output circuit 8081 connected to the second input end of the second output circuit 8082 is used for outputting the readout Data signal Data, and the node of the second input end of the first output circuit 8081 connected to the output end of the second output circuit 8082 is used for outputting an inverted signal of the readout Data signal Data.

Specifically, the signal output circuit includes an eighth read transistor T08, a ninth read transistor T09, a tenth read transistor T10, and an eleventh read transistor T11. The control terminal of the eighth read transistor T08 is used as the first input terminal of the signal output circuit, the first terminal of the eighth read transistor T08 is connected to the high level, and the second terminal of the eighth read transistor T08 is used as the output terminal of the signal output circuit. The control terminal of the ninth read transistor T09 is connected to the control terminal of the eighth read transistor T08, and the first terminal of the ninth read transistor T09 is connected to the second terminal of the eighth read transistor T08. The control terminal of the tenth read transistor T10 serves as a second input terminal of the signal output circuit, the first terminal of the tenth read transistor T10 is connected to the second terminal of the eighth read transistor T08, and the second terminal of the tenth read transistor T10 is grounded. The control terminal of the eleventh read transistor T11 is connected to the control terminal of the tenth read transistor T10, the first terminal of the eleventh read transistor T11 is connected to the high level, and the second terminal of the eleventh read transistor T11 is connected to the second terminal of the eighth read transistor T08.

The operation principle of the output unit 808 will be described based on the embodiment of fig. 11. If the level state of the first node YIONloc is high, the level state of the corresponding second node YIOloc is opposite, i.e., the level state of the second node YIOloc is low. The low level of the second node YIOloc turns on the eighth transistor in the second output circuit 8082, thereby pulling down the inverted signal of the readout Data signal Data to the low level, and correspondingly, the readout Data signal Data is the high level. If the level state of the first node YIONloc is low, the level state of the corresponding second node YIOloc is opposite, i.e., the level state of the second node YIOloc is high. The low level of the first node YIONloc turns on the eighth transistor in the first output circuit 8081, thereby pulling the readout Data signal Data high, and accordingly, the inverted signal of the readout Data signal Data is low.

Fig. 12 is a second schematic diagram of the output unit according to an embodiment, referring to fig. 12, in this embodiment, the output unit 808 further includes a first reset transistor T12 and a second reset transistor T13. The control terminal of the first reset transistor T12 is configured to receive an externally input reset signal, a first terminal of the first reset transistor T12 is connected to a high level, and a second terminal of the first reset transistor T12 is connected to a second terminal of the eighth read transistor. The control end of the second reset transistor T13 is configured to receive the reset signal, the first end of the second reset transistor T13 is connected to the second end of the tenth read transistor, and the second end of the second reset transistor T13 is grounded. By providing the reset transistor, the read Data signal Data line can be reset before Data read, thereby improving the reliability of Data read. Specifically, when the reset signal is at a low level, the first reset transistor T12 is turned on, thereby pulling up the voltage on the readout Data signal Data line to a high level.

In one embodiment, the number of read transistors connected to the first node YIONloc is the same as the number of read transistors connected to the second node YIOloc. For example, based on the second circuit of the embodiment of fig. 7, a third read transistor T03 may be further disposed in the input unit 802, such that the first node YIONloc is connected to four read transistors and the second node YIOloc is also connected to four read transistors. Through the above arrangement, the load capacitances on the first node YIONloc and the second node YIOloc can be equal, so that the charge conditions of the two nodes in the initial state are the same, and balance between the input unit 802 and the reference unit 804 is improved, so as to achieve more accurate reading of the global data signal YIO.

Fig. 13 is a second schematic diagram of a partial structure of a second circuit according to an embodiment, referring to fig. 13, in this embodiment, the input unit 802, the pre-charge unit 806 and the pulse width adjustment unit 810 are the same as those of the embodiment of fig. 7, and the first control circuit 8022 and the output unit 808 of this embodiment may also correspond to those of fig. 9 to 12, and will not be described again here. The reference cell 804 of the present embodiment further includes a sixth read transistor T06 and a second switch 8042. The control terminal of the sixth read transistor T06 is configured to receive the reference data signal Ref, the first terminal of the sixth read transistor T06 is configured to receive the enable adjustment signal, the second terminal of the sixth read transistor T06 is connected to the first terminal of the fourth read transistor T04, and the fourth read transistor T04 receives the enable adjustment signal via the sixth read transistor T06. Two ends of the second switch 8042 are respectively connected to the first end of the sixth read transistor T06 and the second end of the sixth read transistor T06 in a one-to-one correspondence.

Specifically, when the second switch 8042 is closed, the sixth read transistor T06 is shorted, the second terminal of the fourth read transistor T04 may be understood as being directly connected to the pulse width modulation unit 810, and the enable adjustment signal output from the pulse width modulation unit 810 may be rapidly transmitted to the fourth read transistor T04. When the second switch 8042 is turned on, the sixth read transistor T06 needs to be turned on or off in response to the reference data signal Ref, and if the reference data signal Ref controls the fourth read transistor T04 and the sixth read transistor T06 to be turned on, the enable adjustment signal needs to be transmitted to the fourth read transistor T04 through the sixth read transistor T06, so as to change the transmission speed of the enable adjustment signal. It is understood that the semiconductor memory includes a plurality of second circuits, and the signal transmission speeds of the different second circuits are not identical due to the difference of the process steps. Therefore, by providing the second switch 8042, the response speed of the second circuit can be flexibly adjusted, and the reading performance of the semiconductor memory can be improved.

With continued reference to fig. 13, in one embodiment, the reference cell 804 further includes a second control circuit 8041 and a seventh read transistor T07. The second control circuit 8041 is configured to generate a reference control signal according to the second control signal, and it can be appreciated that the second control circuit 8041 in this embodiment can refer to the embodiment of fig. 10, and a detailed description thereof is omitted herein. The control terminal of the seventh read transistor T07 is connected to the second control circuit 8041, the first terminal of the seventh read transistor T07 is connected to the first terminal of the sixth read transistor T06, and the second terminal of the seventh read transistor T07 is connected to the second terminal of the sixth read transistor T06. In this embodiment, the second control signal is used to control the sensitivity characteristic of the reference unit 804 more flexibly, and to control the manufacturing defect of the process, so as to improve the reliability of the semiconductor memory.

The embodiment of the application also provides a data processing circuit shown in fig. 1, which comprises: the data transmission circuit 10 and the check generating circuit 20 as described above, the check generating circuit 20 is connected to the check writing circuit 200, and is configured to obtain data to be written, generate corresponding check data according to the data to be written, and transmit the check data to the check writing circuit 200. It can be appreciated that the data transmission circuit 10 of the present embodiment can refer to the foregoing embodiments, and will not be described herein, and based on the foregoing data transmission circuit 10, the present application provides a data processing circuit with a relatively high processing speed and a relatively high transmission speed.

The embodiment of the application also provides a memory, which comprises: a data storage unit 400, a verification storage unit 500 and a data processing circuit as described above. It can be understood that the data processing circuit of the present embodiment can refer to the foregoing embodiment, and will not be described herein.

The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples merely represent a few implementations of the present examples, which are described in more detail and are not to be construed as limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that various modifications and improvements can be made to the present application without departing from the spirit of the embodiments of the application. Accordingly, the protection scope of the patent of the embodiments of the application shall be subject to the appended claims.

Claims

1. A data transmission circuit, comprising:

The data writing circuit is used for writing the data to be written into the global data line, and the data writing circuit is used for writing the data to be written into the global data line;

the first circuit is used for responding to a precharge enabling signal, generating a pull-up enabling signal, and enabling the enabled pull-up enabling signal to control the first pull-up circuit to output a global data signal; the first circuit is further used for responding to a write enabling signal, generating a pull-up enabling signal and a pull-down enabling signal according to data to be written, transmitting the global data signal to a global data line, enabling the effective pull-down enabling signal to control the first pull-down circuit to output the global data signal, and enabling the pull-up enabling signal and the pull-down enabling signal to be effective in a time-sharing mode;

2. The data transmission circuit of claim 1, wherein the electrical parameters of the corresponding devices of the first pull-down circuit in the data write circuit and the verification write circuit are not identical, so that the driving capability of the first pull-down circuit in the verification write circuit is stronger than the driving capability of the first pull-down circuit in the data write circuit.

3. The data transmission circuit of claim 2, wherein,

The first pull-up circuit comprises a first pull-up transistor, the first pull-up transistor is conducted at a low level, the control end of the first pull-up transistor is used for receiving an inverted signal of the data to be written, and the first end of the first pull-up transistor is connected with a power supply voltage end;

The first pull-down circuit comprises a first pull-down transistor, the first pull-down transistor is conducted at a high level, a control end of the first pull-down transistor is used for receiving an inverted signal of the data to be written, a first end of the first pull-down transistor is connected with a grounding end, and a second end of the first pull-down transistor is connected with a second end of the first pull-up transistor;

4. The data transmission circuit of claim 3, wherein a channel width to length ratio of a first pull-up transistor in the verify write circuit is equal to a channel width to length ratio of a first pull-up transistor in the data write circuit.

5. The data transmission circuit of claim 3, wherein a threshold voltage of a first pull-up transistor in the verify write circuit is equal to a threshold voltage of a first pull-up transistor in the verify write circuit.

6. The data transmission circuit of claim 3, wherein a threshold voltage of a first pull-down transistor in the verify write circuit is less than a threshold voltage of a first pull-down transistor in the verify write circuit.

7. A data transfer circuit according to claim 3, wherein the data transfer circuit is configured with a precharge phase in which a precharge enable signal is active and a data write phase in which a write enable signal is active, the first circuit further comprising:

A logic operation unit connected with the first pull-up transistor and the first pull-down transistor respectively, and used for responding to a write enable signal in the data writing stage to generate an inversion signal of data to be written;

And the NOT gate circuit is connected with the logic operation unit and is used for receiving a precharge enabling signal and controlling the logic operation unit to output a low-level signal in the precharge stage.

8. The data transmission circuit according to claim 7, wherein the logic operation unit includes:

The first input end of the first NOR gate circuit is connected with the output end of the AND gate circuit, the second input end of the first NOR gate circuit is connected with the output end of the NOR gate circuit, the precharge enable signal is used for switching the data transmission circuit to a precharge stage or a data writing stage, and the output end of the first NOR gate circuit is connected with the control end of the first pull-up transistor.

9. The data transmission circuit of claim 8, wherein the output of the first nor gate is further coupled to the control terminal of the first pull-down transistor.

10. The data transmission circuit of claim 8, wherein the logic operation unit further comprises:

a first input end of the NAND gate circuit is used for receiving a precharge enable signal, and a second input end of the NAND gate circuit is used for receiving a write enable signal;

the first input end of the second NOR gate circuit is used for receiving data to be written, the second input end of the second NOR gate circuit is connected with the output end of the NAND gate circuit, and the output end of the second NOR gate circuit is connected with the control end of the first pull-down circuit.

11. The data transfer circuit of claim 1, wherein the data write circuit and the verify write circuit each transfer a global data signal to a corresponding global data line in response to a same write enable signal.

12. The data transmission circuit of claim 1, further comprising:

the data reading circuit is used for acquiring stored data to be read from a global data line connected with the data storage unit so as to read the data to be read;

The verification reading circuit is used for acquiring stored verification data from a global data line connected with the verification storage unit so as to read the stored verification data, wherein the stored verification data corresponds to the stored data to be read;

wherein the driving capability of the verification reading circuit is equal to the driving capability of the data reading circuit.

13. The data transmission circuit of claim 12, wherein the circuit structures of the data reading circuit and the verification reading circuit are both second circuits, and the electrical parameters of the corresponding devices in the data reading circuit and the verification reading circuit are the same, so that the driving capability of the verification reading circuit is equal to the driving capability of the data reading circuit.

14. The data transmission circuit of claim 13, wherein the global data line is further configured to transmit a read signal having a same level state as the data to be read, the second circuit comprising:

A reference unit for receiving a reference data signal in response to the read enable signal;

15. A data processing circuit, comprising:

a data transmission circuit as claimed in any one of claims 1 to 14;

16. A memory, comprising: a data storage unit, a verification storage unit and a data processing circuit as claimed in claim 15.