CN112131037A

CN112131037A - Memory device

Info

Publication number: CN112131037A
Application number: CN201910547971.0A
Authority: CN
Inventors: 中冈裕司
Original assignee: Winbond Electronics Corp
Current assignee: Winbond Electronics Corp
Priority date: 2019-06-24
Filing date: 2019-06-24
Publication date: 2020-12-25
Anticipated expiration: 2039-06-24
Also published as: CN112131037B

Abstract

The invention provides a memory device. The data read-write circuit is used for accessing data of the memory cell array. The correction data read-write circuit is used for accessing the correction data of the correction data memory cell array. The syndrome arithmetic circuit generates an error decoding signal based on the data received from the data read-write circuit and the correction data received from the correction data read-write circuit. In the same reading period of reading data, the data reading and writing circuit corrects the error bit in the data according to the error decoding signal and outputs correct data and a correction bit signal. The syndrome arithmetic circuit also outputs a correction data writing signal to the correction data read-write circuit according to the correction bit signal to update the correction data in the correction data memory cell array. The data read-write circuit also writes the corrected data back to the memory cell array.

Description

Memory device

Technical Field

The present invention relates to a memory device, and more particularly, to a memory device having error checking and error correcting functions.

Background

With the advance of technology, the demand of consumers for storage media has increased rapidly, and among them, Dynamic Random Access Memory (DRAM) has the advantages of simple structure, high density and low cost, and is widely applied to various electronic devices. In order to improve the data reliability of the DRAM, some DRAMs have an Error-correcting code (ECC) memory to detect an Error bit in the stored data and correct the Error bit. At present, the DRAM mainly adopts a Single Error correction (Single Error correction) technique, but the Single Error correction technique can only correct one bit of Error at a time. If the stored data has errors of 2 bits or more at the same time, the error correction function of the ECC circuit is disabled. However, the DRAM may generate an error bit due to a Soft error (Soft error) caused by high temperature, refresh, and the like. If the error bit cannot be corrected in time, the data reliability of the memory may be reduced by accumulating two error bits in the stored data. Therefore, how to correct the stored data in time to avoid accumulating more than 2 error bits and maintain the data correctness of the DRAM becomes a problem to be overcome.

Disclosure of Invention

The invention provides a memory device, which can correct error bits and update stored data and correction data for error check correction in real time in a data reading period.

A memory device of the present invention includes: a data read-write circuit, a correction data read-write circuit and a syndrome arithmetic circuit. The data read-write circuit is coupled to the memory cell array and used for accessing data of the memory cell array. The correction data read-write circuit is coupled with the correction data memory cell array and used for accessing the correction data of the correction data memory cell array. The check sub-operation circuit generates an error decoding signal according to the data received from the data read-write circuit and the correction data received from the correction data read-write circuit, wherein in the same read cycle of the read data, the data read-write circuit corrects the error bits in the data according to the error decoding signal and outputs correct data and a correction bit signal, wherein the data read-write circuit writes the corrected data back to the memory cell array, and wherein the check sub-operation circuit further outputs a correction data write signal to the correction data read-write circuit according to the correction bit signal to update the correction data in the correction data memory cell array.

Based on the above, the memory device of the present invention can read data from the memory cell array in one read cycle and complete the checking and correcting. When an error bit is found in the data, the memory device of the invention can immediately correct the error in the same read cycle to output correct data, and correspondingly write the corrected data back to the memory cell array and the updated corrected data back to the corrected data memory cell array in a continuous period. Therefore, the memory device can improve the reliability of data.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a block diagram of a memory device according to an embodiment of the invention;

FIG. 2 is a block diagram of a data read/write circuit according to an embodiment of the invention;

FIG. 3A is a circuit diagram of a data reading circuit according to an embodiment of the invention;

FIG. 3B is a waveform diagram illustrating a read operation of a memory device according to an embodiment of the invention;

FIG. 4 is a circuit diagram of a data correction circuit according to an embodiment of the present invention;

FIG. 5A is a circuit diagram of a data write circuit according to an embodiment of the invention;

FIG. 5B is a circuit diagram of a control signal generating circuit of a data writing circuit according to an embodiment of the present invention;

FIG. 6A is a waveform diagram illustrating a write operation of a memory device without error bits being found according to an embodiment of the invention;

FIG. 6B is a waveform diagram illustrating a write operation of a memory device with error bit correction according to an embodiment of the invention;

FIG. 7A is a circuit diagram of a syndrome generating circuit according to an embodiment of the present invention;

FIG. 7B is a circuit diagram of an internal operation circuit of the syndrome generating circuit according to an embodiment of the present invention;

FIG. 7C is a circuit diagram of a syndrome control signal generating circuit of the syndrome generating circuit according to an embodiment of the present invention;

FIG. 8 is a circuit diagram of a correction data read/write circuit according to an embodiment of the invention;

FIG. 9 is a circuit diagram of a correction data writing circuit according to an embodiment of the invention.

Description of the reference numerals

100: memory device

110: memory cell array

120: correction data memory cell array

130: data read-write circuit

140: correction data read-write circuit

150: syndrome generating circuit

160: syndrome decoding circuit

170: syndrome arithmetic circuit

210: data reading circuit

220: data correction circuit

230: data write circuit

310: reading switch

320: pre-charging circuit

330: amplifying circuit

332: amplifier with a high-frequency amplifier

410: correction switch

420: read bit latch

430: correction circuit

440. 540: output circuit

442: latch device

510. 520, the method comprises the following steps: write-in switch

530: write bit latch

550: control signal generating circuit

610: signal generating circuit

710: internal arithmetic circuit

720: input circuit

730: syndrome control signal generating circuit

810: correction data reading circuit

820: correction data write circuit

AD. ADi: reading data

ADiT: reading data signals

ADiN: inverted read data signal

BL: bit line

BLN: complementary bit line

CS: correcting bit signals

DE: read enable signal

DM: write mask signal

DWm: write mask select signal

DWmB: inverted write mask select signal

EiT: positive latch bit signal

EiN: anti-latch bit signal

GND: ground voltage

LAR: read latch signal

LAWIN: initial write latch signal

LAWm: first write latch signal

LAWmB: inverting the first write latch signal

LDWm: second write latch signal

LDWmB: inverted second write latch signal

LAWPT: verify write latch signal

LAWPB: inverted verify write latch signal

MD: data of

MDiT: data signal

MDiN: inverted data signal

NAND 1-NAND 5: NAND gate

NOR 1-NOR 3: NOR gate

And NS: correction data write signal

INV, INV 1-INV 21: inverter with a capacitor having a capacitor element

OE: output enable signal

PB: pre-charge signal

PM: correction data

PS: correcting read signal

RWB, RWBI: data output signal

RD, RDi: reading bit signals

SY: syndrome signal

SD, SDi: error decoding signal

And (3) SDE: decoding control signals

TG, TG 1-TG 9: transmission gate

T31, T32, TP 1-TP 10: p-type transistor

T33, T34, T35, TN1 to TN 3: n-type transistor

VDD: voltage source

VSS: low voltage

WE: write enable signal

WED: write data control signal

WEDB: inverted write data control signal

WEm: write data select signal

WEmB: inverted write data select signal

Detailed Description

FIG. 1 is a block diagram of a memory device according to an embodiment of the invention. Referring to fig. 1, the memory device 100 includes a memory cell array 110, a corrected data memory cell array 120, a data read/write circuit 130, a corrected data read/write circuit 140, and a syndrome operation circuit 170, wherein the syndrome operation circuit 170 includes a syndrome generation circuit 150 and a syndrome decoding circuit 160. The data read/write circuit 130 is coupled to the memory cell array 110 to access the data MD in the memory cell array 110. The correction data read/write circuit 140 is coupled to the correction data memory cell array 120 to access the correction data PM of the correction data memory cell array 120. The correction data PM is an error check and correction code for checking and correcting the data MD, and is generated by performing an ECC encoding process such as a Hamming code (Hamming code) on the data MD. The number of bits of the correction data PM depends on the number of bits of the data MD. In the present embodiment, the size of the data MD is 64 bits as an example, and the size of the correction data PM is set to 7 bits correspondingly, but the size of the data MD and the size of the correction data PM are not limited in the present invention.

The syndrome arithmetic circuit 170 generates an error decoding signal SD based on the data MD received from the data read/write circuit 130 (the data read/write circuit 130 outputs a read bit signal RD after reading the data MD) and the correction data PM received from the correction data read/write circuit 140 (the correction data read/write circuit 140 outputs a correction read signal PS after reading the correction data PM), wherein the data read/write circuit 130 corrects an error bit in the data MD based on the error decoding signal SD and outputs correct data (i.e., a data output signal RWB) and a correction bit signal CS in the same read cycle of the read data MD. The data read/write circuit 130 writes the corrected data back to the memory cell array 110, and the syndrome arithmetic circuit 170 further outputs a correction data write signal NS to the correction data read/write circuit 140 according to the correction bit signal CS to update the correction data PM in the correction data memory cell array 120.

In other words, in the embodiment, after the data MD and the correction data PM are read, whether there is an error bit in the data MD can be checked through Syndrome encoding (Syndrome encoding) and Syndrome decoding (Syndrome decoding) of the Syndrome arithmetic circuit 170. If there is an error bit, the data read/write circuit 130 can immediately correct the error bit according to the error decoding signal SD in the same read cycle to output the correct data output signal RWB, and can also output the correction bit signal CS to the syndrome arithmetic circuit 170 to enable the correction data read/write circuit 140 to update the correction data PM. In particular, between reading the data MD and outputting the correct data output signal RWB, the memory device 100 does not need to select the memory cells of the memory cell array 110 again, and can complete the above operations in the same read cycle and also update the correction data PM.

The circuit structure and the implementation of the present embodiment are further described below. FIG. 2 is a block diagram of a data read/write circuit according to an embodiment of the invention. Referring to fig. 2, the data read/write circuit 130 includes a data read circuit 210, a data calibration circuit 220 and a data write circuit 230. The data reading circuit 210 is coupled to the memory cell array 110 and is configured to read data MD from the memory cell array 110 to generate read data AD and a corresponding read bit signal RD. The data calibration circuit 220 is coupled to the data reading circuit 210 and the syndrome decoding circuit 160 of the syndrome computing circuit 170, and is used for latching the read data AD in the reading cycle and calibrating the error bits of the read data AD according to the error decoding signal SD to generate a correct data output signal RWB and a corrected bit signal CS, wherein the data output signal RWB is the output result of the data reading and writing circuit 130 after reading and calibrating the data MD. The data write circuit 230 is coupled to the data correction circuit 220 and the memory cell array 110, and is configured to use the corrected bit signal CS to replace the data output signal RWB corresponding to the error bit to write the correct data MD back to the memory cell array 110.

Referring to fig. 1 again, the syndrome arithmetic circuit 170 includes a syndrome generating circuit 150 and a syndrome decoding circuit 160. The syndrome generating circuit 150 is coupled to the data reading/writing circuit 130 and the correction data reading/writing circuit 140, and selectively receives an output signal of the data reading circuit 210 or the data correcting circuit 220 according to a reading operation or a writing operation to generate a correction data writing signal NS. More specifically, the syndrome generating circuit 150 generates the correction data writing signal NS according to the read bit signal RD when the data read/write circuit 130 performs the read operation, and the syndrome generating circuit 150 generates the correction data writing signal NS according to the correction bit signal CS or the data output signal RWB when the data read/write circuit 130 performs the write operation.

The syndrome generating circuit 150 compares the correction data writing signal NS with the corresponding correction data PM (the correction data PM is read by the correction data reading/writing circuit 140 to provide the correction reading signal PS to the syndrome generating circuit 150) to generate the syndrome signal SY. The syndrome decoding circuit 160 is coupled to the syndrome generating circuit 150 for decoding the syndrome signal SY to generate an error decoded signal SD. The data read/write circuit 130 corrects the error bits in the data MD based on the error decoding signal SD.

Next, a specific embodiment of the data read/write circuit 130 will be described. FIG. 3A is a circuit diagram of a data reading circuit according to an embodiment of the invention, and FIG. 3B is a waveform diagram of a read operation of a memory device according to an embodiment of the invention. Fig. 4 is a circuit diagram of a data correction circuit according to an embodiment of the invention, fig. 5A is a circuit diagram of a data writing circuit according to an embodiment of the invention, and fig. 5B is a circuit diagram of a control signal generating circuit of the data writing circuit according to an embodiment of the invention. Please refer to fig. 3A to fig. 5B with fig. 1 and fig. 2, to specifically describe the implementation details of the data read/write circuit 130.

In fig. 3A, the data reading circuit 210 includes a read switch 310, a precharge circuit 320 and an amplifying circuit 330. The input terminal of the read switch 310 receives data MD from the memory cell array 110 and is controlled by the read enable signal DE to be turned on or off. The precharge circuit 320 is coupled to the input terminal of the read switch 310 and is controlled by a precharge signal PB to perform a precharge operation on the input terminal of the read switch 310. The input terminal of the amplifying circuit 330 is coupled to the output terminal of the read switch 310, and is controlled by the read enable signal DE to generate the read data AD and generate the corresponding read bit signal RD.

Specifically, the sense amplifiers in the memory cell array 110 output the data MD stored in the memory cells by Differential signals (Differential signals), so the data MD includes a Differential signal of a data signal MDiT and an inverted data signal MDiN, where the data MD is 64 bits, MDi represents one bit of the data MD in this specification, and i is an integer from 0 to 63 (i is 0,1,2, …,63), such as MD0, MD1, …, and MD 63. Similarly, the read data AD is also a differential signal including the read data signal ADiT and the inverted read data signal ADiN. For example, the read bit signal RDi, the data output signal RWBi, and the correction bit signal CSi represent corresponding bits in the read bit signal RD, the data output signal RWB, and the correction bit signal CS, and so on.

In the read switch 310, the transmission gate TG1 is coupled to the bit line BL for receiving the data signal MDiT, the transmission gate TG2 is coupled to the complementary bit line BLN for receiving the inverted data signal MDiN, and the transmission gate TG1 and the transmission gate TG2 are controlled by the read enable signal DE. The input terminal of the inverter INV1 in fig. 3A receives the read enable signal DE, and the output terminal thereof is commonly coupled to one of the control terminals of the transmission gate TG1 and the transmission gate TG2 (e.g., the control terminals of the N-type transistors in the transmission gate TG1 and the transmission gate TG 2). The input end of the inverter INV2 is coupled to the output end of the inverter INV1, and the output end thereof is commonly coupled to the other control ends of the transmission gate TG1 and the transmission gate TG2 (for example, the control ends of the P-type transistors in the transmission gate TG1 and the transmission gate TG 2).

In the precharge circuit 320, the inverter INV3 receives the precharge signal PB. The P-type transistor TP1 has a first terminal coupled to the power voltage VDD, a control terminal coupled to the output terminal of the inverter INV3, and a second terminal coupled to the bit line BL. The P-type transistor TP2 has a first terminal coupled to the power voltage VDD, a control terminal coupled to the output terminal of the inverter INV3, and a second terminal coupled to the complementary bit line BLN. The P-type transistor TP3 is coupled between the second terminal of the P-type transistor TP1 and the second terminal of the P-type transistor TP2, and its control terminal is coupled to the output terminal of the inverter INV 3.

In the amplifying circuit 330, an amplifier 332 is coupled to the read switch 310 to receive the data signal MDiT and the inverted data signal MDiN and correspondingly output the read data signal ADiT and the inverted read data signal ADiN. The inverter INV4 receives the inverted read data signal ADiN to output the read bit signal RDi.

In the present embodiment, the amplifier 332 includes P-type transistors T31-T32 and N-type transistors T33-T35. The P-type transistor T31 and the N-type transistor T33 are serially connected between the voltage source VDD and the first terminal of the N-type transistor T35, the P-type transistor T32 and the N-type transistor T34 are also serially connected between the voltage source VDD and the first terminal of the N-type transistor T35, wherein the P-type transistor T31 and the control terminal of the N-type transistor T33 are commonly coupled to the first terminal of the N-type transistor T34, and the P-type transistor T32 and the control terminal of the N-type transistor T34 are commonly coupled to the first terminal of the N-type transistor T33. The second terminal of the N-type transistor T35 is coupled to the ground voltage GND, and the control terminal thereof is coupled to the read enable signal DE.

In FIG. 3B, the precharge signal PB turns on the read switch 310 to precharge the bit line BL and the complementary bit line BLN before the read operation. When a read operation is to be initiated, the precharge signal PB turns off the read switch 310 to end the precharge operation. At the same time, the selection signal CSL for selecting a memory cell of the memory cell array 110 changes from a Low logic level (Low) to a High logic level (High) to read the data MD of the selected memory cell. Then, the read enable signal DE is switched to a High logic level (High) to turn on the read switch 310 and the start amplifier 332 to amplify the data signal MDiT and the inverted data signal MDiN and output the read data signal ADiT, the inverted read data signal ADiN and the read bit signal RDi. The low voltage VSS in fig. 3B is illustrated as a ground voltage GND.

Referring to fig. 4, the data calibration circuit 220 includes a calibration switch 410, a read bit latch 420, a calibration circuit 430, and an output circuit 440. The input terminal of the calibration switch 410 receives the read data ADi from the data reading circuit 210 and is turned on or off by the read latch signal LAR. The read bit latch 420 is coupled to the calibration switch 410 for latching the read data ADi. The correction circuit 430 is coupled to the read bit latch 420 and receives the corresponding error decoding signal SDi for correcting the bit stored in the read bit latch 420 according to the error decoding signal SDi. The output circuit 440 is coupled to the calibration circuit 430 and the read bit latch 420, and is controlled by the output enable signal OE to output the bit stored in the read bit latch 420 as the data output signal RWBi.

In the calibration switch 410 of fig. 4, the transmission gate TG3 receives the read data signal ADiT from the data reading circuit 210, the transmission gate TG4 receives the inverted read data signal ADiN from the data reading circuit 210, and both the transmission gate TG3 and the transmission gate TG4 are controlled by the read latch signal LAR. The inverter INV5 has an input terminal receiving the read latch signal LAR, and an output terminal commonly coupled to one of the control terminals of the transmission gate TG3 and the transmission gate TG4 for providing an inverted signal of the read latch signal LAR.

The read bit latch 420 includes an inverter INV6 and an inverter INV 7. An input terminal of the inverter INV6 is coupled to the output terminal of the inverter INV7 and receives the read data signal ADiT through the transmission gate TG 3. The input terminal of the inverter INV7 is coupled to the output terminal of the inverter INV6 and receives the inverted read data signal ADiN through the transmission gate TG 4.

In the correction circuit 430, an inverter INV8 receives the error decoding signal SDi, and an inverter INV9 is coupled to the output terminal of the inverter INV6 to output the corrected bit signal CSi. The first terminal of the P-type transistor TP4 is coupled to the power voltage VDD, the second terminal thereof is coupled to the first terminal of the P-type transistor TP5, and the control terminal thereof is coupled to the output terminal of the inverter INV 8. The second terminal of the P-type transistor TP5 is coupled to the input terminal of the inverter INV6, and the control terminal thereof receives the read data signal ADiT. The first terminal of the P-type transistor TP6 is also coupled to the power voltage VDD, the second terminal thereof is coupled to the first terminal of the P-type transistor TP7, and the control terminal thereof is coupled to the output terminal of the inverter INV 8. The second terminal of the P-type transistor TP7 is coupled to the output terminal of the inverter INV6, and the control terminal thereof receives the inverted read data signal ADiN.

In the output circuit 440, an input terminal of the inverter INV10 is coupled to the output enable signal OE. The NAND1 has a first input terminal coupled to the second terminal of the P-type transistor TP5, and a second input terminal receiving the output enable signal OE. The NOR gate NOR1 has a first input terminal coupled to the second terminal of the P-type transistor TP5 and a second input terminal coupled to the output terminal of the inverter INV 10. The first terminal of the P-type transistor TP8 is coupled to the power voltage VDD, the control terminal thereof is coupled to the output terminal of the NAND gate 1, and the first terminal of the N-type transistor TN1 is coupled to the second terminal of the P-type transistor TP8 and provides the corrected data output signal RWBi, the control terminal thereof is coupled to the output terminal of the NOR gate NOR1, and the second terminal thereof is coupled to the ground voltage GND. Output circuit 440 may also include a latch 442 coupled to a first terminal of N-type transistor TN 1. The latch 442 has the same circuit structure as the read bit latch 420, and is formed by two inverters INV connected to each other.

Referring to fig. 3B again, when the read latch signal LAR switches to the high logic level, the read bit latch 420 receives the read data ADi to latch the bit value thereof and generates the corresponding positive latch bit signal EiT and the negative latch bit signal EiN. In fig. 3B, during the high logic level period of the read latch signal LAR, the positive latch bit signal EiT changes to the low logic level, and the negative latch bit signal EiN changes to the high logic level. After the read latch signal LAR is switched to the low logic level, if the ith bit of the data MD is an error bit, the error decoding signal SDi from the syndrome decoding circuit 160 is switched to the high logic level. In the same read cycle, the correction circuit 430 inverts the erroneous bit value latched by the read bit latch 420 according to the error decoding signal SDi, so that the positive latch bit signal EiT and the negative latch bit signal EiN are inverted to correct the error. Finally, the output circuit 440 outputs the correct data output signal RWBi according to the output enable signal OE.

Referring to fig. 5A, the data writing circuit 230 includes an inverter INV11, a write switch 510, a write switch 520, a write bit latch 530, and an output circuit 540. An input of the inverter INV11 receives the corresponding data output signal RWBi. The input terminal of the write switch 510 is coupled to the output terminal of the inverter INV11 and controlled by the first write latch signal LAWm to be turned on or off. The input terminal of the write switch 520 receives the corresponding calibration bit signal CSi and is controlled by the second write latch signal LDWm to be turned on or off. Where m is an integer of 0-7, representing the corresponding Mask bits. Write bit latch 530 is coupled to the output of write switch 510 and the output of write switch 520, and output circuit 540 is coupled to the output of write switch 520 and write bit latch 530. The output circuit 540 is controlled by the write enable signal WE and writes the data output signal RWBi or the calibration bit signal CSi into the memory cell array 110.

Here, the data signal MDiT and the inverted data signal MDiN outputted by the output circuit 540 can be transmitted back to the bit line and the complementary bit line of the memory cell array 110, respectively, to rewrite the data MDi.

In fig. 5A, the write switch 510 is implemented as a transmission gate TG5, and the write switch 520 is implemented as a transmission gate TG 6. Two control terminals of the transmission gate TG5 respectively receive the corresponding first write latch signal LAWm and an inverted signal (i.e., an inverted first write latch signal) LAWmB of the first write latch signal LAWm, and two control terminals of the transmission gate TG6 respectively receive the second write latch signal LDWm and an inverted signal (i.e., an inverted second write latch signal) LDWmB of the second write latch signal LDWm.

The write bit latch 530 includes an inverter INV12 and an inverter INV 13. An input end of the inverter INV12 is coupled to the output end of the inverter INV13, an input end of the inverter INV13 is coupled to the output end of the inverter INV12, and an input end of the inverter INV12 is commonly coupled to the output ends of the transmission gate TG5 and the transmission gate TG 6.

In the output circuit 540, the inverter INV14 is connected in series with the inverter INV15, and the inverter INV14 receives the write enable signal WE. The NAND gate NAND2 has a first input terminal coupled to the output terminal of the inverter INV12, a second input terminal coupled to the output terminal of the inverter INV15, and the NOR gate NOR2 has a first input terminal coupled to the output terminal of the inverter INV12, and a second input terminal coupled to the output terminal of the inverter INV 14. The first terminal of the P-type transistor TP9 is coupled to the power voltage VDD, the control terminal thereof is coupled to the output terminal of the NAND gate 2, and the first terminal of the N-type transistor TN2 is coupled to the second terminal of the P-type transistor TP9 and provides the corresponding data signal MDiT, the control terminal thereof is coupled to the output terminal of the NOR gate NOR2, and the second terminal thereof is coupled to the ground voltage GND. The NAND3 has a first input terminal coupled to the output terminal of the inverter INV13, and a second input terminal coupled to the output terminal of the inverter INV 15. The NOR gate NOR3 has a first input terminal coupled to the output terminal of the inverter INV13, and a second input terminal coupled to the output terminal of the inverter INV 14. The first terminal of the P-type transistor TP10 is coupled to the power voltage VDD, the control terminal thereof is coupled to the output terminal of the NAND gate 3, the first terminal of the N-type transistor TN3 is coupled to the second terminal of the P-type transistor TP10 and provides the corresponding inverted data signal MDiN, the control terminal thereof is coupled to the output terminal of the NOR gate NOR3, and the second terminal thereof is coupled to the ground voltage GND.

Referring to fig. 5B, the data writing circuit 230 further includes a control signal generating circuit 550, and the control signal generating circuit 550 generates the first write latch signal LAWm and the second write latch signal LDWm according to the initial write latch signal LAW and the write mask signal DM. In the present embodiment, the write mask signal DM is an 8-bit signal, and thus the write mask signal DMm is a signal indicating the signal corresponding to the mth bit, and m is an integer from 0 to 7. The control signal generating circuit 550 provides the verify-write latch signal LAWPT and the inverted verify-write latch signal LAWPB to the correction data read/write circuit 140, and provides the corresponding first write latch signal LAWm and second write latch signal LDWm, and their inverted signals to the data write circuit 230.

The control signal generating circuit 550 includes an inverter INV16, an inverter INV17, an inverter INV18, and a signal generating circuit 610. The inverter INV16 is serially connected to the inverter INV17, and the input terminal of the inverter INV16 receives the initial write latch signal LAW, the inverter INV17 outputs the verify write latch signal LAWPT to the calibration data read/write circuit 140, wherein the inverter INV18 receives the initial write latch signal LAW to output the inverse verify write latch signal LAWPB.

It should be noted that, during the read operation, the write enable signal WE and the initial write latch signal LAW are kept at the low logic level.

In the signal generating circuit 610 of FIG. 5B, the output terminal of the inverter INV19 receives the corresponding write mask signal DMm. The NAND4 has a first input terminal receiving the initial write latch signal LAW, a second input terminal coupled to the output terminal of the inverter INV19, and an output terminal outputting a corresponding inverted first write latch signal LAWmB. An input end of the inverter INV20 is coupled to an output end of the NAND gate 4 to output the corresponding first write latch signal LAWm. The NAND gate 5 has a first input terminal receiving the initial write latch signal LAW, a second input terminal receiving the corresponding write mask signal DMm, and an output terminal outputting the corresponding inverted second write latch signal LDWmB. An input end of the inverter INV21 is coupled to the output end of the NAND gate 5 to output the corresponding second write latch signal LDWm.

Fig. 6A is a waveform diagram illustrating a write operation of a memory device without error bits found, and fig. 6B is a waveform diagram illustrating a write operation of a memory device with error bits corrected according to an embodiment of the invention. Please refer to fig. 6A and fig. 6B in combination with the above embodiments.

In fig. 6A, when the memory device 100 is to write data MD and the bits to be written do not need correction, the enabling time of the selection signal CSL for selecting a memory cell (e.g., the time kept at the high logic level) is referred to as the normal write time. During the normal write time, the calibration bit signal CS and the write mask signal DM are always kept at the low logic level, the write switch 510 is turned on and the write switch 520 is turned off, and the data write circuit 230 selects to write the data output signal RWBi into the memory cell array 110.

In fig. 6B, when the memory device 100 finds an error bit in the data MD and the data write circuit 230 is to write the correct data back, the enabling time of the selection signal CSL is referred to as the corrected write time. In the calibration write time, after the read latch signal LAR is switched to the low logic level, the logic level of the error decoding signal SDi corresponding to the error bit position is changed to the high logic level, and correspondingly, the calibration bit signal CSi output by the data calibration circuit 220 is also switched to the high logic level. It should be noted that the syndrome generating circuit 150 also correspondingly outputs the correction data writing signal NS to the correction data reading/writing circuit 140 to update the correction data PM.

Then, the data write circuit 230 performs a write operation, the corresponding first write latch signal LAWm turns off the write switch 510 and the corresponding second write latch signal LDWm turns on the write switch 520, so that the calibration bit signal CSi replaces the data output signal RWBi and is input to the output circuit 540 to write a correct bit value during the enabling time of the write enable signal WE.

In short, when the bit to be written is originally correct, the data writing circuit 230 writes the data output signal RWBi into the memory cell array 110, and when the bit to be written is a position of an erroneous bit, the data writing circuit 230 writes the correction bit signal CSi into the memory cell array 110.

Specifically, in the embodiment, the enabling time of the selection signal CSL may be changed, and the corrected writing time may be longer than the normal writing time. When the memory device 100 detects an error bit, the data read/write circuit 130 and the correction data read/write circuit 140 can write correct data back to the memory cell array 110 and update the correction data PM in the same period of correction by prolonging the enabling time of the selection signal CSL. That is, the selection signal CSL only needs to be enabled once to complete the checking, correcting and updating operations.

The circuit architecture details of the syndrome generating circuit 150 are described next. Fig. 7A is a circuit diagram of a syndrome generating circuit according to an embodiment of the present invention, fig. 7B is a circuit diagram of an internal operation circuit of the syndrome generating circuit according to an embodiment of the present invention, and fig. 7C is a circuit diagram of a syndrome control signal generating circuit of the syndrome generating circuit according to an embodiment of the present invention.

Referring to fig. 7A, the syndrome generating circuit 150 includes an internal operation circuit 710 and a plurality of exclusive-or gates XOR2, wherein the internal operation circuit 710 includes a plurality of transmission gates TG (e.g., transmission gates TG 7-TG 9 in fig. 7B) and a plurality of exclusive-or gates XOR 1.

In fig. 7B, the internal operation circuit 710 selectively provides the data output signal RWB, the correction bit signal CS, or the read bit signal RD to the plurality of exclusive-ors XOR1 by controlling the plurality of transmission gates TG to output the correction data write signal NS. Specifically, the internal operation circuit 710 has a plurality of input circuits 720. Each input circuit 720 may receive a corresponding read bit signal RDi from the data read circuit 210 and a corresponding correction bit signal CSi from the data correction circuit 220 in addition to the corresponding data output signal RWBi. The internal operation circuit 710 controls a plurality of transmission gates TG 7-TG 9 of the input circuit 720 to select one of the read bit signal RD, the data output signal RWB and the correction bit signal CS to be input to a corresponding exclusive-or gate XOR 1.

Specifically, the transmission gate TG7 receives the corresponding read bit signal RDi and is controlled by the write data control signal WED and the inverted signal WEDB of the write data control signal WED, the transmission gate TG8 receives the data output signal RWBi and is controlled by the write data selection signal WEm and the inverted signal WEmB of the write data selection signal WEm, and the transmission gate TG9 receives the correction bit signal CSi and is controlled by the write mask selection signal DWm and the inverted signal DWmB of the write mask selection signal DWm.

When the memory device 100 performs a read operation, the input circuit 720 selectively receives the read bit signal RDi, turns on the transmission gate TG7, and turns off the transmission gate TG8 and the transmission gate TG 9; when the memory device 100 performs a write operation, the input circuit 720 turns off the transmission gate TG7, and turns on the transmission gate TG8 or the transmission gate TG9 according to the write mask signal DM to select the received data output signal RWBi or the correction bit signal CSi.

After the multi-stage exclusive-or XOR1 operation, the internal operation circuit 710 finally outputs the correction data write signal NSj, wherein j is an integer from 0 to 6 because the parity bit of the embodiment is 7 bits, and the correction data write signal NSj represents the signal corresponding to the jth bit in the correction data write signal NS.

In fig. 7A, the plurality of exclusive-or gates XOR2 receive the corresponding correction data write signal NSj from the internal operation circuit 710 and the corresponding correction read signal PSj from the correction data read/write circuit 140. The syndrome generating circuit 150 compares the corrected read signal PS with the corrected data write signal NS to output a syndrome signal SY. The syndrome decoding circuit 160 receives the syndrome signal SY and the decoding control signal SDE and performs a decoding operation on the syndrome signal SY to output an error decoding signal SD to the data correction circuit 220 of the data read/write circuit 130.

The syndrome generating circuit 150 further includes a syndrome control signal generating circuit 730 for generating a control signal of the transmission gate TG. The circuit structure of the syndrome control signal generating circuit 730 in fig. 7C is similar to that of the control signal generating circuit 550 in fig. 5B, and therefore the details of the operation of the syndrome control signal generating circuit 730 are not repeated herein.

The specific circuit structure of the correction data read/write circuit 140 is described next. Fig. 8 is a circuit diagram of a correction data read/write circuit according to an embodiment of the invention, and fig. 9 is a circuit diagram of a correction data write circuit according to an embodiment of the invention.

Referring to fig. 8, the calibration data reading/writing circuit 140 includes a calibration data reading circuit 810 and a calibration data writing circuit 820. The calibration data reading circuit 810 is coupled to the calibration data memory cell array 120 and the syndrome operation circuit 170, and is configured to read the calibration data PM from the calibration data memory cell array 120 to output a calibration read signal PS to the syndrome generation circuit 150 of the syndrome operation circuit 170. The corrected data writing circuit 820 is coupled to the corrected data memory cell array 120 and the syndrome generating circuit 150 of the syndrome computing circuit 170 for writing the corrected data PM into the corrected data memory cell array 120.

When the memory device 100 performs a read operation, the correction data reading circuit 810 may read the correction data PM from the correction data memory cell array 120 to output a correction read signal PS to the syndrome generating circuit 150. The syndrome generating circuit 150 checks whether the read bit signal RD has an erroneous bit based on the corrected read signal PS. If there are erroneous bits, the corresponding erroneous decoding signal SDi changes logic level. In the present embodiment, if the ith bit of the data MD is erroneous, the error decoding signal SDi changes to the high logic level, as shown in fig. 3B.

Referring to fig. 3A, the circuit details of the correction data reading circuit 810 can be obtained by those skilled in the art from the data reading circuit 210, and are not described herein again.

Fig. 9 shows circuit details of the correction data writing circuit 820, which has a circuit structure similar to the data writing circuit 230 of fig. 5A, and those skilled in the art can obtain sufficient suggestions, teachings and embodiments from the data writing circuit 230, and will not be described herein again.

Referring to fig. 6B again, when the syndrome generating circuit 150 detects that the read bit signal RD has an error bit, the data writing circuit 230 corrects the error of the read bit signal RD, and the syndrome generating circuit 150 outputs a new correction data writing signal NS according to the correction bit signal CS for recording the error bit position. The correction data writing circuit 820 writes the new correction data writing signal NS into the correction data memory cell array 120 to update the correction data PM. The correction data PM in fig. 9 is a signal including a difference signal composed of a correction data signal PMjT and an inverted correction data signal PMjN, and j is an integer of 0 to 6, representing a corresponding check bit.

In summary, the memory device of the present invention can read data from the memory cell array and check the data in one read cycle, wherein when an error bit is found in the data, the memory device of the present invention can correct the error and output correct data in the same read cycle. In addition, the memory device of the invention can also output the correction bit signal to the data writing circuit and the syndrome generating circuit at the same time. By extending the enable period of the selection signal, the data write circuit can write the corrected data back to the memory cell array and the syndrome generation circuit can provide a new correction data write signal to the correction data write circuit to update the correction data. Therefore, the selection signal can complete the correction and update of the data only by providing an enabling period for the memory cell to be written once, thereby achieving the effect of checking and correcting errors in real time.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A memory device, comprising:

the data read-write circuit is coupled with the memory cell array and used for accessing the data of the memory cell array;

a correction data read-write circuit coupled to the correction data memory cell array for accessing the correction data of the correction data memory cell array; and

a syndrome arithmetic circuit for generating an error decoding signal based on the data received from the data read-write circuit and the correction data received from the correction data read-write circuit,

in the same reading period of reading the data, the data read-write circuit corrects an error bit in the data according to the error decoding signal and outputs correct data and a corrected bit signal, wherein the data read-write circuit writes the corrected data back to the memory cell array, and the syndrome arithmetic circuit further outputs a corrected data write signal to the corrected data read-write circuit according to the corrected bit signal to update the corrected data in the corrected data memory cell array.

2. The memory device according to claim 1, wherein an enabling time of a selection signal for selecting a memory cell when the corrected data is to be written into the memory cell array is referred to as a corrected writing time, and an enabling time of the selection signal when the data for which the erroneous bit is not found is to be written into the memory cell array is referred to as a normal writing time, wherein the corrected writing time is greater than the normal writing time.

3. The memory device according to claim 1, wherein the data read/write circuit comprises:

a data reading circuit, coupled to the memory cell array, for reading the data from the memory cell array to generate read data and a corresponding read bit signal;

a data correction circuit, coupled to the data reading circuit and the syndrome operation circuit, for latching the read data in the read cycle and correcting an error bit of the read data according to the error decoding signal to generate a data output signal and the corrected bit signal, wherein the data output signal is an output result of the data reading and writing circuit after the data is read and corrected; and

a data write circuit coupled to the data correction circuit and the memory cell array for replacing the data output signal corresponding to the error bit with the corrected bit signal to write the correct data back to the memory cell array.

4. The memory device according to claim 3, wherein the data reading circuit comprises:

a read switch, an input terminal of which receives the data from the memory cell array and is controlled by a read enable signal to be turned on or off;

the pre-charging circuit is coupled with the input end of the reading switch and is controlled by a pre-charging signal to execute a pre-charging action on the input end of the reading switch; and

an amplifying circuit, an input end of which is coupled to the output end of the reading switch, is controlled by the reading enabling signal to generate the reading data and generate the corresponding reading bit signal.

5. The memory device of claim 4,

the read switch includes:

a first transmission gate and a second transmission gate, wherein the first transmission gate is coupled to a bit line for receiving a data signal, the second transmission gate is coupled to a complementary bit line for receiving an inverted data signal, and both the first transmission gate and the second transmission gate are controlled by the read enable signal, wherein the data is a differential signal including the data signal and the inverted data signal; and

a first inverter and a second inverter, wherein an input terminal of the first inverter receives the read enable signal, an output terminal of the first inverter is coupled to one of the control terminals of the first transmission gate and the second transmission gate, an input terminal of the second inverter is coupled to an output terminal of the first inverter, and an output terminal of the second inverter is coupled to the other of the control terminals of the first transmission gate and the second transmission gate;

the pre-charge circuit includes:

a third inverter receiving the precharge signal;

a first P-type transistor having a first terminal coupled to a power voltage, a control terminal coupled to the output terminal of the third inverter, and a second terminal coupled to the bit line;

a second P-type transistor having a first terminal coupled to the power voltage, a control terminal coupled to the output terminal of the third inverter, and a second terminal coupled to the complementary bit line; and

a third P-type transistor coupled between the second terminal of the first P-type transistor and the second terminal of the second P-type transistor, and having a control terminal coupled to the output terminal of the third inverter; and

the amplification circuit includes:

an amplifier coupled to the read switch to receive the data signal and the inverted data signal and correspondingly output a read data signal and an inverted read data signal, wherein the read data is a differential signal including the read data signal and the inverted read data signal; and

a fourth inverter receiving the inverted read data signal to output the read bit signal.

6. The memory device according to claim 3, wherein the data correction circuit comprises:

a correction switch, an input end of which receives the read data from the data reading circuit and is controlled by a read latch signal to be turned on or off;

a read bit latch coupled to the calibration switch for latching the read data;

a correction circuit, coupled to the read bit latch and receiving the error decoding signal, for correcting the bit stored in the read bit latch according to the error decoding signal; and

the first output circuit is coupled to the correction circuit and the read bit latch, and is controlled by an output enable signal to output the bit stored in the read bit latch as the data output signal.

7. The memory device of claim 6,

the correction switch includes:

a third transmission gate and a fourth transmission gate, wherein the third transmission gate receives a read data signal from the data reading circuit, the fourth transmission gate receives an inverted read data signal from the data reading circuit, and the third transmission gate and the fourth transmission gate are both controlled by the read latch signal, wherein the read data is a differential signal including the read data signal and the inverted read data signal; and

a fifth inverter, an input terminal of which receives the read latch signal and an output terminal of which is commonly coupled to one of the control terminals of the third transmission gate and the fourth transmission gate; and

the read bit latch includes:

a sixth inverter and a seventh inverter, wherein an input of the sixth inverter is coupled to the output of the seventh inverter and receives the read data signal through the third transmission gate, and an input of the seventh inverter is coupled to the output of the sixth inverter and receives the inverted read data signal through the fourth transmission gate.

8. The memory device of claim 7, wherein the correction circuit comprises:

an eighth inverter receiving the error decoding signal;

a ninth inverter coupled to an output terminal of the sixth inverter to output the correction bit signal;

a fourth P-type transistor and a fifth P-type transistor, wherein a first terminal of the fourth P-type transistor is coupled to the power voltage, a second terminal of the fourth P-type transistor is coupled to the first terminal of the fifth P-type transistor, a control terminal of the fourth P-type transistor is coupled to the output terminal of the eighth inverter, and a second terminal of the fifth P-type transistor is coupled to the input terminal of the sixth inverter, and a control terminal of the fifth P-type transistor receives the read data signal; and

a sixth P-type transistor and a seventh P-type transistor, wherein a first terminal of the sixth P-type transistor is coupled to the power voltage, a second terminal of the sixth P-type transistor is coupled to the first terminal of the seventh P-type transistor, a control terminal of the sixth P-type transistor is coupled to the output terminal of the eighth inverter, and a second terminal of the seventh P-type transistor is coupled to the output terminal of the sixth inverter, and a control terminal of the seventh P-type transistor receives the inverted read data signal.

9. The memory device according to claim 8, wherein the first output circuit comprises:

a tenth inverter, an input terminal of which is coupled to the output enable signal;

a first nand gate having a first input terminal coupled to the second terminal of the fifth P-type transistor and a second input terminal receiving the output enable signal;

a first inverter, wherein a first input terminal of the first inverter is coupled to the second terminal of the fifth P-type transistor, and a second input terminal of the first inverter is coupled to the output terminal of the tenth inverter;

an eighth P-type transistor having a first terminal coupled to the power voltage and a control terminal coupled to the output terminal of the first NAND gate; and

a first N-type transistor having a first terminal coupled to the second terminal of the eighth P-type transistor for providing the corrected data output signal, a control terminal coupled to the output terminal of the first nor gate, and a second terminal coupled to a ground voltage.

10. The memory device according to claim 3, wherein the data writing circuit comprises:

an eleventh inverter whose input receives the corresponding data output signal;

a first write switch, an input end of which is coupled to the output end of the eleventh inverter and is controlled by a first write latch signal to be turned on or off;

a second write switch, the input end of which receives the corresponding correction bit signal and is controlled by a second write latch signal to be switched on or off;

a write bit latch coupled to an output of the first write switch and an output of the second write switch; and

and a second output circuit coupled to the output terminal of the second write switch and the write bit latch, and controlled by a write enable signal to write the data output signal or the correction bit signal into the memory cell array.

11. The memory device of claim 10,

the first write-in switch is a fifth transmission gate, and the second write-in switch is a sixth transmission gate; and

the write bit latch includes:

a twelfth inverter and a thirteenth inverter, wherein an input of the twelfth inverter is coupled to the output of the thirteenth inverter, an input of the thirteenth inverter is coupled to the output of the twelfth inverter, and inputs of the twelfth inverter are commonly coupled to the outputs of the fifth transmission gate and the sixth transmission gate.

12. The memory device according to claim 11, wherein the second output circuit comprises:

a fourteenth inverter and a fifteenth inverter, wherein the fourteenth inverter is connected in series with the fifteenth inverter, and the fourteenth inverter receives the write enable signal;

a second nand gate having a first input terminal coupled to the output terminal of the twelfth inverter and a second input terminal coupled to the output terminal of the fifteenth inverter;

a second inverter, wherein a first input terminal of the second inverter is coupled to the output terminal of the fifth inverter, and a second input terminal of the second inverter is coupled to the output terminal of the sixth inverter;

a ninth P-type transistor, having a first terminal coupled to the power voltage and a control terminal coupled to the output terminal of the second NAND gate;

a second N-type transistor having a first terminal coupled to the second terminal of the ninth P-type transistor for providing a corresponding data signal, a control terminal coupled to the output terminal of the second nor gate, and a second terminal coupled to a ground voltage;

a third nand gate having a first input terminal coupled to the output terminal of the thirteenth inverter and a second input terminal coupled to the output terminal of the fifteenth inverter;

a third inverter, wherein a first input terminal of the third inverter is coupled to the output terminal of the thirteenth inverter, and a second input terminal of the third inverter is coupled to the output terminal of the fourteenth inverter;

a tenth P-type transistor having a first terminal coupled to the power voltage and a control terminal coupled to the output terminal of the third NAND gate; and

a third N-type transistor, having a first terminal coupled to the second terminal of the tenth P-type transistor and providing a corresponding inverted data signal, a control terminal coupled to the output terminal of the third nor gate, and a second terminal coupled to the ground voltage, wherein the data is a differential signal including the data signal and the inverted data signal.

13. The memory device according to claim 12, wherein the data write circuit further comprises a control signal generation circuit that generates the first write latch signal and the second write latch signal according to an initial write latch signal and a write mask signal, comprising:

a sixteenth inverter, a seventeenth inverter and an eighteenth inverter, wherein the sixteenth inverter and the seventeenth inverter are connected in series, an input end of the sixteenth inverter receives the initial write latch signal, the seventeenth inverter outputs a verify write latch signal to the correction data read/write circuit, and the eighteenth inverter receives the initial write latch signal to output an inverted verify write latch signal to the correction data read/write circuit; and

a signal generating circuit comprising:

a nineteenth inverter, an output terminal of which receives the corresponding write mask signal;

a fourth nand gate, a first input end of which receives the initial write latch signal, a second input end of which is coupled to the output end of the nineteenth inverter, and an output end of which outputs an inverted signal of the corresponding first write latch signal;

a twentieth inverter, an input terminal of which is coupled to the output terminal of the fourth nand gate to output the corresponding first write latch signal;

a fifth nand gate, a first input terminal of which receives the initial write latch signal, a second input terminal of which receives the corresponding write mask signal, and an output terminal of which outputs an inverted signal of the corresponding second write latch signal; and

a twenty-first inverter, an input end of which is coupled to the output end of the fifth nand gate to output the corresponding second write latch signal.

14. The memory device according to claim 3, wherein the syndrome arithmetic circuit comprises:

a syndrome generating circuit, coupled to the data read/write circuit and the correction data read/write circuit, for selectively receiving an output signal of the data read/write circuit or the data correction circuit according to a read operation or a write operation to generate the correction data write signal, and comparing the correction data write signal with the corresponding correction data to generate a syndrome signal; and

the syndrome decoding circuit is coupled with the syndrome generating circuit and used for decoding the syndrome signal to generate the error decoding signal.

15. The memory device according to claim 14, wherein the syndrome generating circuit generates the correction data write signal based on the read bit signal when the data read/write circuit performs the read operation, and generates the correction data write signal based on the correction bit signal or the data output signal when the data read/write circuit performs the write operation.

16. The memory device according to claim 14, wherein the correction data read/write circuit reads the correction data to output a correction read signal to the syndrome generation circuit, and the syndrome generation circuit includes:

an internal operation circuit including a plurality of transmission gates and a plurality of first exclusive-or gates, the internal operation circuit selectively providing the data output signal, the calibration bit signal or the read bit data to the plurality of first exclusive-or gates by controlling the plurality of transmission gates to output the calibration data write signal; and

and a plurality of second exclusive-or gates receiving the correction data write signal from the internal operation circuit and receiving the corresponding correction read signal from the correction data read-write circuit to output the syndrome signal.

17. The memory device according to claim 1, wherein the correction data read/write circuit comprises:

a correction data reading circuit coupled to the correction data memory cell array and the syndrome computing circuit for reading the correction data from the correction data memory cell array to output a correction read signal to the syndrome computing circuit; and

and the correction data writing circuit is coupled with the correction data storage unit array and the syndrome operation circuit and is used for writing the corrected correction data into the correction data storage unit array.