CN115440269A

CN115440269A - Data transmission circuit, data processing circuit and memory

Info

Publication number: CN115440269A
Application number: CN202110609555.6A
Authority: CN
Inventors: 尚为兵; 李红文; 冀康灵; 何军; 龚园媛; 应战
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2021-06-01
Filing date: 2021-06-01
Publication date: 2022-12-06
Anticipated expiration: 2041-06-01
Also published as: CN115440269B

Abstract

The embodiment of the application relates to a data transmission circuit, a data processing circuit and a memory. The data transmission circuit includes: the data writing circuit is used for transmitting data to be written to the global data line; the verification write-in circuit is used for transmitting verification data to the global data line, and the verification write-in circuit and the data write-in circuit are both first circuits; the first circuit generates a pull-up enable signal in response to the pre-charge enable signal, and enables the effective pull-up enable signal to control the first pull-up circuit to output a global data signal; the first circuit also responds to the write enable signal, generates a pull-up enable signal and a pull-down enable signal according to data to be written, transmits the global data signal to the global data line, and enables the effective pull-down enable signal to control the first pull-down circuit to output the global data signal; the driving capability of the first pull-up circuit in the data writing circuit and the verifying writing circuit is equal, and the driving capability of the first pull-down circuit in the verifying writing circuit is stronger than that of the first pull-down circuit in the data writing circuit.

Description

Data transmission circuit, data processing circuit and memory

Technical Field

The embodiment of the application relates to the technical field of memories, in particular to a data transmission circuit, a data processing circuit and a memory.

Background

A semiconductor Memory is a Memory accessed using a semiconductor circuit, and among them, a Dynamic Random Access Memory (DRAM) is widely used in various fields with its fast Memory speed and high integration. In order to obtain higher data read-write reliability, a check related circuit needs to be arranged in the semiconductor memory to check whether the read data is accurate, but the introduction of the check related circuit may cause the read-write speed of the memory to be slow, which affects the performance of the semiconductor memory.

Disclosure of Invention

The embodiment of the application provides a data transmission circuit, a data processing circuit and a memory, which can optimize the read-write speed of the memory.

A data transmission circuit comprising:

the data writing circuit is used for transmitting data to be written to a global data line connected with the data storage unit;

the verification write-in circuit is used for transmitting verification data to a global data line connected with the verification storage unit, the verification data correspond to data to be written, and the verification write-in circuit and the data write-in circuit are both first circuits;

the first circuit includes: a first pull-up circuit and a first pull-down circuit;

the first circuit is used for responding to a pre-charging enabling signal and generating a pull-up enabling signal, and the effective pull-up enabling signal is enabled to control the first pull-up circuit to output a global data signal; the first circuit is also used for responding to the write enable signal, generating a pull-up enable signal and a pull-down enable signal according to data to be written, transmitting the global data signal to the global data line, enabling the effective pull-down enable signal to control the first pull-down circuit to output the global data signal, and enabling the pull-up enable signal and the pull-down enable signal in a time-sharing manner;

the driving capacity of a first pull-up circuit in the data writing circuit is equal to that of a first pull-up circuit in the verification writing circuit, and the driving capacity of the first pull-down circuit in the verification writing circuit is stronger than that of the first pull-down circuit in the data writing circuit.

In one embodiment, the electrical parameters of the devices corresponding to the first pull-down circuit in the data writing circuit and the verification writing circuit are not completely the same, so that the driving capability of the first pull-down circuit in the verification writing circuit is stronger than that of the first pull-down circuit in the data writing circuit.

In one embodiment, the first pull-up circuit comprises a first pull-up transistor, the first pull-up transistor is conducted at a low level, a control end of the first pull-up transistor is used for receiving an inverted signal of data to be written, and a first end of the first pull-up transistor is connected with a power supply voltage end;

the first pull-down circuit comprises a first pull-down transistor, the high level of the first pull-down transistor is conducted, the control end of the first pull-down transistor is used for receiving an inverted signal of data to be written, the first end of the first pull-down transistor is connected with the grounding end, and the second end of the first pull-down transistor is connected with the second end of the first pull-up transistor;

the channel width-length ratio of the first pull-down transistor in the verification writing circuit is larger than that of the first pull-down transistor in the data writing circuit.

In one embodiment, the channel width-to-length ratio of the first pull-up transistor in the verify write circuit is equal to the channel width-to-length ratio of the first pull-up transistor in the data write circuit.

In one embodiment, the threshold voltage of the first pull-up transistor in the verify write circuit is equal to the threshold voltage of the first pull-up transistor in the verify write circuit.

In one embodiment, the threshold voltage of the first pull-down transistor in the verify write circuit is less than the threshold voltage of the first pull-down transistor in the verify write circuit.

In one embodiment, the data transfer circuit is configured with a precharge phase in which the precharge enable signal is active and a data write phase in which the write enable signal is active, the first circuit further comprising:

and the logic operation unit is respectively connected with the first pull-up transistor and the first pull-down transistor and is used for responding to the write enable signal in the data writing stage and generating an inverted signal of the data to be written.

And the NOT gate circuit is connected with the logic operation unit and used for receiving a pre-charging enabling signal and controlling the logic operation unit to output a low-level signal in a pre-charging stage.

In one embodiment, the logical operation unit includes:

the first input end of the AND gate circuit is used for receiving data to be written, and the second input end of the AND gate circuit is used for receiving a write enable signal;

and the first input end of the first NOR gate circuit is connected with the output end of the AND gate circuit, the second input end of the first NOR gate circuit is connected with the output end of the NOT gate circuit, the pre-charging enabling signal is used for switching the data transmission circuit to a pre-charging stage or a data writing stage, and the output end of the first NOR gate circuit is connected with the control end of the first pull-up transistor.

In one embodiment, the output terminal of the first nor gate is further connected to the control terminal of the first pull-down transistor.

In one embodiment, the logical operation unit further includes:

the first input end of the NAND gate circuit is used for receiving a pre-charging enabling signal, and the second input end of the NAND gate circuit is used for receiving a writing enabling signal;

and the first input end of the second NOR gate circuit is used for receiving data to be written, the second input end of the second NOR gate circuit is connected with the output end of the NAND gate circuit, and the output end of the second NOR gate circuit is connected with the control end of the first pull-down circuit.

In one embodiment, the data write circuit and the verification write circuit respectively transmit the global data signals to the corresponding global data lines in response to the same write enable signal.

In one embodiment, the data transmission circuit further comprises:

the data reading circuit is used for acquiring stored data to be read from a global data line connected with the data storage unit so as to read the data to be read;

the verification reading circuit is used for acquiring stored verification data from a global data line connected with the verification storage unit so as to read the stored verification data, and the stored verification data corresponds to the stored data to be read;

wherein, the driving capability of the verification reading circuit is equal to that of the data reading circuit.

In one embodiment, the circuit structures of the data reading circuit and the verification reading circuit are both the second circuit, and the electrical parameters of the corresponding devices in the data reading circuit and the verification reading circuit are the same, so that the driving capability of the verification reading circuit is equal to that of the data reading circuit.

In one embodiment, the global data line is further configured to transmit a read signal, a level state of the read signal is the same as a level state of data to be read, and the second circuit includes:

an input unit for receiving a global data signal in response to a read enable signal;

a reference unit for receiving a reference data signal in response to a read enable signal;

the pre-charging unit is connected with the input unit and the reference unit and connected with the second node, and is used for responding to a pre-charging enabling signal and pre-charging the first node and the second node to a preset level respectively;

and the output unit is respectively connected with the input unit and the reference unit and used for generating a read data signal according to the global data signal and the reference data signal.

A data processing circuit comprising:

the data transmission circuit as described above;

and the verification generating circuit is connected with the verification writing circuit and used for acquiring the data to be written, generating corresponding verification data according to the data to be written and transmitting the verification data to the verification writing circuit.

A memory, comprising: data storage unit, check storage unit and data processing circuit as above.

In the above-mentioned data transmission circuit, data processing circuit and memory, the data transmission circuit includes: the data writing circuit is used for transmitting data to be written to a global data line connected with the data storage unit; the verification write-in circuit is used for transmitting verification data to a global data line connected with the verification storage unit, the verification data correspond to data to be written in, and the verification write-in circuit and the data write-in circuit are both first circuits; the first circuit includes: a first pull-up circuit and a first pull-down circuit; the first circuit is used for responding to a pre-charging enabling signal and generating a pull-up enabling signal, and the effective pull-up enabling signal is enabled to control the first pull-up circuit to output a global data signal; the first circuit is also used for responding to the write enable signal, generating a pull-up enable signal and a pull-down enable signal according to data to be written, transmitting the global data signal to the global data line, enabling the effective pull-down enable signal to control the first pull-down circuit to output the global data signal, and enabling the pull-up enable signal and the pull-down enable signal in a time-sharing manner; the driving capacity of the first pull-up circuit in the data writing circuit is equal to that of the first pull-up circuit in the verification writing circuit, and the driving capacity of the first pull-down circuit in the verification writing circuit is stronger than that of the first pull-down circuit in the data writing circuit. The first pull-up circuit in the verification write-in circuit and the data write-in circuit generates a pull-up enabling signal in response to a precharge enabling signal, the first pull-up circuit is controlled by an enabling effective pull-up enabling signal to output a global data signal, the first circuit generates a pull-up enabling signal and a pull-down enabling signal in response to the write enabling signal according to data to be written, the global data signal is transmitted to a global data line, the first pull-down circuit is controlled by the enabling effective pull-down enabling signal to output the global data signal, the driving capability of the first pull-up circuit in the data write-in circuit is equal to that of the first pull-up circuit in the verification write-in circuit, the driving capability of the first pull-down circuit in the verification write-in circuit is stronger than that of the first pull-down circuit in the data write-in circuit, the transmission speed of verification data can be higher than that of the data to be stored, so that the time for generating the verification data in the embodiment of the application is compensated, the data write-in speed of the memory is increased, the number of the global data lines is saved, and the power consumption is reduced.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or related technologies of the present application, the drawings needed to be used in the description of the embodiments or related technologies are briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is a block diagram of a data processing circuit according to an embodiment;

FIG. 2 is a block diagram of a first circuit according to an embodiment;

FIG. 3 is a second block diagram of the first circuit according to an embodiment;

FIG. 4 is a timing diagram illustrating the writing of data to be stored and parity data according to one embodiment;

FIG. 5 is a second block diagram of the data processing circuit according to an embodiment;

FIG. 6 is a block diagram of a second circuit according to an embodiment;

FIG. 7 is a partial schematic diagram of a second circuit according to an embodiment;

FIG. 8 is a timing diagram of signals in the pulse width modulation unit of the embodiment of FIG. 7;

FIG. 9 is a schematic diagram of a first control circuit according to an embodiment;

FIG. 10 is a diagram illustrating a second control circuit according to an embodiment;

FIG. 11 is a diagram illustrating an output unit according to an embodiment;

FIG. 12 is a second schematic structural diagram of an output unit according to an embodiment;

fig. 13 is a second partial schematic structure diagram of the second circuit according to the embodiment.

Description of reference numerals:

10. a data transmission circuit; 100. a data write circuit; 200. a verify write circuit; 300. a first circuit; 302. a first pull-up circuit; 304. a first pull-down circuit; 306. a logical operation unit; 308. a not gate circuit; 310. an AND gate circuit; 312. a first NOR gate circuit; 314. a NAND gate circuit; 316. a second NOR gate circuit; 400. a data storage unit; 500. verifying the storage unit; 600. a data reading circuit; 700. verifying the reading circuit; 800. a second circuit; 802. an input unit; 8021. a first switch; 8022. a first control circuit; 804. a reference unit; 8041. a second control circuit; 8042. a second switch; 806. a pre-charging unit; 808. an output unit; 8081. a first output circuit 8081; 8082. a second output circuit; 810. a pulse width adjusting unit; 20. a verification generation circuit.

Detailed Description

To facilitate an understanding of the embodiments of the present application, the embodiments of the present application will be described more fully below with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. The embodiments of the present application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments of this application belong. The terminology used herein in the description of the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments of the present application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It will be understood that, as used herein, the terms "first," "second," and the like may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, a first node yilon may be referred to as a second node yilon, and similarly, a second node yilon may be referred to as a first node yilon, without departing from the scope of this application. The first node YIONloc and the second node YIONloc are both nodes, but they are not the same node.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise. In the description of the present application, "a number" means at least one, such as one, two, etc., unless specifically limited otherwise.

Fig. 1 is one of structural block diagrams of a Data processing circuit according to an embodiment, and it should be noted that Data to be written shown in each drawing in the embodiment of the present application refers to Data to be stored that actually needs to be stored for a Data writing circuit 100, and refers to check Data generated according to the Data to be stored for a check writing circuit 200. Referring to fig. 1, in the present embodiment, the data processing circuit includes a data transmission circuit 10 and a verification generation circuit 20.

The verification generation circuit 20 is configured to receive data to be stored and generate verification data according to the data to be stored. The check data is generated and stored in the data writing stage to determine whether an error occurs in the data reading stage, that is, whether the data read from the data storage unit 400 is the same as the data to be stored is determined to determine whether an error occurs in the data reading and writing process. The verification generation circuit 20 may be configured to verify data information of a plurality of storage arrays, so as to optimize the number of the verification generation circuits 20, and further provide a small-sized semiconductor memory. It is understood that the check generating circuit 20 may have any circuit structure having a function of generating check data, and the present embodiment does not limit the specific type of the check generating circuit 20, and may have at least one of a parity check function, an error correction check function, and the like.

The memory array includes a plurality of data memory cells 400 and a plurality of verify memory cells 500 for storing data signals, thereby implementing a memory function of the semiconductor memory. The data storage unit 400 is used for storing data to be stored, which is input to the memory from the outside, and the verification storage unit 500 is used for storing verification data generated according to the data to be stored. Specifically, the memory cell further comprises a storage capacitor and a transistor, wherein a control end of the transistor is connected with the word line, a first end of the transistor is connected with the storage capacitor, and a second end of the transistor is connected with the bit line. When the word line control transistor is conducted, the storage capacitor is conducted with the bit line, so that data information is read and written, namely, when the data information is read, the storage capacitor transmits the stored data information to the bit line; when data information is written, the bit line sends the data information to be written to the storage capacitor.

The data transmission circuit 10 includes a data write circuit 100 and a verify write circuit 200. The data transmission circuit 10 is respectively connected to the verification generation circuit 20 and the storage array, and is configured to transmit data to be stored to the data storage unit 400 and transmit verification data to the verification storage unit 500. Specifically, the data writing circuit 100 is configured to transmit data to be written to a global data line connected to the data storage unit 400, so as to store the data to be written; the verification write circuit 200 is configured to transmit verification data to a global data line connected to the verification storage unit 500 to store the verification data, where the verification data corresponds to data to be written. The verification write circuit 200 and the data write circuit 100 are both the first circuit 300, and it is understood that the data write circuit 100 and the verification write circuit 200 correspond to each other and have the same connection relationship. In this embodiment, by setting the data write circuit 100 and the verification write circuit 200 having the same circuit structure, the difficulty in optimizing the parameters of the semiconductor memory can be reduced, so that the difficulty in the mask design process and the difficulty in the memory manufacturing process can be reduced, and the preparation yield of the semiconductor memory can be improved.

The first circuit 300 includes: a first pull-up circuit 302 and a first pull-down circuit 304; the first circuit 300 is configured to generate a pull-up enable signal in response to the precharge enable signal EQ, and enable the active pull-up enable signal to control the first pull-up circuit 302 to output the global data signal; the first circuit 300 is further configured to generate a pull-up enable signal and a pull-down enable signal according to Data to be written in response to the write enable signal WrEn, and transmit the global Data signal to the global Data line YIO, where the enabled pull-down enable signal controls the first pull-down circuit 304 to output the global Data signal. In this embodiment, the pull-up enable signal and the pull-down enable signal are enabled in a time-sharing manner, so that the global Data signal transmitted to the global Data line YIO has a certain level state, and the certain level state is specifically the same as the level state of the Data to be written. The global data signal includes a signal which is subsequently transmitted on the global data line, and it is to be understood that the global data signal includes a global data signal at a high level output by the first pull-up circuit 302 and a global data signal at a low level output by the first pull-down circuit 304, and the global data signal at the high level and the global data signal at the low level are transmitted to the global data line in a time-sharing manner. Before receiving Data to be written, the first circuit 300 controls the first pull-up circuit 302 to output a global Data signal of a high level in response to the precharge enable signal EQ, if the first circuit 300 generates a pull-up enable signal enabling valid according to the Data to be written, the first circuit 300 directly transmits the global Data signal of the high level generated by controlling the first pull-up circuit 302 in response to the precharge enable signal EQ to the global Data line YIO, and controls the first pull-up circuit 302 to continuously output the global Data signal of the high level through the pull-up enable signal enabling valid, and if the first circuit 300 generates a pull-down enable signal enabling valid according to the Data to be written, the first circuit 300 controls the first pull-down circuit 304 to output the global Data signal of the low level, and transmits the global Data signal of the low level to the global Data line YIO.

The data write circuit 100 and the verification write circuit 200 are configured to synchronously transmit data to the corresponding global data line YIO, and it should be clear that synchronous transmission in this embodiment is not limited to that two data must be written at the same time, and synchronous transmission means that verification data and data to be stored having a corresponding relationship are transmitted in the same data write cycle. For example, the data writing circuit 100 and the verification writing circuit 200 respectively transmit data to corresponding global data line groups in response to the same write enable signal WrEn, so as to save the number of required signals on the one hand and improve the writing synchronism of the data to be stored and the verification data on the other hand. In the present embodiment, the driving capability of the first pull-up circuit 302 in the data writing circuit 100 is equal to the driving capability of the first pull-up circuit 302 in the verification writing circuit 200, and the driving capability of the first pull-down circuit 304 in the verification writing circuit 200 is stronger than the driving capability of the first pull-down circuit 304 in the data writing circuit 100, wherein the driving capabilities of the first pull-up circuit 302 and the first pull-down circuit 304 can be characterized by the writing current, therefore, the writing current of the first pull-up circuit 302 in the verification writing circuit 200 of the present embodiment is equal to the writing current of the first pull-up circuit 302 in the data writing circuit 100, and the writing current of the first pull-down circuit 304 in the verification writing circuit 200 is greater than the writing current of the first pull-down circuit 304 in the data writing circuit 100.

The data to be stored can be directly written into the data storage unit 400 through the data writing circuit 100, and the verification data needs to be generated according to the data to be stored, so the time for the verification data to reach the verification writing circuit 200 is inevitably later than the time for the data to be stored to reach the data writing circuit 100, and correspondingly, the time for the verification data to be written into the verification storage unit 500 is also slightly later than the corresponding writing time of the data to be stored, thereby causing the problems of poor data writing synchronism and further increased writing speed. In this embodiment, the first circuit responds to the precharge enable signal, and controls the first pull-up circuit to output the global data signal transmitted to the global data line according to the data to be written in advance, and by setting the first pull-down circuit with strong driving capability in the verification write-in circuit 200, the total time length for data writing in the verification write-in circuit 200 can be shortened, so that the transmission speed of the verification data is greater than that of the data to be stored, thereby effectively compensating the time consumed in the process of generating the verification data, and further optimizing the write-in speed of the stored data.

In one embodiment, the electrical parameters of the corresponding devices of the first pull-up circuit 302 in the data writing circuit 100 and the verification writing circuit 200 are identical, so that the driving capability of the first pull-up circuit 302 in the verification writing circuit 200 is equal to that of the first pull-up circuit 302 in the data writing circuit 100. The corresponding devices refer to two devices which are located at the same position in two circuits and have the same connection relationship, and the types of the corresponding devices may be, but are not limited to, MOS transistors, triodes, diodes, and the like.

In one embodiment, the electrical parameters of the corresponding devices of the first pull-down circuit 304 in the data writing circuit 100 and the verification writing circuit 200 are not identical, so that the driving capability of the first pull-down circuit 304 in the verification writing circuit 200 is stronger than that of the first pull-down circuit 304 in the data writing circuit 100.

Fig. 2 is a block diagram of a first circuit according to an embodiment, and referring to fig. 2, in one embodiment, the first pull-up circuit 102 includes a first pull-up transistor T1, the first pull-down circuit 104 includes a first pull-down transistor T2, and the first pull-up transistor T1 and the first pull-down transistor T2 are different in conduction type, one of which is turned on at a high level and the other of which is turned on at a low level. Specifically, the first pull-up transistor T1 is turned on at a low level, a control terminal of the first pull-up transistor T1 is configured to receive an inverted signal of Data to be written, and a first terminal of the first pull-up transistor T1 is connected to the power supply voltage terminal. The first pull-down transistor T2 is turned on at a high level, the control terminal of the first pull-down transistor T2 is used for receiving an inverted signal of Data to be written, the first terminal of the first pull-down transistor T2 is connected with the ground terminal, and the second terminal of the first pull-down transistor T2 is connected with the second terminal of the first pull-up transistor T1. Specifically, in the precharge stage, the precharge enable signal EQ is at a low level, the first pull-up transistor T1 is turned on, and the global data signal whose output voltage is the power supply voltage, that is, the global data signal at a high level is output, thereby implementing precharge; in the Data writing stage, the precharge enable signal EQ is at a high level, the write enable signal WrEn is at a high level, and the first circuit 300 can implement Data writing according to the Data signal, for example, when the Data signal is at a high level, the control end of the first pull-up transistor T1 and the control end of the second pull-up transistor T3 both receive a low-level signal, the first pull-up transistor T1 is turned on, the first pull-down transistor T2 is turned off, the global Data signal whose voltage is the power voltage is maintained, and the power voltage is transmitted to the global Data line YIO, and at this time, the write signal is at a high level, so that the signal on the global Data line YIO is the same as the Data signal to be written.

It can be understood that the larger the channel width-to-length ratio of the first pull-down transistor in the verify-write circuit is, the larger the channel width-to-length ratio of the transistor is, the higher the write current is, and accordingly the stronger the driving capability is, therefore, the driving capability of the first pull-down transistor T2 of the verify-write circuit 200 is stronger than that of the first pull-down transistor T2 of the data write circuit 100, so as to improve the data transmission speed of the global data signal output by the first pull-down transistor T2 of the verify-write circuit 200, and further improve the write speed of the semiconductor memory.

In one embodiment, the channel width-to-length ratio of the first pull-up transistor in the verify write circuit is equal to the channel width-to-length ratio of the first pull-up transistor in the data write circuit, so that the data transfer rate of the global data signal output by the first pull-up transistor T1 in the verify write circuit 200 is equal to the data transfer rate of the global data signal output by the first pull-up transistor T1 in the data write circuit 100.

In one embodiment, the threshold voltage of the first pull-up transistor in the verify write circuit is equal to the threshold voltage of the first pull-up transistor in the verify write circuit. It is understood that the smaller the threshold voltage, the larger the write current thereof, and accordingly the stronger the driving capability, and therefore the threshold voltage of the first pull-up transistor in the verify write circuit is equal to the threshold voltage of the first pull-up transistor in the data write circuit, so that the data transfer rate of the global data signal output by the first pull-up transistor T1 in the verify write circuit 200 is equal to the data transfer rate of the global data signal output by the first pull-up transistor T1 in the data write circuit 100. Alternatively, the threshold voltages of the transistors may be changed by adjusting the doping concentrations, that is, the first pull-down transistor T2 of the verify write circuit 200 and the first pull-down transistor T2 of the data write circuit 100 are formed with different doping concentrations, respectively, to achieve different threshold voltages.

In one embodiment, the threshold voltage of the first pull-down transistor in the verify write circuit is less than the threshold voltage of the first pull-down transistor in the verify write circuit. Similarly to the foregoing description, the smaller the threshold voltage, the larger the write current thereof, and accordingly the stronger the driving capability, therefore, the threshold voltage of the first pull-down transistor in the verify write circuit is smaller than the threshold voltage of the first pull-down transistor in the data write circuit, so that the driving capability of the first pull-down transistor T2 of the verify write circuit 200 is stronger than the driving capability of the first pull-down transistor T2 of the data write circuit 100, thereby increasing the data transfer rate of the global data signal output by the first pull-down transistor T2 in the verify write circuit 200, and further increasing the write speed of the semiconductor memory. Alternatively, the threshold voltages of the transistors may be changed by adjusting the doping concentrations, that is, the first pull-down transistor T2 of the verify write circuit 200 and the first pull-down transistor T2 of the data write circuit 100 are formed with different doping concentrations, respectively, to achieve different threshold voltages.

Referring to fig. 2, in one embodiment, the first circuit 300 further comprises: a logic operation unit 306 and a not gate circuit 308. The logical operation unit 306 is connected to the first pull-up transistor T1 and the first pull-down transistor T2, respectively, and generates an inverted signal of the Data to be written in response to the write enable signal WrEn in the Data writing phase. The not circuit 308 is connected to the logic operation unit 306, and is configured to receive the precharge enable signal EQ and control the logic operation unit 306 to output a low level signal in the precharge phase. In this embodiment, the precharge enable signal EQ is further applied to the first circuit 300, when the precharge enable signal EQ is at a low level, the data transmission circuit is in a precharge stage, and under the action of the not gate circuit 308, the inverted precharge enable signal EQ at a high level is transmitted to the logic operation unit 306, so as to control the logic operation unit 306 to keep the level state of the output signal unchanged in the precharge stage, thereby improving the stability and reliability of the circuit.

With continued reference to FIG. 2, in one embodiment, the logical operation unit 306 includes an AND gate circuit 310 and a first NOR gate circuit 312. A first input end of the and circuit 310 is configured to receive Data to be written, and a second input end of the and circuit 310 is configured to receive a write enable signal WrEn; in the Data writing phase, the write enable signal WrEn is high, so the signal output by the and circuit 310 follows the Data signal input by the first input terminal. A first input terminal of the first nor gate 312 is connected to the output terminal of the and gate 310, a second input terminal of the first nor gate 312 is connected to the output terminal of the not gate 308, and is configured to receive an inverted signal of a precharge enable signal EQ, where the precharge enable signal EQ is used to switch the data transmission circuit to a precharge stage or a data write stage, and an output terminal of the first nor gate 312 is connected to a control terminal of the first pull-up transistor. Further, the output end of the first nor gate 312 may be connected to the control end of the first pull-down transistor T2, so as to control the first pull-up transistor T1 and the first pull-down transistor T2 simultaneously based on a signal, thereby saving the number of signal traces. In the precharge phase, the precharge enable signal EQ is at a low level, the output signal of the not-gate circuit 308 is at a high level, and if one input terminal of the first not-gate circuit 312 is at a high level, the output signal thereof must be at a low level, so as to keep the write signals received by the control terminals of the first pull-up transistor T1 and the first pull-down transistor T2 unchanged. In the Data write phase, the precharge enable signal EQ and the write enable signal WrEn are both high level, so that the signal on the global Data line YIO corresponds to the Data signal.

Fig. 3 is a second block diagram of the first circuit according to an embodiment, referring to fig. 3, in which the logic unit 306 further includes: a nand gate 314 and a second nor gate 316. A first input terminal of the nand gate circuit 314 is configured to receive the precharge enable signal EQ, and a second input terminal of the nand gate circuit 314 is configured to receive the write enable signal WrEn; a first input terminal of the second nor gate 316 is configured to receive Data to be written, a second input terminal of the second nor gate 316 is connected to the output terminal of the nand gate 314, and an output terminal of the second nor gate 316 is connected to the control terminal of the first pull-down circuit T2. The first pull-up transistor T1 is controlled by the first nor gate 312, and the control method is as in the previous embodiment, which is not described herein again. In the precharge phase, the precharge enable signal EQ is at a low level, the output signal of the nand gate circuit 314 is at a high level, and if one input terminal of the second nor gate circuit 316 is at a high level, the output signal thereof must be at a low level, so as to keep the write signals received by the control terminals of the first pull-up transistor T1 and the first pull-down transistor T2 unchanged. In the Data write phase, the precharge enable signal EQ and the write enable signal WrEn are both high level, so that the signal on the global Data line YIO corresponds to the Data signal. In this embodiment, the first pull-up transistor T1 and the first pull-down transistor T2 are controlled by the two logic gates in a one-to-one correspondence manner, so that the control reliability of the first pull-up transistor T1 and the first pull-down transistor T2 can be effectively improved.

Fig. 4 is a timing diagram for writing data to be stored and verification data according to an embodiment, both the data writing circuit 100 and the verification writing circuit 200 of this embodiment employ the first circuit 300 of the embodiment of fig. 3, referring to fig. 8, based on the first circuit 300 of the embodiment of fig. 3, a time period tdp required for writing low-level verification data is smaller than a time period td required for writing low-level data to be stored, and in the precharge stage, a global data signal preset value is set to a high level, and a time for outputting a global data signal according to the data to be written when transmitting the high-level verification data and the high-level data to be stored is negligible, thereby improving the writing speed of the semiconductor memory.

Fig. 5 is a second block diagram of the data processing circuit according to an embodiment, and referring to fig. 5, in one embodiment, the signal processing further includes a data reading circuit 600 and a verification reading circuit 700. The Data reading circuit 600 is configured to obtain Data to be read from the global Data line group connected to the Data storage unit 400, so as to read the Data to be read; the verification reading circuit 700 is configured to obtain verification Data from the global Data line connected to the verification storage unit 500 to read stored verification Data, where the stored verification Data corresponds to Data to be read. Wherein, the driving capability of the verify-read circuit 700 is equal to the driving capability of the data-read circuit 600. In the Data reading stage, since the read Data can be verified based on the verification Data after the read operation of the Data to be read is completed, the reading speeds of the Data reading circuit 600 and the verification reading circuit 700 are equivalent, and the reading speed of the semiconductor memory is not affected.

In one embodiment, the circuit structures of the data reading circuit 600 and the verification reading circuit 700 are both the second circuit 800, and the electrical parameters of the corresponding devices in the data reading circuit 600 and the verification reading circuit 700 are the same. Specifically, fig. 6 is a block diagram of a second circuit according to an embodiment, and referring to fig. 6, in this embodiment, the global Data line YIO is further used for transmitting a read signal, a level state of the read signal is the same as that of Data to be read, and the second circuit 800 includes an input unit 802, a reference unit 804, a precharge unit 806, and an output unit 808.

The input unit 802 is configured to receive a global data signal YIO in response to an externally input read enable signal RdEn. The reference unit 804 is configured to receive the reference data signal Ref in response to the read enable signal RdEn. The precharge unit 806 is connected to the first node YIONloc with the input unit 802, and connected to the second node YIONloc with the reference unit 804, and the precharge unit 806 is configured to precharge the first node YIONloc and the second node YIONloc to a predetermined level in response to a precharge enable signal EQ before data reading. The output unit 808 is connected to the input unit 802 and the reference unit 804, respectively, and is configured to generate the read Data signal Data according to the global Data signal YIO and the reference Data signal Ref. In this embodiment, first, in the precharge phase, the first node YIONloc and the second node YIONloc are precharged, so that the data to be read can be accurately and quickly read. Then, in the data reading stage, the process and result of reading data can be adjusted by the reference data signal Ref received by the reference unit 804, thereby improving the accuracy of data reading. According to the performance test result before the semiconductor memory leaves the factory, a specific reference data signal Ref can be preset and stored in the semiconductor memory.

Fig. 7 is a partial schematic structure diagram of a second circuit according to an embodiment, and referring to fig. 7, in the present embodiment, the precharge unit 806 includes transistors T14 to T22. Specifically, the transistors T14 to T16 form a precharge circuit, the first terminal of the transistor T14 is connected to the power supply terminal, the first terminal of the transistor T15 is connected to the power supply terminal, the first terminal of the transistor T16 is connected to the second terminal of the transistor T14, the second terminal of the transistor T16 is connected to the second terminal of the transistor T15, and the control terminals of the three transistors simultaneously receive the precharge enable signal EQ, thereby implementing fast precharge. The transistors T17 to T20 together form a positive feedback circuit, that is, the transistors T17 to T20 form an amplifying circuit, which amplifies signals of the first node YIONloc and the second node YIOloc in the data reading stage, so that the signal of the global data line YIO is transmitted to the subsequent output unit 808. Specifically, the control terminal of the transistor T17 and the control terminal of the transistor T19 are respectively connected to the second terminal of the transistor T16, the control terminal of the transistor T18 and the control terminal of the transistor T20 are respectively connected to the first terminal of the transistor T16, the first terminal of the transistor T17 and the first terminal of the transistor T18 are respectively connected to the power supply terminal, the second terminal of the transistor T17 is connected to the first terminal of the transistor T19, the second terminal of the transistor T18 is connected to the first terminal of the transistor T20, and the second terminal of the transistor T19 and the second terminal of the transistor T20 are respectively connected to the first terminal of the transistor T11. In some embodiments, the precharge circuit further includes a control terminal of the transistor T21 and a control terminal of the transistor T22, which respectively receive the precharge enable signal EQ, a first terminal of the transistor T21 and a first terminal of the transistor T22 are respectively connected to the power supply terminals, a second terminal of the transistor T21 is connected to the first node yionoc, and a second terminal of the transistor T22 is connected to the second node yionoc. It should be noted that the positive feedback circuit (amplifying circuit) in the embodiment of fig. 7 is only used for exemplary illustration and is not used to limit the protection scope of the present application, and other positive feedback circuits having the same function also belong to the protection scope of the present application. It should be noted that, in this embodiment, fig. 7 shows the amplifying circuit in the precharging unit 806, which is only for convenience of description and does not limit the scope of protection of the present application, it should be understood by those skilled in the art that, in order to implement different functions in the precharging circuit and the amplifying circuit, in the precharging stage, the precharging circuit is operated while the amplifying circuit is not operated, and in the data reading stage, the precharging circuit is not operated while the amplifying circuit is operated, so as to amplify the global data signal.

With continued reference to fig. 7, in some embodiments, the second circuit 800 further includes a pulse width adjustment unit 810. The pulse width adjusting unit 810 is respectively connected to the input unit 802 and the reference unit 804, and is configured to adjust the read enable signal RdEn according to the precharge enable signal EQ to generate an enable adjustment signal, and the input unit 802 and the reference unit 804 are respectively configured to generate corresponding data signals in response to the enable adjustment signal. That is, the input unit 802 controls the data signal of the first node YIONloc in response to the enable adjustment signal, and the reference unit 804 controls the data signal of the second node YIONloc in response to the enable adjustment signal. Fig. 8 is a timing diagram of signals in the pulse width adjusting unit of the embodiment of fig. 7, and referring to fig. 8, a pulse width of the enable adjusting signal is smaller than a pulse width of the read enable signal RdEn and smaller than a width of the precharge enable signal EQ that is disabled. In the present embodiment, based on the wider read enable signal RdEn and the inverted precharge enable signal EQN, a signal having a pulse width less than 500ps can be generated, thereby realizing a more accurate signal generation function.

With continued reference to FIG. 7, in one embodiment, the input cell 802 includes a first read transistor T01. The control terminal of the first read transistor T01 is configured to receive the global data signal YIO, the first terminal of the first read transistor T01 is connected to the pulse width adjusting unit 810, and the second terminal of the first read transistor T01 is connected to the first node YIONloc. When the global data signal YIO is at a high level, the first reading transistor T01 is turned on, and the first reading transistor T01 transmits the enable adjustment signal to the first node YIONloc, wherein the level state of the enable adjustment signal can be adjusted by the switch structure in the pulse width adjustment unit 810, thereby controlling the signal transmitted to the first node YIONloc. When the global data signal YIO is low, the first read transistor T01 is turned off, and the level state of the first node YIONloc remains unchanged. Based on the above structure, the input unit 802 can transmit the data information carried by the global data signal YIO to the first node YIONloc.

Further, the input unit 802 further includes a second reading transistor T02. A control terminal of the second reading transistor T02 is configured to receive the global data signal YIO, a first terminal of the second reading transistor T02 is connected to a first terminal of the first reading transistor T01, and a second terminal of the second reading transistor T02 is connected to a second terminal of the first reading transistor T01. Still further, the input unit 802 further includes a first switch 8021. The first switch 8021 includes two first terminals and a second terminal, one first terminal of the first switch 8021 is configured to receive the global data signal YIO, another first terminal of the first switch 8021 is grounded, the second terminal of the first switch 8021 is connected to the control terminal of the second reading transistor T02, and the first switch 8021 is configured to selectively transmit the global data signal YIO or the ground signal to the control terminal of the second reading transistor T02. Here, if the first switch 8021 selects the ground path, the second reading transistor T02 is always turned off. If the first switch 8021 selects the global data signal YIO, the second reading transistor T02 is turned on or off according to the level state of the global data signal YIO, that is, the second reading transistor T02 corresponds to the first reading transistor T01 synchronously, and transmits the same enable adjustment signal, so that the response speed to the global data signal YIO can be effectively improved. It is understood that the semiconductor memory includes a plurality of second circuits 800, and the signal transmission speeds of the different second circuits 800 are not completely the same due to the difference of the process. Therefore, by providing the first switch 8021, the response speed of the second circuit 800 can be adjusted more flexibly, and the reading performance of the semiconductor memory can be improved.

In one embodiment, the input unit 802 further includes a first control circuit 8022 and a third read transistor T03. The first control circuit 8022 is configured to generate an adjustment control signal according to the global data signal YIO and the first control signal. Wherein the memory may include a plurality of fuses to configure the memory, in some examples, the first control signal may be a signal correspondingly generated according to a fuse state. In other examples, the first control signal may also be a signal input from outside the memory. A control end of the third reading transistor T03 is connected to the first control circuit 8022 and configured to receive the adjustment control signal, a first end of the third reading transistor T03 is connected to a first end of the first reading transistor T01, and a second end of the third reading transistor T03 is connected to a second end of the first reading transistor T01. Specifically, fig. 9 is a schematic structural diagram of the first control circuit according to an embodiment, and referring to fig. 9, the first control circuit 8022 includes a pull-up transistor and a pull-down transistor, a first terminal of the pull-up transistor is connected to a power supply terminal, a second terminal of the pull-up transistor is connected to a first terminal of the pull-down transistor, a second terminal of the pull-down transistor is connected to ground, and the two transistors are enabled in different manners. The two transistors respectively receive the same first control signal and output corresponding adjusting control signals under the control of the first control signal. As shown in fig. 9, if the first control signal is a time-sharing variable signal, the first control circuit 8022 also outputs different adjusting control signals YIO _ opt1 and YIO _ opt through an output terminal in a time-sharing manner. It is understood that the number of the first control signals corresponds to the number of the third reading transistors T03 in the input unit 802, and the level state of the first control signals can be set according to the sensitivity requirement. In the present embodiment, the plurality of first control signals are used to control the sensitivity characteristics of the input unit 802 more flexibly, and defects can be formed by a card control process, thereby improving the reliability of the semiconductor memory.

With continued reference to FIG. 7, in one embodiment, the reference cell 804 includes a fourth read transistor T04. A control terminal of the fourth read transistor T04 is configured to receive the reference data signal Ref, a first terminal of the fourth read transistor T04 is configured to receive the enable adjustment signal, and a second terminal of the fourth read transistor T04 is connected to the second node yiloc, so that a voltage of the second node yiloc is adjusted according to the reference data signal Ref.

Further, the reference cell 804 further includes a second control circuit 8041 and a fifth read transistor T05. The second control circuit 8041 is configured to generate a reference control signal according to the second control signal. A control terminal of the fifth reading transistor T05 is connected to the second control circuit 8041 for receiving the reference control signal, a first terminal of the fifth reading transistor T05 is connected to a first terminal of the fourth reading transistor T04, and a second terminal of the fifth reading transistor T05 is connected to a second terminal of the fourth reading transistor T04. Specifically, fig. 10 is a schematic structural diagram of the second control circuit according to an embodiment, and referring to fig. 10, the second control circuit 8041 includes a pull-up transistor and a pull-down transistor, a first terminal of the pull-up transistor is connected to a power supply terminal, a second terminal of the pull-up transistor is connected to a first terminal of the pull-down transistor, a second terminal of the pull-down transistor is grounded, and the two transistors are enabled differently. The two transistors respectively receive the same second control signal and output corresponding adjusting control signals under the control of the second control signal. As shown in fig. 10, if the second control signal is a time-sharing signal, the second control circuit 8041 also time-shares different adjusting control signals Ref _ opt2, ref _ opt1 and Ref _ opt through one output terminal. It is understood that the number of the second control signals corresponds to the number of the fourth reading transistors T04 in the reference unit 804, and the level states of the second control signals can be set according to the sensitivity requirement. In this embodiment, the plurality of second control signals are used, so that the sensitivity characteristics of the reference cell 804 can be more flexibly controlled, and defects can be made by a card control process, thereby improving the reliability of the semiconductor memory.

Fig. 11 is a schematic structural diagram of an output unit according to an embodiment, and referring to fig. 11, in the embodiment, the output unit 808 includes two signal output circuits. The two signal output circuits are a first output circuit 8081 and a second output circuit 8082, and each signal output circuit includes a first input end, a second input end, and an output end. A first input terminal of the first output circuit 8081 is connected to the first node YIONloc, a first input terminal of the second output circuit 8082 is connected to the second node YIONloc, an output terminal of the first output circuit 8081 is connected to a second input terminal of the second output circuit 8082, and a second input terminal of the first output circuit 8081 is connected to an output terminal of the second output circuit 8082. A node at which the output end of the first output circuit 8081 is connected to the second input end of the second output circuit 8082 is used to output the read Data signal Data, and a connection node at which the second input end of the first output circuit 8081 is connected to the output end of the second output circuit 8082 is used to output an inverted signal of the read Data signal Data.

Specifically, the signal output circuit includes an eighth read transistor T08, a ninth read transistor T09, a tenth read transistor T10, and an eleventh read transistor T11. A control terminal of the eighth read transistor T08 serves as a first input terminal of the signal output circuit, a first terminal of the eighth read transistor T08 is connected to a high level, and a second terminal of the eighth read transistor T08 serves as an output terminal of the signal output circuit. A control terminal of the ninth reading transistor T09 is connected to a control terminal of the eighth reading transistor T08, and a first terminal of the ninth reading transistor T09 is connected to a second terminal of the eighth reading transistor T08. A control terminal of the tenth reading transistor T10 serves as a second input terminal of the signal output circuit, a first terminal of the tenth reading transistor T10 is connected to a second terminal of the eighth reading transistor T08, and a second terminal of the tenth reading transistor T10 is grounded. A control terminal of the eleventh read transistor T11 is connected to a control terminal of the tenth read transistor T10, a first terminal of the eleventh read transistor T11 is connected to a high level, and a second terminal of the eleventh read transistor T11 is connected to a second terminal of the eighth read transistor T08.

The operation principle of the output unit 808 will be explained based on the embodiment of fig. 11. If the level state of the first node yilon is high, the level state of the corresponding second node yilon is opposite, that is, the level state of the second node yilon is low. The low level of the second node YIOloc turns on the eighth transistor in the second output circuit 8082, thereby pulling down the inverted signal of the read Data signal Data to a low level, and accordingly, the read Data signal Data to a high level. If the level state of the first node YIONloc is low, the level state of the corresponding second node YIONloc is opposite, that is, the level state of the second node YIONloc is high. The low level of the first node YIONloc turns on the eighth transistor in the first output circuit 8081, thereby pulling high the read Data signal Data, and accordingly, the inverted signal of the read Data signal Data is low.

Fig. 12 is a second schematic structural diagram of the output unit according to the first embodiment, and referring to fig. 12, in the present embodiment, the output unit 808 further includes a first reset transistor T12 and a second reset transistor T13. The control end of the first reset transistor T12 is configured to receive an externally input reset signal, the first end of the first reset transistor T12 is connected to a high level, and the second end of the first reset transistor T12 is connected to the second end of the eighth read transistor. The control end of the second reset transistor T13 is configured to receive the reset signal, the first end of the second reset transistor T13 is connected to the second end of the tenth read transistor, and the second end of the second reset transistor T13 is grounded. By providing the reset transistor, the Data line for the read Data signal can be reset before Data reading, thereby improving the reliability of Data reading. Specifically, when the reset signal is at a low level, the first reset transistor T12 is turned on, pulling up the voltage on the readout Data signal Data line to a high level.

In one embodiment, the number of read transistors to which the first node YIONloc is connected is the same as the number of read transistors to which the second node YIONloc is connected. Illustratively, based on the second circuit of the embodiment of fig. 7, a third read transistor T03 may be further disposed in the input cell 802, such that the first node YIONloc is connected to four read transistors, and the second node YIONloc is also connected to four read transistors. Through the arrangement mode, the load capacitances on the first node YIONloc and the second node YIONloc can be equal, so that the charge conditions of the two nodes in the initial state are the same, the balance between the input unit 802 and the reference unit 804 is improved, and the global data signal YIO can be read more accurately.

Fig. 13 is a second schematic diagram of a partial structure of the second circuit according to an embodiment, referring to fig. 13, in this embodiment, an input unit 802, a pre-charging unit 806, and a pulse width adjusting unit 810 are the same as those in the embodiment of fig. 7, and a first control circuit 8022 and an output unit 808 of this embodiment may also correspond to fig. 9 to fig. 12, which are not repeated herein. The reference cell 804 of the present embodiment further includes a sixth reading transistor T06 and a second switch 8042. The control end of the sixth reading transistor T06 is configured to receive the reference data signal Ref, the first end of the sixth reading transistor T06 is configured to receive the enable adjustment signal, the second end of the sixth reading transistor T06 is connected to the first end of the fourth reading transistor T04, and the fourth reading transistor T04 receives the enable adjustment signal through the sixth reading transistor T06. Two ends of the second switch 8042 are respectively connected to the first end of the sixth reading transistor T06 and the second end of the sixth reading transistor T06 in a one-to-one correspondence manner.

Specifically, when the second switch 8042 is closed, the sixth reading transistor T06 is short-circuited, and the second terminal of the fourth reading transistor T04 can be understood as being directly connected to the pulse width adjusting unit 810, so that the enable adjustment signal output by the pulse width adjusting unit 810 can be rapidly transmitted to the fourth reading transistor T04. When the second switch 8042 is turned on, the sixth reading transistor T06 needs to be turned on or off in response to the reference data signal Ref, and if the reference data signal Ref controls the fourth reading transistor T04 and the sixth reading transistor T06 to be turned on, the enable adjustment signal also needs to pass through the sixth reading transistor T06 to be transmitted to the fourth reading transistor T04, so as to change the transmission speed of the enable adjustment signal. It is understood that the semiconductor memory includes a plurality of second circuits, and the signal transmission speeds of the different second circuits are not completely the same due to the difference of the process. Therefore, by providing the second switch 8042, the response speed of the second circuit can be adjusted more flexibly, thereby improving the reading performance of the semiconductor memory.

With continued reference to FIG. 13, in one embodiment, the reference cell 804 further includes a second control circuit 8041 and a seventh read transistor T07. The second control circuit 8041 is configured to generate a reference control signal according to the second control signal, and it is understood that the second control circuit 8041 of this embodiment may refer to the embodiment in fig. 10, and details are not repeated here. A control terminal of the seventh read transistor T07 is connected to the second control circuit 8041, a first terminal of the seventh read transistor T07 is connected to a first terminal of the sixth read transistor T06, and a second terminal of the seventh read transistor T07 is connected to a second terminal of the sixth read transistor T06. In this embodiment, the second control signal is used to control the sensitivity characteristic of the reference cell 804 more flexibly, and the defects can be made by the card control process, thereby improving the reliability of the semiconductor memory.

An embodiment of the present application further provides a data processing circuit as shown in fig. 1, where the data processing circuit includes: as the data transmission circuit 10 and the verification generation circuit 20, the verification generation circuit 20 is connected to the verification write circuit 200, and is configured to obtain data to be written, generate corresponding verification data according to the data to be written, and transmit the verification data to the verification write circuit 200. It can be understood that, for the data transmission circuit 10 of the present embodiment, reference may be made to the foregoing embodiments, and details are not repeated herein, and based on the foregoing data transmission circuit 10, the present application provides a data processing circuit with a faster processing speed and a faster transmission speed.

An embodiment of the present application further provides a memory, including: a data storage unit 400, a verification storage unit 500 and a data processing circuit as described above. It can be understood that, the data processing circuit of this embodiment may refer to the foregoing embodiments, and details are not repeated herein, and based on the foregoing data processing circuit, the present application provides a semiconductor memory with a faster data writing speed.

All possible combinations of the technical features of the above embodiments may not be described for the sake of brevity, but should be considered as within the scope of the present disclosure as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express a few embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for those skilled in the art, variations and modifications can be made without departing from the concept of the embodiments of the present application, and these embodiments are within the scope of the present application. Therefore, the protection scope of the embodiments of the present application shall be subject to the appended claims.

Claims

1. A data transmission circuit, comprising:

the verification write-in circuit is used for transmitting verification data to a global data line connected with a verification storage unit, the verification data corresponds to the data to be written, and the verification write-in circuit and the data write-in circuit are both first circuits;

the first circuit is used for responding to a pre-charging enabling signal and generating a pull-up enabling signal, and the pull-up enabling signal which is enabled to be effective controls the first pull-up circuit to output a global data signal; the first circuit is further used for responding to a write enable signal, generating a pull-up enable signal and a pull-down enable signal according to data to be written, transmitting the global data signal to a global data line, enabling the effective pull-down enable signal to control the first pull-down circuit to output the global data signal, and enabling the pull-up enable signal and the pull-down enable signal in a time-sharing manner;

the driving capacity of a first pull-up circuit in the data writing circuit is equal to that of a first pull-up circuit in the verification writing circuit, and the driving capacity of a first pull-down circuit in the verification writing circuit is stronger than that of the first pull-down circuit in the data writing circuit.

2. The data transmission circuit as claimed in claim 1, wherein the electrical parameters of the corresponding devices of the first pull-down circuit in the data writing circuit and the verification writing circuit are not identical, so that the driving capability of the first pull-down circuit in the verification writing circuit is stronger than that of the first pull-down circuit in the data writing circuit.

3. The data transmission circuit of claim 2,

the first pull-up circuit comprises a first pull-up transistor, the first pull-up transistor is conducted at a low level, a control end of the first pull-up transistor is used for receiving an inverted signal of the data to be written, and a first end of the first pull-up transistor is connected with a power supply voltage end;

the first pull-down circuit comprises a first pull-down transistor, the first pull-down transistor is conducted at a high level, a control end of the first pull-down transistor is used for receiving an inverted signal of the data to be written, a first end of the first pull-down transistor is connected with a grounding end, and a second end of the first pull-down transistor is connected with a second end of the first pull-up transistor;

4. The data transmission circuit of claim 3, wherein a channel width-to-length ratio of the first pull-up transistor in the verify write circuit is equal to a channel width-to-length ratio of the first pull-up transistor in the data write circuit.

5. The data transmission circuit of claim 3, wherein a threshold voltage of the first pull-up transistor in the verify write circuit is equal to a threshold voltage of the first pull-up transistor in the verify write circuit.

6. The data transmission circuit according to claim 3, wherein a threshold voltage of the first pull-down transistor in the verify write circuit is smaller than a threshold voltage of the first pull-down transistor in the verify write circuit.

7. The data transmission circuit of claim 3, wherein the data transmission circuit is configured with a precharge phase in which a precharge enable signal is asserted and a data write phase in which a write enable signal is asserted, the first circuit further comprising:

the logic operation unit is respectively connected with the first pull-up transistor and the first pull-down transistor and is used for responding to a write enable signal in the data writing stage and generating an inverted signal of data to be written;

and the NOT gate circuit is connected with the logic operation unit and used for receiving a pre-charging enabling signal and controlling the logic operation unit to output a low-level signal in the pre-charging stage.

8. The data transmission circuit according to claim 7, wherein the logic operation unit comprises:

the first input end of the first NOR gate circuit is connected with the output end of the AND gate circuit, the second input end of the first NOR gate circuit is connected with the output end of the NOT gate circuit, the pre-charging enabling signal is used for switching the data transmission circuit to a pre-charging stage or a data writing stage, and the output end of the first NOR gate circuit is connected with the control end of the first pull-up transistor.

9. The data transmission circuit of claim 8, wherein the output of the first nor gate circuit is further connected to the control terminal of the first pull-down transistor.

10. The data transmission circuit according to claim 8, wherein the logic operation unit further comprises:

the NAND gate circuit comprises a first input end and a second input end, wherein the first input end of the NAND gate circuit is used for receiving a pre-charging enabling signal, and the second input end of the NAND gate circuit is used for receiving a writing enabling signal;

and a second NOR gate circuit, wherein a first input end of the second NOR gate circuit is used for receiving data to be written, a second input end of the second NOR gate circuit is connected with an output end of the NAND gate circuit, and an output end of the second NOR gate circuit is connected with a control end of the first pull-down circuit.

11. The data transmission circuit according to claim 1, wherein the data write circuit and the verify write circuit respectively transmit the global data signals to the corresponding global data lines in response to a same write enable signal.

12. The data transmission circuit of claim 1, further comprising:

the verification reading circuit is used for acquiring stored verification data from a global data line connected with a verification storage unit so as to read the stored verification data, and the stored verification data corresponds to the stored data to be read;

wherein the driving capability of the verification reading circuit is equal to that of the data reading circuit.

13. The data transmission circuit as claimed in claim 12, wherein the circuit structures of the data reading circuit and the verification reading circuit are both second circuits, and the electrical parameters of the corresponding devices in the data reading circuit and the verification reading circuit are the same, so that the driving capability of the verification reading circuit is equal to that of the data reading circuit.

14. The data transmission circuit according to claim 13, wherein the global data line is further configured to transmit a read signal, a level state of the read signal is the same as a level state of the data to be read, and the second circuit includes:

a reference unit for receiving a reference data signal in response to the read enable signal;

the pre-charging unit is connected with the input unit and the reference unit and is used for responding to a pre-charging enabling signal and pre-charging the first node and the second node to a preset level respectively;

15. A data processing circuit, comprising:

a data transmission circuit as claimed in any one of claims 1 to 14;

16. A memory, comprising: a data storage unit, a check storage unit and a data processing circuit as claimed in claim 15.