CN115425110A - Manufacturing method of perovskite crystalline silicon laminated solar cell crystalline silicon bottom cell and cell - Google Patents
Manufacturing method of perovskite crystalline silicon laminated solar cell crystalline silicon bottom cell and cell Download PDFInfo
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
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- H01L31/02—Details
- H01L31/0216—Coatings
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- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/054—Optical elements directly associated or integrated with the PV cell, e.g. light-reflecting means or light-concentrating means
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- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
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Abstract
The invention discloses a manufacturing method of a perovskite crystalline silicon tandem solar cell crystalline silicon bottom cell and a cell, relating to the technical field of solar energy, wherein the method comprises the following steps: preparing a silicon wafer substrate; preparing a first passivation layer on the upper surface of a silicon wafer substrate; preparing a second passivation layer on the lower surface of the silicon wafer substrate; preparing a carrier selective transmission layer on the lower surface of the second passivation layer; preparing an antireflection layer on the lower surface of the carrier selective transmission layer; and preparing a metal bottom electrode layer on the lower surface of the antireflection layer. The invention relates to a manufacturing method of a perovskite crystalline silicon tandem solar cell crystalline silicon bottom cell and the cell, which meet the application requirements of the perovskite crystalline silicon tandem solar cell by reducing the input of indium materials in the crystalline silicon bottom cell.
Description
Technical Field
The invention relates to the technical field of solar energy, in particular to a manufacturing method of a crystalline silicon bottom cell of a perovskite crystalline silicon tandem solar cell and the cell.
Background
Solar cells are one of the most important technologies driving the revolution of renewable energy sources, and the research on solar cells has made a great progress in conversion efficiency. However, it is still necessary to improve the efficiency of photovoltaic modules. Higher photovoltaic modules can make the system more compact, thereby reducing the cost of the system.
In general, it is necessary to reduce absorption loss while maintaining or increasing the voltage of the photovoltaic cell. Furthermore, single junction solar cells have an upper efficiency limit (Shockley-queesser limit) beyond which the efficiency of single junction cells cannot exceed. In view of this, one of the strategies to improve the efficiency of photovoltaic cells is to use a tandem cell.
The tandem cell includes multiple (≧ 2) subcells composed of materials with different absorption properties, allowing more efficient use of different bands of light energy from the solar spectrum. In particular, the tandem cell combines an upper layer solar cell with a high efficiency wide band gap with a lower layer solar cell with a low band gap to improve the overall efficiency. The stack allows high-energy photons to be absorbed in the upper subcell (the top cell), which can generate a high voltage to reduce heat loss for the high-energy photons; and allows the lower subcell (bottom cell) to absorb low energy photons (having been transmitted through the upper subcell), facilitating energy collection of photons in different bands.
Due to their bandgap properties, crystalline silicon solar cells are often used as low-level subcells in stacks. The silicon heterojunction lower subcell dominates the stack study. In order to develop a stack structure suitable for commercial scale production, it is desirable to optimize the performance and cost of the lower subcell (i.e., the crystalline silicon bottom cell) and its compatibility with the subsequent processing steps to form the stack structure. For example, the consumption of indium is limited, the indium is distributed in the earth crust in a small amount and is dispersed, and the indium is listed as rare metal, which can be used in perovskite crystalline silicon tandem solar cells, and the use of indium material is involved in crystalline silicon bottom cells in perovskite crystalline silicon tandem solar cells, so that different crystalline silicon bottom cell schemes are necessary.
Disclosure of Invention
The invention aims to overcome the defects of the prior art, and provides a manufacturing method of a perovskite crystalline silicon tandem solar cell crystalline silicon bottom cell and a cell.
In order to solve the above problems, the present invention provides a method for manufacturing a crystalline silicon bottom cell of a perovskite crystalline silicon tandem solar cell, wherein the method comprises:
preparing a silicon wafer substrate, wherein the thickness of the silicon wafer substrate is between 100 and 500 micrometers, the silicon wafer substrate is made of N-type silicon or P-type silicon, and the resistivity of the silicon wafer substrate is between 0.1 and 20ohm cm;
preparing a first passivation layer on the upper surface of a silicon wafer substrate, wherein the first passivation layer comprises a first doped polycrystalline silicon layer and a first tunneling silicon oxide layer, the thickness of the first doped polycrystalline silicon layer is 0-135nm, and the thickness of the first tunneling silicon oxide layer is 0-15 nm;
preparing a second passivation layer on the lower surface of the silicon wafer substrate, wherein the thickness of the second passivation layer is between 0 and 135 nm;
a carrier selective transmission layer is arranged on the lower surface of the second passivation layer, and the thickness of the carrier selective transmission layer is between 0 and 200 nm;
preparing an antireflection layer on the lower surface of the carrier selective transmission layer, wherein the thickness of the antireflection layer is between 0 and 300 nm;
and preparing a metal bottom electrode layer on the lower surface of the antireflection layer, wherein the thickness of the metal bottom electrode layer is 1-2000 mu m.
A suede structure or a polished surface structure is prepared on the upper surface of the silicon wafer substrate, and a suede structure or a polished surface structure is prepared on the lower surface of the silicon wafer substrate;
the preparation of the suede structure is completed through an alkali suede technology, and the surface roughness Ra of the suede structure is less than 2; the preparation of the polished surface structure is completed by an acid polishing process, an alkali polishing process or a mechanical polishing process, and the surface roughness Ra of the polished surface structure is less than 0.2.
The preparation of the first passivation layer on the upper surface of the silicon wafer substrate comprises the following steps:
when preparing the first passivation layer based on the N-type doped polycrystalline silicon layer, controlling the thickness of the N-type doped polycrystalline silicon layer in the first passivation layer to be 0-120nm and the doping concentration to be 8 x 10 18 cm -3 To 1.5 x 10 21 cm -3 The square resistance is 20-150 omega/\9633; or when preparing the first passivation layer based on the P-type doped polycrystalline silicon layer, controlling the thickness of the P-type doped polycrystalline silicon layer in the first passivation layer to be 0-120nm and the doping concentration to be 8 x 10 18 cm -3 To 3 x 10 21 cm -3 The square resistance is 20-150 omega/\9633;
and when the first tunneling silicon oxide layer is prepared, controlling the thickness of the first tunneling silicon oxide layer to be 0-15nm.
The preparing of the second passivation layer on the lower surface of the silicon wafer substrate comprises:
when the first passivation layer is prepared on the basis of the N-type doped polycrystalline silicon layer, the second passivation layer is prepared on the basis of the P-type doped polycrystalline silicon layer or the P-type diffusion doping layer, and the sheet resistance of the N-type doped polycrystalline silicon layer or the N-type diffusion doping layer is 20-150 omega/9633; or when the first passivation layer is prepared on the basis of the P-type doped polycrystalline silicon layer, the second passivation layer is prepared on the basis of the N-type doped polycrystalline silicon layer or the N-type diffusion doping layer, and the sheet resistance of the N-type doped polycrystalline silicon layer or the N-type diffusion doping layer is 20-150 omega/9633.
The preparing of the second passivation layer on the lower surface of the silicon wafer substrate comprises:
when preparing the second passivation layer based on the N-type doped polycrystalline silicon layer, the thickness of the N-type doped polycrystalline silicon layer in the second passivation layer is controlled to be 0-120nm, and the doping concentration is controlled to be 8 x 10 18 cm -3 To 1.5 x 10 21 cm -3 The square resistance is 20-150 omega/\9633; or when preparing the second passivation layer based on the P-type doped polysilicon layer, controlling the thickness of the P-type doped polysilicon layer in the second passivation layer to be 0-120nm and the doping concentration to be 8 x 10 18 cm -3 To 3 x 10 21 cm -3 The square resistance is 20-150 omega/\9633;
and when the second tunneling silicon oxide layer is prepared, controlling the thickness of the second tunneling silicon oxide layer to be 0-15nm.
The preparing of the carrier selective transmission layer on the lower surface of the second passivation layer comprises: preparing a carrier selective transmission layer by ALD or PVD;
the carrier selective transport layer includes an electron selective transport layer or a hole selective transport layer. The preparation material of the electron selective transmission layer comprises one or more of ZnO, taOx, tiOx, snOx, tiNx, zrO2, tiSnOx, snZnOx and derivatives thereof; the preparation material of the hole selective transport layer comprises one or more of MoOx, WOx, VOx, cu2O, cuI and derivatives thereof.
Correspondingly, the invention also provides a crystalline silicon bottom cell, which is applied to the perovskite crystalline silicon tandem solar cell, and comprises:
the thickness of the silicon wafer substrate is between 100 and 500 micrometers, the silicon wafer substrate is made of N-type silicon or P-type silicon, and the resistivity of the silicon wafer substrate is between 0.1 and 20ohm cm;
the first passivation layer is positioned on the upper surface of the silicon wafer substrate and comprises a doped polycrystalline silicon layer and a first tunneling silicon oxide layer, the thickness of the first passivation layer is between 0 and 135nm, and the thickness of the first tunneling silicon oxide layer is between 0 and 15 nm;
the second passivation layer is positioned on the lower surface of the silicon wafer substrate, and the thickness of the second passivation layer is between 0 and 135 nm;
the carrier selective transmission layer is positioned on the lower surface of the second passivation layer carrier selective transmission layer, and the thickness of the carrier selective transmission layer is between 0 and 200 nm;
the antireflection layer is positioned on the lower surface of the carrier selective transmission layer, and the thickness of the antireflection layer is between 0 and 300 nm;
the metal bottom electrode layer is located on the lower surface of the antireflection layer, and the thickness of the metal bottom electrode layer is 1-2000 mu m.
When preparing the first passivation layer based on the N-type doped polycrystalline silicon layer, the thickness of the N-type doped polycrystalline silicon layer in the first passivation layer is 0-120nm, and the doping concentration is 8 x 10 18 cm -3 To 1.5 x 10 21 cm -3 (ii) a Or when preparing the first passivation layer based on the P-type doped polycrystalline silicon layer, the thickness of the P-type doped polycrystalline silicon layer in the first passivation layer is 0-120nm, and the doped polycrystalline silicon layer is doped with nitrogenImpurity concentration 8 x 10 18 cm -3 To 3 x 10 21 cm -3 ；
The thickness of the first tunneling silicon oxide layer of the first passivation layer is 0-15nm.
When the first passivation layer comprises an N-type doped polycrystalline silicon layer, the second passivation layer comprises a P-type doped polycrystalline silicon layer or a P-type diffusion doping layer; the thickness of the N-type doped polysilicon layer in the second passivation layer is 0-120nm, and the doping concentration is 8 x 10 18 cm -3 To 1.5 x 10 21 cm -3 ；
Or when the first passivation layer comprises a P-type doped polycrystalline silicon layer, the second passivation layer is prepared on the basis of an N-type doped polycrystalline silicon layer or an N-type diffusion doping layer; the P-type doped polysilicon layer in the second passivation layer has a thickness of 0-120nm and a doping concentration of 8 × 10 18 cm -3 To 3 x 10 21 cm -3 ；
The thickness of the second tunneling silicon oxide layer is 0-15nm.
The metal bottom electrode layer is of a full-coverage structure or a grid line structure.
According to the crystalline silicon bottom cell and the manufacturing method thereof, the use of indium materials can be reduced, the crystalline silicon bottom cell is used as a part of the perovskite crystalline silicon tandem solar cell, the use of the perovskite crystalline silicon tandem solar cell can be promoted, the commercialization efficiency is improved, and the absorption capacity of the crystalline silicon bottom cell is enhanced by adding the antireflection layer. The crystalline silicon bottom cell with the structure is prepared from conventional materials, the use of noble metal indium materials can be reduced, the cost of the crystalline silicon bottom cell is reduced, the application of the crystalline silicon bottom cell in a perovskite crystalline silicon tandem solar cell is popularized, and the subsequent process steps for forming the tandem structure have higher compatibility.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic view of a first structure of a perovskite crystalline silicon tandem solar cell crystalline silicon bottom cell in an embodiment of the invention;
FIG. 2 is a schematic diagram of a second structure of a perovskite crystalline silicon tandem solar cell crystalline silicon bottom cell in an embodiment of the invention;
FIG. 3 is a schematic diagram of a third structure of a perovskite crystalline silicon tandem solar cell crystalline silicon bottom cell in an embodiment of the invention;
FIG. 4 is a schematic diagram of a fourth structure of a perovskite crystalline silicon tandem solar cell crystalline silicon bottom cell in an embodiment of the invention;
FIG. 5 is a schematic diagram of a fifth configuration of a perovskite crystalline silicon tandem solar cell crystalline silicon bottom cell in an embodiment of the present invention;
FIG. 6 is a schematic diagram of a sixth configuration of a perovskite crystalline silicon tandem solar cell crystalline silicon bottom cell in an embodiment of the present invention;
fig. 7 is a flowchart of a method for manufacturing a crystalline silicon bottom cell of a perovskite crystalline silicon tandem solar cell in an embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Specifically, fig. 1 shows a first structural schematic diagram of a perovskite crystalline silicon tandem solar cell crystalline silicon bottom cell in an embodiment of the present invention, and fig. 2 shows a second structural schematic diagram of a perovskite crystalline silicon tandem solar cell crystalline silicon bottom cell in an embodiment of the present invention, where the crystalline silicon bottom cell includes: silicon chip base, first passivation layer, second passivation layer, carrier selective transmission layer, antireflection layer, metal bottom electrode layer, wherein:
the silicon wafer substrate is made of N-type silicon or P-type silicon, the upper surface and the lower surface of the silicon wafer substrate are of a suede structure or a polished surface structure, a first passivation layer playing a passivation effect is arranged on the upper surface of the silicon wafer substrate, and a second passivation layer playing a passivation effect is arranged on the lower surface of the silicon wafer substrate;
the lower surface of the second passivation layer is provided with a carrier selective transmission layer, the lower surface of the carrier selective transmission layer is provided with an antireflection layer, and the lower surface of the antireflection layer is provided with a metal bottom electrode layer.
The metal bottom electrode layer may be a full-coverage structure or a gate line structure, such as the metal bottom electrode layer with the full-coverage structure shown in fig. 1, and the metal electrode layer with the gate line structure shown in fig. 2.
Here, the first passivation layer includes a doped polysilicon layer and a first tunnel silicon oxide layer, the second passivation layer includes a doped polysilicon layer and a second tunnel silicon oxide layer, or the second passivation layer includes a diffusion doping layer. The polarity of the first passivation layer is opposite to that of the second passivation layer, namely when the first passivation layer comprises an N-type doped polycrystalline silicon layer, the second passivation layer comprises a P-type doped polycrystalline silicon layer or a P-type diffusion doping layer, and the sheet resistance of the P-type doped polycrystalline silicon layer or the P-type diffusion doping layer is 20-150 omega/\9633; or when the first passivation layer comprises a P-type doped polysilicon layer, the second passivation layer comprises an N-type doped polysilicon layer or an N-type diffusion doping layer, and the sheet resistance of the N-type doped polysilicon layer or the N-type diffusion doping layer is 20-150 omega/9633. Here, the doped polysilicon layer may be prepared by a PECVD or LPCVD process, and the diffusion doping layer may be prepared by a tube type diffusion furnace.
Fig. 3 shows a schematic third structure of a perovskite-crystalline silicon tandem solar cell silicon bottom cell in an embodiment of the present invention, where the first passivation layer comprises an N-type doped polysilicon layer and a first tunneling silicon oxide layer, where the second passivation layer comprises a P-type doped polysilicon layer and a second tunneling silicon oxide layer, wherein: the first tunneling silicon oxide layer is positioned between the N-type doped polycrystalline silicon layer and the silicon wafer substrate, and the second tunneling silicon oxide layer is positioned between the P-type doped polycrystalline silicon layer and the silicon wafer substrate.
Fig. 4 shows a fourth schematic structure diagram of a perovskite crystalline silicon tandem solar cell crystalline silicon bottom cell in an embodiment of the present invention, where the first passivation layer comprises a P-type doped polysilicon layer and a first tunneling silicon oxide layer, and where the second passivation layer comprises an N-type doped polysilicon layer and a second tunneling silicon oxide layer, wherein: the first tunneling silicon oxide layer is positioned between the P-type doped polycrystalline silicon layer and the silicon wafer substrate, and the second tunneling silicon oxide layer is positioned between the N-type doped polycrystalline silicon layer and the silicon wafer substrate.
Fig. 5 shows a fifth structural schematic diagram of a crystalline silicon bottom cell of a perovskite crystalline silicon tandem solar cell in an embodiment of the invention, where the first passivation layer comprises an N-type doped polysilicon layer and a first tunneling silicon oxide layer, where the second passivation layer comprises a P-type diffused doped layer, wherein: the first tunneling silicon oxide layer is positioned between the N-type doped polycrystalline silicon layer and the silicon wafer substrate.
Fig. 6 shows a fifth structural schematic diagram of a crystalline silicon bottom cell of a perovskite crystalline silicon tandem solar cell in an embodiment of the invention, where the first passivation layer comprises a P-type doped polysilicon layer and a first tunneling silicon oxide layer, where the second passivation layer comprises an N-type diffusion doped layer, wherein: the first tunneling silicon oxide layer is positioned between the P-type doped polycrystalline silicon layer and the silicon wafer substrate.
The carrier selective transport layer includes Al 2 O 3 The anti-reflection layer is SiN x (silicon nitride) or SiN x O y (silicon oxynitride) and the like.
The first passivation layer is a poly-silicon Oxide (POLO) structure formed by combining doped polysilicon and tunneling silicon Oxide, and the second passivation layer may be a POLO structure formed by combining doped polysilicon and tunneling silicon Oxide, or a diffusion doping layer formed by diffusion.
The doped polysilicon layer can be prepared by the following methods:
1. preparing an undoped polysilicon layer by LPCVD (low pressure chemical vapor deposition) + ion implantation doping;
2. preparing an undoped polysilicon layer by LPCVD (low pressure chemical vapor deposition) + thermal diffusion doping;
3. in-situ doping LPCVD to prepare a doped polycrystalline silicon layer;
4. preparing a doped polycrystalline silicon layer by PECVD;
5. PEALD produces a doped polysilicon layer.
The diffusion doped layer can be prepared by: thermal diffusion or ion implantation is used to prepare the doped layer.
The silicon wafer substrate has a thickness of 100 μm to 500 μm and a resistivity of 0.1ohm cm to 20ohm cm. The upper surface of the silicon chip is of a suede structure or a polished surface structure, and the lower surface of the silicon chip is of a suede structure or a polished surface structure.
The suede structure can be prepared by an alkali texturing process, and the surface roughness Ra of the suede structure is less than 2. The chemical used in the alkali texturing process is one or more of NaOH, KOH and surfactant, and the process time is 0-60 minutes.
The polished surface structure, namely the planar structure, can be prepared by acid polishing, alkali polishing and mechanical polishing processes, and the surface roughness Ra of the polished surface structure is less than 0.2.
It should be noted that the material of the carrier selective transport layer is one or more of SiOx, al2O3, alN, inSb, siC, tiOx, and TiN, and the passivation layer may be a single layer or a stack of dielectric layers, such as SiOx/AlOx, with a thickness of 0-200nm. The carrier selective transport layer herein may be prepared by ALD or PECVD.
The antireflection layer is made of Al 2 O 3 、SiN x 、SiN x O y 、MgF 2 One or more of LiF, the antireflection layer may be a single layer or a stack of dielectric layers, such as SiO x Or SiN x The thickness is 0-300nm.
The anti-reflective layer extends between portions of the upper electrode. The AR coating in the antireflective layer, which may reduce reflection from the surface of the silicon substrate, is formed using two or more sub-layers, one of which is a barrier layer that may have antireflective properties. I.e. the AR coating may comprise a stack comprising a dielectric layer and a barrier layer. In the specific implementation process, the material can be TiO x (Barrier layer) and SiO x Composed stackAR functionality may be provided. In particular implementations, stacks may also be used to form the antireflective layer, i.e., the AR coating may optimize the thickness of the coating and/or barrier layer to enhance absorption by the silicon solar cell. Other sub-layers forming the AR coating may be deposited on top of the barrier layer, between the individual elements of the electrode, the barrier layer will be deposited between the electrode and the internal layers of the cell, and the other sub-layers will extend between the electrode portions overlying the barrier layer. The antireflective layer may comprise SiN x (silicon nitride) or SiN x O y (silicon oxynitride).
It should be noted that the thickness of the P-type doped polysilicon layer is 0-120nm, and the doping concentration is 8 x 10 18 cm -3 To 3 x 10 21 cm -3 。
It should be noted that the P-type doped polysilicon layer can be prepared by PECVD in-situ doping, LPCVD in-situ doping or thermal diffusion process.
The thermal diffusion process is to dope the P-type polysilicon layer with a P-type dopant to produce a P-type doped layer; and configuring the precursor and the other precursor back to prepare the P-type doped polycrystalline silicon layer.
The thermal diffusion process preparation process involves the use of high temperatures to increase the diffusivity to speed up the reactions required for the P-doped polysilicon layer to form the desired P-doped polysilicon layer in a shorter time. Not only the desired reaction but also undesired reactions are accelerated by the thermal diffusion process. During the preparation process, a portion of the precursor is contaminated with a dopant, and the silicon-based charge transport layer obtains its transport characteristics by incorporating a specific dopant (P-type) into the silicon. The preparation of the P-type doped polysilicon layer is carried out based on boron diffusion, the boron diffusion process needs higher temperature for diffusion, and the formed borosilicate glass can cause the layer to lose the specific charge transmission characteristics, the BSG layer of the borosilicate glass can be removed by a wet chemical method, the BSG layer is etched for 10-100min by using NaOH or KOH solution, and the formation of the BSG layer can be avoided to a great extent by arranging a precursor and another precursor back to back in a diffusion furnace.
It should be noted that, here, the thickness of the N-type doped polysilicon layer0-120nm, and doping concentration of 8 x 10 18 cm -3 To 1.5 x 10 21 cm -3 。
The N-type doped polysilicon layer herein may be prepared by PECVD in-situ doping, LPCVD in-situ doping or thermal diffusion processes.
The thermal diffusion process is to dope the N-type polycrystalline silicon layer with N-type dopant to generate an N-type doped layer; and configuring the precursor and the other precursor back to prepare the N-type doped polycrystalline silicon layer.
The thermal diffusion process involves the use of high temperatures to increase the diffusivity to speed up the desired reaction to form the desired N-doped polysilicon layer in a shorter time. The thermal diffusion process not only accelerates the desired reaction, but also accelerates undesired reactions. During the preparation process, a portion of the precursor is contaminated with dopants. Silicon-based charge transport layers achieve their transport properties by incorporating specific dopants (N-type) into the silicon. The preparation of the N-type doped polysilicon layer is carried out based on boron diffusion, the boron diffusion process needs higher temperature for diffusion, the formed borosilicate glass can cause the layer to lose the specific charge transmission characteristics, the BSG layer of the borosilicate glass can be removed by a wet chemical method, the etching is carried out for 10-100min by using NaOH or KOH solution, and the formation of the BSG layer can be avoided to a great extent by arranging the precursor and another precursor back to back in a diffusion furnace.
Here the first tunnel silicon oxide layer and the first tunnel silicon oxide layer have a thickness of 0-15nm. The silicon oxide layer can be produced here by thermal oxidation, wet-chemical methods, wet-oxygen methods or by applying ultraviolet radiation in an ozone atmosphere.
The metal bottom electrode layer is made of one or more of aluminum, silver, titanium, palladium, nickel, chromium, tin or copper, the thickness of the metal bottom electrode layer is 1-2000 mu m, and the metal bottom electrode layer can be prepared by one or more of PVD, screen printing and electroplating.
The embodiment of the invention relates to a manufacturing method of a perovskite crystalline silicon tandem solar cell crystalline silicon bottom cell, which comprises the following steps: preparing a first passivation layer on the upper surface of a silicon wafer substrate, and preparing a second passivation layer on the lower surface of the silicon wafer substrate, wherein the surface of the silicon wafer substrate has a textured structure or a polished surface structure, the thickness of the silicon wafer substrate is controlled to be between 100 and 500 micrometers, and the resistivity of the silicon wafer substrate is between 0.1 and 20ohm cm; preparing a carrier selective transmission layer on the lower surface of the second passivation layer, wherein the thickness of the carrier selective transmission layer is controlled to be between 0nm and 300 nm; preparing an antireflection layer on the lower surface of the carrier selective transmission layer, wherein the thickness of the antireflection layer is controlled to be 0-300 nm; and preparing a metal bottom electrode layer on the lower surface of the antireflection layer.
Specifically, fig. 7 shows a flowchart of a manufacturing method of a crystalline silicon bottom cell of a perovskite crystalline silicon tandem solar cell in an embodiment of the present invention, which includes the following steps:
s701, preparing a silicon wafer substrate;
the method comprises the steps of preparing a silicon wafer substrate from N-type silicon or P-type silicon, and preparing a textured structure or a polished surface structure on the upper surface and the lower surface of the silicon wafer substrate.
The thickness of the silicon wafer substrate needs to be controlled to be between 100 μm and 500 μm, for example, the thickness can be: 100 μm, 150 μm, 200 μm, 300 μm, 400 μm, 500 μm, etc., and controlling the resistivity of the silicon wafer substrate to be between 0.1ohm cm and 20ohm cm, for example, the resistivity can be: 0.1 ohm-cm, 0.2 ohm-cm, 0.5 ohm-cm, 1 ohm-cm, 2 ohm-cm, 5 ohm-cm, 10 ohm-cm, 15 ohm-cm, 20 ohm-cm, and the like.
The preparation of the suede structure can be completed by an alkali suede technology, and the surface roughness Ra of the suede structure is less than 2. The chemical used in the alkali wool making process is one or more of NaOH, KOH and surfactant, and the process time is 0-60 minutes.
The preparation of the polished surface structure, namely the planar structure, can be completed by an acid polishing process, an alkali polishing process or a mechanical polishing process, wherein the surface roughness Ra of the polished surface structure, namely the planar structure, is less than 0.2.
S702, preparing a first passivation layer on the upper surface of a silicon wafer substrate;
the first passivation layer includes a doped polysilicon layer and a first tunneling silicon oxide layer, where the doped polysilicon layer and the first tunneling silicon oxide layer are to be prepared. The method comprises the steps of preparing a first tunneling silicon oxide layer on the upper surface of a silicon wafer substrate, and preparing a doped polycrystalline silicon layer of a first passivation layer on the upper surface of the first tunneling silicon oxide layer; or preparing the first passivation layer on the upper surface of the silicon chip substrate after preparing the first passivation layer based on the first passivation layer doped polycrystalline silicon layer and the first tunneling silicon oxide layer. The thickness of the first passivation layer is any value between 0 and 135 nm.
When preparing the first passivation layer based on the N-type doped polysilicon layer, the thickness of the N-type doped polysilicon layer is controlled to be 0-120nm, and the doping concentration is controlled to be 8 x 10 18 cm -3 To 1.5 x 10 21 cm -3 The square resistance is 20-150 omega/\9633;. The N-type doped polysilicon layer can be prepared by PECVD in-situ doping, LPCVD in-situ doping or thermal diffusion processes. The thermal diffusion process is to dope the N-type polycrystalline silicon layer with N-type dopant to generate an N-type doped layer; and configuring the precursor and the other precursor back to prepare the N-type doped polycrystalline silicon layer.
When preparing the first passivation layer based on the P-type doped polysilicon layer, the thickness of the P-type doped polysilicon layer is controlled to be 0-120nm, and the doping concentration is controlled to be 8 x 10 18 cm -3 To 3 x 10 21 cm -3 The sheet resistance is 20-150 omega/9633the P-type doped polysilicon layer can be prepared by PECVD in-situ doping, LPCVD in-situ doping or thermal diffusion process. The thermal diffusion process is to dope the P-type polysilicon layer with a P-type dopant to produce a P-type doped layer; and configuring the precursor and the other precursor back to prepare the P-type doped polycrystalline silicon layer.
Here, the thickness of the first tunneling silicon oxide layer needs to be controlled to be 0-15nm, and the thickness of the first tunneling silicon oxide layer can be 0.2nm, 0.5nm, 1nm, 3nm, 5nm, 8nm, 10nm, 11nm, 15nm, and the like. The first tunneling silicon oxide layer may be prepared by thermal oxidation, or wet chemical, or wet oxygen, or by applying ultraviolet radiation in an ozone environment.
S703, preparing a second passivation layer on the lower surface of the silicon wafer substrate;
the second passivation layer may include a doped polysilicon layer and a second tunnel silicon oxide layer, where the doped polysilicon layer and the first tunnel silicon oxide layer are to be formed. A second tunneling silicon oxide layer is prepared on the lower surface of a silicon wafer substrate, and a doped polycrystalline silicon layer of a second passivation layer is prepared on the lower surface of the second tunneling silicon oxide layer; or preparing a second passivation layer on the basis of the second passivation layer doped polycrystalline silicon layer and the second tunneling silicon oxide layer, and then preparing the second passivation layer on the upper surface of the silicon chip substrate. The doped polysilicon layer here may be a P-type doped polysilicon layer or an N-type doped polysilicon layer.
The second passivation layer here includes a diffusion doping layer, which may be a P-type diffusion doping layer or an N-type diffusion doping layer.
When the first passivation layer is prepared on the basis of the N-type doped polycrystalline silicon layer, the second passivation layer is prepared on the basis of the P-type doped polycrystalline silicon layer or the P-type diffusion doping layer, and the sheet resistance of the P-type doped polycrystalline silicon layer or the P-type diffusion doping layer is 20-150 omega/9633; when the first passivation layer is prepared based on the P-type doped polysilicon layer, the second passivation layer is prepared based on the N-type doped polysilicon layer or the N-type diffusion doping layer having a sheet resistance of 20-150 Ω/9633where it is required to control the polarities of the first passivation layer and the second passivation layer to be opposite.
When preparing the second passivation layer based on the N-type doped polysilicon layer, the thickness of the N-type doped polysilicon layer is controlled to be 0-120nm, and the doping concentration is 8 x 10 18 cm -3 To 1.5 x 10 21 cm -3 . The N-type doped polysilicon layer herein may be prepared by PECVD in-situ doping, LPCVD in-situ doping or thermal diffusion processes. The thermal diffusion process is to dope the N-type polycrystalline silicon layer with an N-type dopant to produce an N-type doped layer; and configuring the precursor and the other precursor back to prepare the N-type doped polycrystalline silicon layer.
When preparing the second passivation layer based on the P-type doped polysilicon layer, the thickness of the P-type doped polysilicon layer is controlled to be 0-120nm, and the doping concentration is controlled to be 8 x 10 18 cm -3 To 3 x 10 21 cm -3 The P-type doped polysilicon layer may be prepared by PECVD in-situ doping, LPCVD in-situ doping or thermal diffusion processes. The thermal diffusion process isDoping the P-type polysilicon layer with a P-type dopant to produce a P-type doped layer; and configuring the precursor and the other precursor back to prepare the P-type doped polycrystalline silicon layer.
The thickness of the second tunneling silicon oxide layer is controlled to be 0-15nm, and the thickness of the second tunneling silicon oxide layer can be 0.2nm, 0.5nm, 1nm, 3nm, 5nm, 8nm, 10nm, 11nm, 15nm, and the like. The second tunneling silicon oxide layer may be prepared by thermal oxidation, or wet chemical, or wet oxygen, or by applying ultraviolet radiation in an ozone environment.
Here, the N-type diffusion doping layer or the P-type diffusion doping layer may be prepared by thermal diffusion.
S704, preparing a carrier selective transmission layer on the lower surface of the second passivation layer;
the material of the carrier selective transmission layer is one or more of SiOx, al2O3, alN, inSb, siC, tiOx and TiN, and the passivation layer can be a single layer or a stack of dielectric layers, such as SiOx/AlOx, and has a thickness of 0-200nm.
The carrier selective transport layer here can be produced by ALD or PECVD, i.e. the carrier selective transport layer here is produced by ALD or PECVD.
S705, preparing an antireflection layer on the lower surface of the carrier selective transmission layer;
the material for preparing the antireflection layer is Al 2 O 3 、SiN x 、SiN x O y 、MgF 2 One or more of LiF, and the antireflection layer may be a single layer or a stack of dielectric layers, such as SiO x Or SiN x The thickness is 0-300nm.
The anti-reflective layer extends between portions of the upper electrode. The AR coating in the antireflective layer, which may reduce reflection from the surface of the silicon substrate, is formed using two or more sub-layers, one of which is a barrier layer that may have antireflective properties. I.e. the AR coating may comprise a stack comprising a dielectric layer and a barrier layer. In the specific implementation process, the material can be TiO x (Barrier layer) and SiO x The composed stack may provide AR functionality.In particular implementations, stacks may also be used to form the antireflective layer, i.e., the AR coating may optimize the thickness of the coating and/or barrier layer to enhance absorption by the silicon solar cell. Other sub-layers forming the AR coating may be deposited on top of the barrier layer, between the individual elements of the electrode, the barrier layer will be deposited between the electrode and the internal layers of the cell, and the other sub-layers will extend between the electrode portions overlying the barrier layer. The antireflective layer may comprise SiN x (silicon nitride) or SiN x O y (silicon oxynitride).
S706, preparing a metal bottom electrode layer on the lower surface of the antireflection layer.
The metal bottom electrode layer is made of one or more of aluminum, silver, titanium, palladium, nickel, chromium, tin or copper, the thickness of the metal bottom electrode layer is 1-2000 mu m, and the metal bottom electrode layer can be prepared by one or more of PVD, screen printing and electroplating.
According to the crystalline silicon bottom cell and the manufacturing method thereof, the use of indium materials can be reduced, the crystalline silicon bottom cell can be used as a part of a perovskite crystalline silicon laminated solar cell, the use of the perovskite crystalline silicon laminated solar cell can be promoted, the commercialization efficiency is improved, and the absorption capacity of the crystalline silicon bottom cell is enhanced by adding the antireflection layer. The crystalline silicon bottom cell with the structure is prepared from conventional materials, the use of noble metal indium materials can be reduced, the cost of the crystalline silicon bottom cell is reduced, the application of the crystalline silicon bottom cell in a perovskite crystalline silicon tandem solar cell is popularized, and the subsequent process steps for forming the tandem structure have higher compatibility.
The above embodiments of the present invention are described in detail, and the principle and the implementation of the present invention are described herein by using specific embodiments, and the description of the above embodiments is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (10)
1. A manufacturing method of a crystalline silicon bottom cell of a perovskite crystalline silicon tandem solar cell is characterized by comprising the following steps:
preparing a silicon wafer substrate, wherein the thickness of the silicon wafer substrate is between 100 and 500 micrometers, the silicon wafer substrate is made of N-type silicon or P-type silicon, and the resistivity of the silicon wafer substrate is between 0.1 and 20ohm cm;
preparing a first passivation layer on the upper surface of a silicon wafer substrate, wherein the first passivation layer comprises a first doped polycrystalline silicon layer and a first tunneling silicon oxide layer, the thickness of the first doped polycrystalline silicon layer is between 0 and 135nm, and the thickness of the first tunneling silicon oxide layer is between 0 and 15 nm;
preparing a second passivation layer on the lower surface of the silicon wafer substrate, wherein the thickness of the second passivation layer is between 0 and 135 nm;
preparing a carrier selective transmission layer on the lower surface of the second passivation layer, wherein the thickness of the carrier selective transmission layer is between 0 and 200 nm;
preparing an antireflection layer on the lower surface of the carrier selective transmission layer, wherein the thickness of the antireflection layer is between 0 and 300 nm;
and preparing a metal bottom electrode layer on the lower surface of the antireflection layer, wherein the thickness of the metal bottom electrode layer is 1-2000 mu m.
2. The manufacturing method of the perovskite crystalline silicon tandem solar cell crystalline silicon bottom cell as claimed in claim 1, wherein a textured structure or a polished surface structure is prepared on the upper surface of the silicon wafer substrate, and a textured structure or a polished surface structure is prepared on the lower surface of the silicon wafer substrate;
the preparation of the suede structure is finished through an alkaline suede making process, and the surface roughness Ra of the suede structure is less than 2; the preparation of the polished surface structure is completed by an acid polishing process, an alkali polishing process or a mechanical polishing process, and the surface roughness Ra of the polished surface structure is less than 0.2.
3. The method for fabricating a perovskite-crystalline silicon tandem solar cell crystalline silicon bottom cell as claimed in claim 1, wherein the step of preparing a first passivation layer on the upper surface of the silicon wafer substrate comprises:
when preparing the first passivation layer based on the N-type doped polycrystalline silicon layer, controlling the thickness of the N-type doped polycrystalline silicon layer in the first passivation layer to be 0-120nm and the doping concentration to be 8 x 10 18 cm -3 To 1.5 x 10 21 cm -3 The square resistance is 20-150 omega/\9633; or when preparing the first passivation layer based on the P-type doped polycrystalline silicon layer, controlling the thickness of the P-type doped polycrystalline silicon layer in the first passivation layer to be 0-120nm and the doping concentration to be 8 x 10 18 cm -3 To 3 x 10 21 cm -3 The square resistance is 20-150 omega/\9633;
and when the first tunneling silicon oxide layer is prepared, controlling the thickness of the first tunneling silicon oxide layer to be 0-15nm.
4. The method for manufacturing a perovskite crystalline silicon tandem solar cell crystalline silicon bottom cell as claimed in claim 3, wherein the step of preparing the second passivation layer on the lower surface of the silicon wafer substrate comprises the following steps:
when the first passivation layer is prepared on the basis of the N-type doped polycrystalline silicon layer, the second passivation layer is prepared on the basis of the P-type doped polycrystalline silicon layer or the P-type diffusion doping layer, and the sheet resistance of the P-type doped polycrystalline silicon layer or the P-type diffusion doping layer is 20-150 omega/9633; or when the first passivation layer is prepared on the basis of the P-type doped polycrystalline silicon layer, the second passivation layer is prepared on the basis of the N-type doped polycrystalline silicon layer or the N-type diffusion doping layer, and the sheet resistance of the N-type doped polycrystalline silicon layer or the N-type diffusion doping layer is 20-150 omega/9633.
5. The method for manufacturing a crystalline silicon bottom cell of a perovskite crystalline silicon tandem solar cell as claimed in claim 4, wherein the step of preparing a second passivation layer on the lower surface of the silicon wafer substrate comprises the steps of:
when preparing the second passivation layer based on the N-type doped polycrystalline silicon layer, the thickness of the N-type doped polycrystalline silicon layer in the second passivation layer is controlled to be 0-120nm, and the doping concentration is controlled to be 8 x 10 18 cm -3 To 1.5 x 10 21 cm -3 Square resistance of20-150 omega/\ 9633; or when preparing the second passivation layer based on the P-type doped polysilicon layer, controlling the thickness of the P-type doped polysilicon layer in the second passivation layer to be 0-120nm and the doping concentration to be 8 x 10 18 cm -3 To 3 x 10 21 cm -3 The square resistance is 20-150 omega/\9633;
and when the second tunneling silicon oxide layer is prepared, controlling the thickness of the second tunneling silicon oxide layer to be 0-15nm.
6. The method for manufacturing the crystalline silicon bottom cell of the perovskite crystalline silicon tandem solar cell as claimed in claim 1, wherein the step of preparing the carrier selective transmission layer on the lower surface of the second passivation layer comprises the following steps: preparing a carrier selective transport layer by ALD or PVD;
the carrier selective transport layer includes an electron selective transport layer or a hole selective transport layer.
7. A crystalline silicon bottom cell, characterized in that, crystalline silicon bottom cell is applied to perovskite crystalline silicon tandem solar cell, crystalline silicon bottom cell includes:
the thickness of the silicon wafer substrate is between 100 and 500 micrometers, the silicon wafer substrate is made of N-type silicon or P-type silicon, and the resistivity of the silicon wafer substrate is between 0.1 and 20ohm cm;
the first passivation layer is positioned on the upper surface of the silicon wafer substrate and comprises a doped polycrystalline silicon layer and a first tunneling silicon oxide layer, the thickness of the first passivation layer is between 0 and 135nm, and the thickness of the first tunneling silicon oxide layer is between 0 and 15 nm;
the second passivation layer is positioned on the lower surface of the silicon wafer substrate, and the thickness of the second passivation layer is between 0 and 135 nm;
the carrier selective transmission layer is positioned on the lower surface of the second passivation layer, and the thickness of the carrier selective transmission layer is 0-200 nm;
the antireflection layer is positioned on the lower surface of the carrier selective transmission layer, and the thickness of the antireflection layer is between 0 and 300 nm;
the metal bottom electrode layer is located on the lower surface of the antireflection layer, and the thickness of the metal bottom electrode layer is 1-2000 mu m.
8. The crystalline silicon bottom cell of claim 6, wherein, in preparing the first passivation layer based on the N-type doped polysilicon layer, the thickness of the N-type doped polysilicon layer in the first passivation layer is 0-120nm, and the doping concentration is 8 x 10 18 cm -3 To 1.5 x 10 21 cm -3 (ii) a Or when preparing the first passivation layer based on the P-type doped polycrystalline silicon layer, the thickness of the P-type doped polycrystalline silicon layer in the first passivation layer is 0-120nm, and the doping concentration is 8 x 10 18 cm -3 To 3 x 10 21 cm -3 ；
The thickness of the first tunneling silicon oxide layer of the first passivation layer is 0-15nm.
9. The crystalline silicon bottom cell of claim 7, wherein when the first passivation layer comprises an N-type doped polysilicon layer, the second passivation layer comprises a P-type doped polysilicon layer or a P-type diffusion doping layer preparation; the thickness of the N-type doped polysilicon layer in the second passivation layer is 0-120nm, and the doping concentration is 8 x 10 18 cm -3 To 1.5 x 10 21 cm -3 ；
Or when the first passivation layer comprises a P-type doped polycrystalline silicon layer, the second passivation layer is prepared on the basis of an N-type doped polycrystalline silicon layer or an N-type diffusion doping layer; the P-type doped polysilicon layer in the second passivation layer has a thickness of 0-120nm and a doping concentration of 8 × 10 18 cm -3 To 3 x 10 21 cm -3 ；
The thickness of the second tunneling silicon oxide layer is 0-15nm.
10. The crystalline silicon bottom cell of any of claims 7 to 9, wherein the metal bottom electrode layer is a full-coverage structure or a grid line structure.
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