CN115210589A

CN115210589A - Chip testing device and testing method

Info

Publication number: CN115210589A
Application number: CN202080098077.0A
Authority: CN
Inventors: 李春雷; 苗广田; 郑�和; 徐一鸣; 袁博文; 李亚
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-03-25
Filing date: 2020-03-25
Publication date: 2022-10-18
Anticipated expiration: 2040-03-25
Also published as: WO2021189322A1; CN115210589B

Abstract

A chip testing device and a testing method relate to the technical field of chip testing and solve the problem that the testing cost of ATE testing in the prior art is too high. The specific scheme is as follows: provided is a chip testing apparatus including: the test system comprises a first backboard (311), a control module (310) of an upper computer (312) and a first test module (313) which are respectively coupled with the first backboard (311), and M test heads (320). Each test head (320) comprises: the system comprises a second backboard (321), a main control board card (322) and a second test module (323) which are respectively coupled with the second backboard (321). The M second backplanes (321) are connected with the first backplane (311) through cables. When the chip testing device is used for testing the chip to be tested through the N testing heads (320), the upper computer (312) transmits the control signals to the main control board card (322) of the N testing heads (320) through the first back plate (311) and the second back plate (321) respectively. Each master control board card (322) controls the second test module (323) to generate the first test signal according to the control signal. The upper computer (312) also controls the first test module (313) to generate a second test signal, and the second test signal is transmitted to the N test heads (320) through the first backboard (311).

Description

Chip testing device and testing method

Technical Field

The embodiment of the application relates to the technical field of chips, in particular to a chip testing device and a chip testing method.

Background

The chip is used as a core device of the electronic equipment, and needs to be strictly tested before a manufacturer delivers goods so as to ensure the normal operation of the electronic equipment. For example, the pre-shipment testing of the chip may include testing Intellectual Property (IP) characteristics of the chip, testing the chip in different scenarios, and so on. For example, the IP characteristics of the chip may include voltage and current values of different pins during operation, design For Test (DFT) vector values, and the like.

The test on the IP characteristics can directly verify whether the basic functions of the chip reach the standard or not. Therefore, testing of IP characteristics is an important ring in pre-shipment testing of chips.

The tests for different IP characteristics may be implemented using Automated Test Equipment (ATE). In this application, testing of IP characteristics may also be referred to as ATE testing. ATE, which is commonly used in the industry for performing ATE testing of chips, may comprise two parts. As shown in FIG. 1, ATE 100 may comprise an integrated test head 110 and an upper computer 120. The test head 110 and the upper computer 120 can be connected through a communication cable such as an optical fiber, so that the upper computer 120 controls the test head 110, and the test head 110 sends a test result to the upper computer 120. As shown in fig. 1, one or more test cards 102 may be disposed in the test head 110. Different test cards 102 may cooperate to enable test head 110 to provide different test capabilities for different ATE tests. The test head 110 is provided with a card slot 103 for placing the test single board 105. The test board 105 is provided with a peripheral circuit corresponding to the chip to be tested, and is configured to bear the chip to be tested, and enable the chip to be tested to work normally under the support of different electrical signals provided by the test board 102. One or more thimbles 104 are disposed in the card slot 103 for electrically connecting with a test single board 105. For example, the chip to be tested is the chip 106. When the ATE test is required to be performed on the chip 106, the chip 106 may be placed on the test board 105, and the test board 105 is pressed in the card slot 103, so that the test board 105 may be electrically connected to the card slot 103 through the thimble 104 disposed in the card slot 103, and thus the test head 110 may perform the ATE test on the chip 106 under the control of the upper computer 120, for example, the test capability provided by the mutual cooperation of a plurality of test boards 102 may be used to perform the test corresponding to the IP characteristic on the chip 106.

Currently, different ATEs operate independently, and due to chip size limitations, the number of chips that can be tested at one time by one ATE is very limited. Therefore, when the shipment detection pressure of the chips is large and the ATE detection needs to be carried out on more chips at the same time, it is necessary to use multiple ATEs simultaneously for testing. However, ATE is generally integrated and expensive, which makes the cost of testing the ATE on the chip rising.

Disclosure of Invention

The embodiment of the application provides a chip testing device and a chip testing method, and solves the problem that the testing cost of ATE testing in the prior art is too high.

In order to achieve the above purpose, the embodiment of the present application adopts the following technical solutions:

in a first aspect, a chip testing apparatus is provided, which includes: the device comprises a control module and M test heads, wherein M is an integer larger than 1. Wherein, this control module includes: the first backboard, the upper computer and the first test module are respectively coupled with the first backboard. Each of the M test heads includes: the main control board card and the second test module are respectively coupled with the second backboard. The M second back plates are connected with the first back plate through cables. When the chip testing device is used for testing a chip to be tested through the N testing heads, the upper computer is used for transmitting control signals to the main control board card of the N testing heads through the first back plate and the second back plates of the N testing heads respectively. Each of the N main control board cards is configured to control the second test module to generate a first test signal according to the control signal. The upper computer is also used for controlling the first test module to generate a second test signal and transmitting the second test signal to the N test heads through the first back plate. The second test signal and the first test signal generated by each of the N test heads are used for testing a chip to be tested connected with the test head. N is a positive integer less than or equal to M. Based on this scheme, the volume of a test apparatus having a plurality of test heads is effectively reduced by separating the control side from the test heads. The upper computer is used for controlling the plurality of test heads to test the chip in a centralized manner, so that the test efficiency of the chip can be greatly improved. And further, the purpose of reducing the test cost of the chip is realized.

In one possible design, the first test module includes one or more digital boards. The second test signal is a digital test signal. Based on the scheme, the digital board card with larger volume is stripped from the test head and concentrated on the control side, so that the volume of the test head is effectively reduced.

In one possible design, the second test module includes one or more clock boards and one or more power boards. The first test signal includes a clock signal and a power supply signal. The clock signal is generated by the one or more clock boards under the control of the master control board card, and the power signal is generated by the one or more power boards under the control of the master control board card. Based on this scheme, through setting up clock integrated circuit board and/or power integrated circuit board in second test module to second test module can generate corresponding first test signal under the control of host computer, makes the chip work at the state that corresponds, and then guarantees going on of corresponding ATE test.

In one possible design, the second test module further includes one or more analog boards, the first test signal also includes an analog test signal. The one or more simulation boards generate the simulation test signal under the control of the main control board card. Based on the scheme, the second test module can provide the simulation test signal by arranging the simulation board card in the second test module. And further ensuring the test of the analog IP of the chip to be tested. Especially, when the chip to be tested does not have self-test capability (i.e. cannot automatically generate the required analog test signal), the test coverage of the analog IP can be effectively ensured.

In one possible design, the upper computer is further configured to send a synchronous clock control signal to the second backplanes of the N test heads through the first backplane, respectively. The main control board card of the N test heads is further configured to acquire the synchronous clock control signal, and control the N test heads to test the connected chip to be tested according to the synchronous clock control signal. Based on the scheme, the plurality of test heads can synchronously work by controlling signals through the synchronous clock, so that the test efficiency is improved, and meanwhile, the control on the manipulator for placing/recovering the chip is facilitated.

In one possible design, the second backplane is provided with a first card slot and Q second card slots. The main control board card and the second test module are respectively coupled with the second back plate, and the main control board card and the second test module comprise: the main control board card is clamped on the second backboard through the first clamping groove. Any board card included by the second test module is clamped on the second back plate through any one of the Q second card slots. Based on the scheme, the test head can provide various different resource configurations by normalizing the clamping grooves on the back plate so as to solve the problem of testing resource bottleneck in the prior art.

In one possible design, the main control board includes a processing module and at least one operation module. The processing module is used for controlling the at least one operation module to generate a configuration signal according to the control signal. Each of the N main control boards is configured to control the second test module to generate a first test signal according to the control signal, and includes: and the processing module in each of the N main control board cards is used for controlling the second test module to generate the first test signal according to the configuration signal. Based on the scheme, the main control board card realizes accurate control on the second test module according to the control signal through the processing module and the operation module. In some implementation manners, when the processing module needs to be coupled with the plurality of operation modules at the same time, but the processing module cannot provide enough pins to be coupled with the operation modules respectively, the main control board card may further include a switching module for being disposed between the processing module and the plurality of operation modules, so as to shunt control of the processing module over the operation modules, and to realize control of the processing module over the plurality of operation modules through the switching module.

In a second aspect, there is provided a chip testing method applied to the chip testing apparatus according to any one of the first aspect and its possible designs, the method including: when the chip testing device is used for testing a chip to be tested through the N testing heads, the upper computer transmits control signals to the main control board cards of the N testing heads respectively through the first back plate and the second back plates of the N testing heads. And each of the N main control board cards controls the second test module to generate a first test signal according to the control signal. The upper computer controls the first test module to generate a second test signal, and the second test signal is transmitted to the main control board card of the N test heads through the first back plate. The main control board card of each of the N test heads transmits the first test signal and the second test signal generated by the test head to a chip to be tested connected with the test head, for testing the chip to be tested. Based on this scheme, the volume of a test apparatus having a plurality of test heads is effectively reduced by separating the control side from the test heads. The upper computer is used for controlling the plurality of test heads to test the chip in a centralized manner, so that the test efficiency of the chip can be greatly improved. And further, the purpose of reducing the test cost of the chip is realized.

In one possible design, the second test signal is a digital test signal. Based on the scheme, the digital test signal is provided through the digital board card arranged on the control side, so that the digital IP of the chip to be tested is tested. Since the ATE test on the chip generally requires the digital control signal to be transmitted to the chip to be tested, so that the chip to be tested can operate in the corresponding operating state, in this embodiment of the application, the second test signal may further include the digital control signal.

In one possible design, the first test signal includes a clock signal and a power signal. Based on the scheme, the clock signal and the power supply signal are transmitted to the chip to be tested, so that the chip to be tested can work in a corresponding state, and the corresponding ATE test can be performed on the chip to be tested.

In one possible design, the first test signal further includes: a test signal is simulated. Based on the scheme, the test of the analog IP of the chip to be tested is realized by transmitting the analog test signal to the chip to be tested.

In one possible design, the method further includes: the upper computer respectively sends synchronous clock control signals to the second back plates of the N testing heads through the first back plate. The main control board card of the N test heads receives the synchronous clock control signal through the second back plate and controls the N test heads to test connected chips to be tested simultaneously according to the synchronous clock control signal. Based on the scheme, the plurality of test heads can synchronously work by controlling signals through the synchronous clock, so that the test efficiency is improved, and meanwhile, the control on the manipulator for placing/recovering the chip is facilitated.

In one possible design, the control signal is a configuration signal for controlling the second test module to generate the first test signal. Or, the control signal includes: voltage amplitude level identification and time sequence timing identification. The main control board card controls the second test module to generate a first test signal according to the control signal, and the method comprises the following steps: and the main control board card determines the configuration signal according to the level identifier and the timing identifier. The main control board card controls the second test module to generate the first test signal according to the configuration signal. Based on the scheme, the upper computer can directly send the configuration signal to the main control board card so that the main control board card controls the second test module to generate the corresponding first control signal according to the configuration information. In other implementation manners, the upper computer may further send an identifier with a small data amount to the main control board, so that the main control board queries and determines the configuration signal corresponding to the identifier in a pre-stored correspondence according to the identifier. Therefore, the data interaction pressure between the upper computer and the main control board card can be effectively reduced, and the system stability is improved.

In a possible design, an initial primary signal is stored in the storage area of the main control board card, and the primary signal is used for indicating the corresponding relationship between the level identifier and the timing identifier, and the configuration signal. The main control board card determines the configuration signal according to the level identifier and the timing identifier, and the method comprises the following steps: and the main control board card determines the configuration signal according to the level identifier, the timing identifier and the primary signal. Based on the scheme, the corresponding relation between the identification and the configuration signal is prestored in the main control board card, so that the main control board card can determine the configuration signal according to the received identification.

In a possible design, before the main control board determines a configuration signal according to the level identifier and the timing identifier, the method further includes: the host computer sends the primary signal to the second backplane through the backplane. The primary control board card receives and stores the primary signal through the second backboard. Based on the scheme, when the ATE test is started, the upper computer can pre-store the corresponding relation in the main control board card so that the main control board card can accurately acquire the corresponding configuration signal after receiving the identification.

In a third aspect, a chip system is provided, the chip comprising processing circuitry and an interface. The processing circuit is configured to retrieve from the storage medium and execute a computer program stored in the storage medium to perform the test method according to any one of the second aspect and its possible designs.

In a fourth aspect, there is provided a computer readable storage medium comprising computer instructions which, when executed, perform a testing method as described in any one of the second aspect and its possible designs above.

It is understood that the chip system provided by the third aspect and the computer-readable storage medium provided by the fourth aspect may both correspond to the method provided by the second aspect, and therefore the beneficial effects achieved by the chip system provided by the third aspect and the computer-readable storage medium provided by the fourth aspect are similar and will not be described herein again.

Drawings

FIG. 1 is a schematic diagram of the components of an ATE;

FIG. 2 is a schematic diagram of a test board;

fig. 3 is a schematic composition diagram of a chip testing apparatus according to an embodiment of the present disclosure;

fig. 4 is a schematic diagram illustrating a control module according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a test head according to an embodiment of the present disclosure;

fig. 6 is a logic schematic diagram of a main control board based on an MCU provided in the embodiment of the present application;

FIG. 7 is a schematic diagram illustrating a second test module according to an embodiment of the present disclosure;

FIG. 8 is a schematic diagram illustrating an embodiment of a chip testing apparatus;

fig. 9 is a schematic flowchart of a testing method according to an embodiment of the present application;

FIG. 10 is a schematic flow chart illustrating another testing method provided in the embodiments of the present application;

fig. 11 is a schematic composition diagram of a chip system according to an embodiment of the present disclosure.

Detailed Description

Typically, each chip requires ATE testing before shipment to ensure that the performance of the chip meets shipment requirements. Illustratively, the chip may be subjected to corresponding ATE tests, and depending on whether the ATE test passed or failed, to determine whether the corresponding IP characteristics of the chip meet the shipping requirements. In the prior art, ATE for performing ATE testing may include two parts, a test head 110 and a host computer 120, as shown in fig. 1.

The test head 110 can realize various different ATE tests under the control of the upper computer 120. In the following embodiments, a chip on which an ATE test is performed will be referred to as a chip to be tested. For example, in conjunction with fig. 1, fig. 2 shows a schematic diagram of a test board 102. As shown in fig. 2, the test board 102 includes a clock board 201, a power board 202, and a digital board 203.

It can be understood that the chip to be tested can work in various different working states when working normally. Therefore, in the ATE test before the shipment of the chips to be tested, it is desirable to cover as much as possible its different operating states, so as to ensure that all functions of the chip to be tested are in a normal state. When the chip to be tested works in different working states, corresponding clock signals and/or digital control signals and/or power signals are different. Therefore, when the ATE is tested, different clock signals and/or digital control signals and/or power signals can be input into the chip to be tested, so that the chip to be tested works in different working states, and the coverage of the ATE test in different working states can be realized by testing the IP characteristics of the chip to be tested working in different working states. For example, when a certain ATE test is performed on a chip to be tested, the clock board 201 may be configured to generate a corresponding clock signal according to a control signal transmitted by the upper computer 120, the power supply board 202 may be configured to provide a corresponding power supply signal according to the control signal transmitted by the upper computer 120, and the digital board 203 may be configured to provide a corresponding digital control signal according to the control signal transmitted by the upper computer 120. Thus, the clock signal, the digital control signal and the power signal corresponding to the control signal are input into the chip to be tested, the chip to be tested can work in the working state corresponding to the control signal.

The test head 110 can input a test signal to the chip to be tested while controlling the chip to be tested to be in a corresponding working state. By collecting the output signal of the chip to be tested and verifying the output signal, whether the chip to be tested passes the ATE test can be determined. And when the ATE test is passed, the IP characteristic of the chip to be tested, which corresponds to the ATE test, is in accordance with the shipment requirement. Otherwise, when the ATE test fails, the IP characteristic of the chip to be tested, which corresponds to the ATE test, does not meet the shipment requirement.

It should be noted that, in the ATE test process, different test signals may be input to the chip to be tested, so as to implement the test of the corresponding IP characteristics of the chip to be tested. Common test signals may include digital signals and analog signals.

The ATE test with digital test signals is generally used to test the digital logic characteristics of the chip and the operating state of the chip to be tested. In the embodiment of the present application, the ATE test in which the test signal is a digital signal is referred to as a digital IP test. Illustratively, when a digital test signal needs to be input to the chip to be tested, the digital board 203 may be further configured to provide a digital test signal according to the control signal under the control of the upper computer 120, so that the test head 110 may transmit the digital test signal to the chip to be tested, so as to perform a corresponding IP characteristic test.

Accordingly, ATE testing, in which the test signals are analog signals, is generally used to test the analog characteristics of the chip. That is, when it is necessary to input an analog test signal to the chip under test, the test head 110 needs to have the capability of providing the analog test signal. In the embodiment of the present application, the ATE test in which the test signal is an analog signal is referred to as an analog IP test. Therefore, as shown in fig. 2, the test board 102 in the test head 110 may further include a simulation board 204, so that the test head 110 may generate a corresponding simulation test signal according to the control signal through the simulation board 204 under the control of the upper computer 120, and transmit the simulation test signal to the chip to be tested to implement the simulation IP test.

As the complexity of the chip increases, the need for ATE test items before shipment has also become more prevalent. That is to say, for each before shipment the test time of the chip becomes longer. Because the existing ATE has high integration level and the price of the equipment is very expensive, the test time is prolonged, which causes the test cost of the ATE to rise significantly. Particularly, when the chip shipment pressure is high, since a large number of chips need to be tested in a short time, a large amount of ATE needs to be configured for testing, which causes a sharp rise in the test cost. In addition, the high-integration ATE has a large volume, so when a large amount of ATE is configured for testing, the cost corresponding to the test space occupied by the ATE is very high, which is also a significant reason for the high test cost when large-scale ATE testing is performed. It should be noted that, in the prior art, it is difficult to implement synchronous testing between different ATEs through one control signal. That is, if a plurality of ATEs are required to perform ATE testing simultaneously, control signals need to be input to the upper computer corresponding to each ATE respectively so as to perform test control on the corresponding ATE. Thereby also introducing additional testing costs.

Therefore, when testing large-scale ATE based on the existing ATE, the testing cost is too high, which is a problem to be solved urgently.

In order to reduce the cost of the test, an attempt may be made to perform ATE testing (also referred to as performing multi-site testing) on multiple chips simultaneously on one ATE. Therefore, the test efficiency of the chip in unit time is improved, and the ATE test cost of the chip is reduced. However, since the chip needs to be pressed on the test board for testing, and the test board needs to have a peripheral circuit capable of supporting the chip to perform normal operation, the number of chips to be tested that can be loaded on one test head at the same time is very limited. Especially for some network chips, the size of the test board is large due to the large size of the chip itself (generally in the range of 35mm × 35mm to 50mm × 50mm or even larger), and due to the very complicated peripheral circuits. Therefore, in general, only 2 network chips can be loaded at a time by one test head. In addition, since the integrated ATE is capable of providing fixed test resources (such as the size of the power supply), the shortage of the test resources also becomes a bottleneck for the multi-site test.

In order to solve the above problems, embodiments of the present application provide a chip testing apparatus and a testing method, where the chip testing apparatus effectively reduces the size of a testing device through main control and centralized control of digital resources, compared with an existing ATE. Through the customized backboard, one upper computer can simultaneously control a plurality of test heads to test, and the chip test efficiency is greatly improved. In addition, through the normalized slot and the interface, the test head can more flexibly configure the test resources, so as to solve the bottleneck caused by insufficient test resources. Based on the characteristics, the chip testing device and the chip testing method provided by the embodiment of the application can obviously reduce the chip testing cost. This effect is particularly pronounced when large batches of ATE tests are required.

The following describes a chip testing apparatus and a testing method provided in the embodiments of the present application in detail with reference to the accompanying drawings.

Please refer to fig. 3, which is a schematic diagram illustrating a chip testing apparatus 300 according to an embodiment of the present disclosure. As shown in fig. 3, the chip test apparatus 300 may include a control module 310, and M test heads 320 respectively connected to the control module 310 via communication cables (e.g., optical fibers, etc.). Wherein M is an integer greater than or equal to 2. The M test heads 320 can simultaneously perform ATE testing on the chips to be tested loaded on the M test heads 320 under the control of the control module 310.

Illustratively, to enable N test heads 320 of the M test heads 320 simultaneously to perform ATE testing on a chip under test, N is a positive integer less than or equal to M. The control module 310 may be configured to send a control signal to each test head 320 of the N test heads 320 through the cable, so as to trigger each test head 320 of the N test heads 320 to start performing an ATE test on the chip to be tested loaded by the test head corresponding to the control signal. For example, in response to the control signal, each test head 320 of the N test heads 320 may be configured to generate a first test signal according to the received control signal, and input the first test signal into a chip under test connected to the test head 320 to support a corresponding ATE test. In addition, the control module 310 may be further configured to generate a second test signal and transmit the second test signal to the chip under test through the test head 320. Therefore, the chip to be tested can execute the corresponding ATE test under the support of the first test signal and the second test signal. For example, after receiving the first test signal and the second test signal, the chip to be tested may process the related input data and output a corresponding output signal.

Test head 320 may also be used to forward the output signal to control module 310, so that control module 310 determines whether the current ATE test passes based on the output signal.

In some embodiments, the output signal may be an output signal of the chip under test after processing the input test signal. After receiving the output signal through the test head 320, the control module 310 may compare the output signal with a predetermined output signal to verify whether the output signal is expected, so as to determine whether the current ATE test is passed.

In some other embodiments, the chip under test may have a Built In Self Test (BIST) capability, that is, the chip under test may process the input test signal and then determine whether the processed signal meets the expectation. That is, the chip under test can determine whether the ATE test passes. The output signal may be a result of the to-be-tested chip automatically judging whether the ATE test passes or not.

The output signals may be output from the relevant pins of the chip under test to the test head 320. The test head 320 may transmit the result to the control module 310, and the control module 310 may determine whether the current ATE test passes according to the result, and further perform corresponding processing on the chip to be tested, for example, classify the chip to be tested according to whether the ATE test passes.

It can be seen that when the chip under test has BIST capability, the test head 320 can directly transmit the result of the ATE test to the control module 310 according to the above method, which can significantly reduce the signal transmission stress between the test head 320 and the control module 310 in the process. Meanwhile, since the result of whether the ATE test passes or not is determined by the judgment of the chip to be tested, the control module 310 does not need to compare and verify a large amount of processed data to obtain the ATE test result, and the processing pressure of the control module 310 is reduced. On the other hand, the test head 320 may also directly transmit the output signal of the chip under test after processing the input test signal to the control module 310, thereby reducing the requirement for the chip under test, that is, even if the chip under test does not have BIST capability, the ATE test may be performed and the feedback of the output data may be completed through the above scheme. In the specific implementation process of the above scheme, the scheme can be flexibly selected according to requirements, and the embodiment of the application is not limited thereto.

In order to make the detailed features of the chip testing apparatus provided in the embodiments of the present application more clearly understood by those skilled in the art, the detailed composition and division of each module and the function thereof will be described in detail below based on the composition of the chip testing apparatus 300 shown in fig. 3.

For example, as shown in fig. 4, the control module 310 in the chip testing apparatus 300 may include an upper computer 312, a first testing module 313 and a first backplane 311.

The upper computer 312 may be coupled to the first backplane 311 via a communication cable (e.g., an optical fiber).

The first test module 313 is also coupled to the first backplane 311. For example, the first test module 313 may include one or more test boards, which may be plugged into the first backplane 311 through a plurality of slots disposed on the first backplane 311 to couple the first test module 313 and the first backplane 311.

For example, the upper computer 312 may be configured to generate a control signal and transmit the control signal to the first backplane 311 through a cable, so that the control signal can be transmitted to the corresponding test head 320 through the first backplane 311.

The upper computer 312 may further be configured to control the first test module 313 to generate a second test signal, and send the second test signal to the test head 320 through the first backplane 311.

Wherein the second test signal may comprise a digital control signal when performing the analog IP test. The second test signal may include a digital control signal and a digital test signal when performing a digital IP test.

In some embodiments, the first test module 313 may include one or more digital test boards. It is understood that in ATE testing, whether analog IP characterization tests are performed or digital IP characterization tests are performed, digital control signals need to be input into the chip. The digital control signal may be very complex, and therefore, the volume of the digital board card for generating the digital control signal is much larger than that of other boards (such as an analog board card, a power supply board card or a clock board card). In addition, in the digital IP testing process, the digital test board is also used to provide digital test signals, and since the digital test signals are generally complex and have a large data size, the digital board generating the digital test signals also needs to have a complex circuit, and thus has a large volume.

Therefore, in the embodiment of the present application, the digital board is stripped from the test head, and the digital board is integrated in the control module 310. Therefore, a digital board card occupying a large amount of space does not need to be arranged in each test head, so that the volume of each test head can be obviously reduced, and the volume of the whole chip testing device 300 is further reduced. Thereby enabling a reduction in the space cost of the chip test apparatus 300 during large-scale chip test deployment.

It should be noted that, in some implementations, as shown in fig. 4, the upper computer 312 may not be directly coupled to the first test module 313, but control the first test module 313 through a communication line on the first backplane 311. In other implementations, the upper computer 312 may also be directly coupled to the first test module 313 through a communication line so as to directly control the first test module 313 to generate the second test signal.

In addition, the upper computer 312 described in this embodiment may be a tablet computer, a desktop computer, a laptop computer, a handheld computer, a notebook computer, an ultra-mobile personal computer (UMPC), a netbook, a workstation, or other devices capable of generating a control signal under the operation of a user. Of course, the upper computer 312 may also be a relay device connected to the network, and is configured to obtain a corresponding signal from the network and forward the signal to a corresponding module, such as the control module 310, to implement a corresponding function. The embodiment of the present application does not particularly limit the specific form of the apparatus.

In the embodiment of the present application, please refer to fig. 5, which is a schematic composition diagram of a test head 320 according to the embodiment of the present application. The M test heads in the chip test apparatus 300 shown in fig. 3 each have the composition of the test head 320 shown in fig. 5.

As shown in fig. 5, the test head 320 may include a second backplane 321, a main control board 322 and a second test module 323. The main control board 322 and the second test module 323 are coupled to the second backplane 321. For example, the second backplane 321 may be provided with a plurality of slots, so that the main control board 322 and the second test module 323 are plugged into the second backplane 321 through the slots to couple the main control board 322, the second test module 323 and the second backplane 321. In addition, the second backplane 321 is also coupled to the control module 310 (e.g., the first backplane 311 of the control module 310) via a communication cable, so as to receive the control signal from the control module 310 and send the ATE test result to the control module 310 via the communication cable.

The main control board 322 is a control center of the test head 320. In this embodiment, the main control board 322 may include a processing module and at least one operation module; the processing module may be configured to control the at least one operation module to generate the configuration signal according to the control signal. The processing module may be further configured to transmit the configuration signal to the second test module, so that the second test module generates a corresponding first test signal for performing a corresponding test on the chip to be tested.

For example, the Processing module may be a device having a Processing function, such as a processor (CPU) or a Micro Controller Unit (MCU). The operation module may be a Field-Programmable Gate Array (FPGA) or other device having a logic operation function. In some implementation manners, when the processing module needs to be coupled to the plurality of operation modules at the same time, but the processing module cannot provide enough pins to be coupled to the operation modules respectively, the main control board card may further include a switching module for being disposed between the processing module and the plurality of operation modules, so as to shunt control of the processing module to the operation modules, and realize control of the processing module to the plurality of operation modules through the switching module.

The following description will take the processing module as an MCU, the main control board 322 includes 2 FPGAs, and the switch module is a Complex Programmable Logic Device (CPLD). Please refer to fig. 6, which is a logic diagram of a MCU-based main control board according to an embodiment of the present disclosure. As shown in fig. 6, the main control board 322 may include an MCU 322a, a cpld 322b, an fpga 322C, a Joint Test Action Group (JTAG), and peripheral circuits and devices.

The MCU 322A, the CPLD 322B, and the FPGA 322C may be coupled via a Local Bus (Local Bus) to realize data transmission. In addition, the FPGA 322C may be coupled to JTAG, so that the main control board 322 may perform data interaction with the outside through JTAG. It should be noted that, in this example, the number of the modules such as the MCU 322a, the cpld 322b, the fpga 322C, and the JTAG may be one or more, and the greater the number of the modules, the greater the corresponding processing functions provided by the modules. In FIG. 6, an example of a system including one

MCU

322A,1

CPLD

322B,2 FPGAs 322C (e.g., FPGA-1 and FPGA-2), and 3 JTAG (e.g., JTAG-1, JTAG-2, and JTAG-3) is illustrated.

The MCU 322A is responsible for communicating with the upper computer 312 through the second backplane 321, for example, the MCU 322A may be configured to receive an instruction of the upper computer, convert the instruction into a register, process the register through the CPLD, and send the register to a corresponding FPGA through the Local Bus. As shown in fig. 6, the MCU 322A further provides a plurality of pins with different functions, such as PL LED 4, I2C, UART, RS485, JTAG, MDIO, ETH0, ETH1, CLK _25m _out, CLK _66m67_out, irq0, local bus, irq1, pcie 3, spi, etc., for implementing the signal interaction between the MCU 322A and the outside. Illustratively, PL LEDs 4 may be used in conjunction with LEDs to enable device status indication. The I2C can be used for being coupled with the E2PROM to realize information storage such as equipment manufacturer numbers. The UART may be configured to couple to the RJ45 via a serial chip to control the peripheral via a serial port. JTAG may be used to couple with the JTAG-3 module to enable control of peripherals. The ETH0 may be used to couple with the RJ45 through a network interface chip to implement logic version updating and establish a connection with a network.

The CPLD 322B may be used for expansion of the number of input and output signals.

Two of the FPGAs 322C each have their corresponding logic programming utility. The FPGA-1 is used to process all signals for controlling and managing the modules inside the test head 320. For example, FPGA-1 may be used to generate backplane & fan control signals under the control of the MCU 322A, for controlling the signal flow of the second backplane 321 and the operation of the heat dissipation fan inside the test head 320. As another example, FPGA-1 may also be used to generate a Global Clock Signal (Global Clock) and a Global synchronization Signal (Global Sync Signal) under the control of MCU 322A to control the in-order transmission of all signals inside test head 320. The FPGA2 is configured to process all signals for controlling and managing a chip side to be tested (or called a Load Board (LB) side) outside the test head 320. For example, FPGA-2 may be used to implement control of all LB sides through logic programming under the control of the MCU 322A and to control other modules (e.g., the second test module 323) in the test head 320 to provide clock signals, power signals, and other control signals required for operation for the LB sides. As an example, FPGA-2 may be configured to output a Utility 56 Control bits signal under the Control of the MCU 322A, for controlling a switch loaded on the board. FPGA-2 may also be used to output 4 pcm bus signals (i.e., 4 sets of SPI protocol signals) for configuring the clock board card under the control of MCU 322A.

In addition, a memory module (not shown in fig. 6) having a memory function may also be provided in the MCU 322A. The storage module may be used to store external data required by the MCU 322A during operation, so that the MCU 322A can make calls to the data more quickly. The memory module may also be used to store intermediate data generated by MCU 322A during operation. Of course, the storage module may also be used to store data required by other main control boards 322 during operation. The embodiments of the present application do not limit this. As an example, the memory module may include multiple (e.g., 4) DDR3 memories and/or Error Checking and Correcting (ECC) memories and/or multiple storage media with different storage characteristics, such as a Nand flash and/or a Nor flash, so that when the memory module is used to store data, layered storage of data can be implemented, the utilization rate of the storage media is increased, and meanwhile, the efficiency of reading and writing data is increased.

In this embodiment of the present application, the storage module may be further configured to store a correspondence between an identifier carried in the control signal and the configuration signal, where in this embodiment of the present application, the correspondence may also be referred to as primary selection (primary) information. For example, the identifier carried in the control signal may include a voltage amplitude (level) identifier indicating the corresponding test signal, and a timing identifier indicating the timing of the corresponding test signal. At this time, the primary signal is also used to indicate the voltage configuration information and the timing configuration information corresponding to the level identifier and the timing identifier. For example, after receiving the control signal carrying the first level identifier and the first timing identifier, the main control board 322A may be configured to query and acquire the corresponding configuration signal from the primary signal according to the first level identifier and the first timing identifier. And controls the second test module 323 to generate a corresponding first test signal according to the configuration signal. The main control board 322A may be configured to transmit the first test signal to the chip to be tested, so as to support performing corresponding ATE test on the chip to be tested.

The second test module 323 in the test head 320 may comprise a plurality of different types of test boards for generating corresponding signals to support corresponding ATE tests under the control of the master control board 322.

Illustratively, as shown in FIG. 7, the second test module 323 may include a power board 323A and a clock board 323B. The power board 323A may be configured to generate a corresponding power signal under the control of the main control board 322, so as to provide electric energy for the operation of the test head 320 and the chip to be tested. The clock board 323B may be configured to generate a corresponding clock signal under the control of the main control board 322, so as to provide a clock signal for the test head 320 to normally operate, and support a clock signal for the chip to be tested to normally operate in a corresponding ATE test scenario.

It should be noted that, in some embodiments, the clock signal may also be provided by the master card 322 shown in fig. 5 or the master card 322 shown in fig. 6. For example, the main control board card has a composition as shown in fig. 6. The main control board 322 may be provided with a clock synchronization control circuit, which may generate a system clock signal based on a high-precision frequency source under the control of the MCU 322A. The system clock signal may be in the form of a multi-point low Voltage Differential Signaling (M-LVDS) and output to each module in the test head 320, so as to implement clock frequency synchronization of each board in the test head 320. It is understood that, when the master board has the above function of generating the clock signal, the second test module 323 may not include the clock board 323A. Of course, the clock signal may also be obtained from other devices through an external interface (such as an SMA interface, not shown in fig. 6) on the main control board 322. The embodiments of the present application do not limit this. The following description will be given taking an example in which a clock signal is generated by the clock board 323A.

In addition, in some test scenarios, for example, when performing an analog IP test, the test head 320 needs to provide a corresponding analog test signal for the chip to be tested, so that the chip to be tested performs corresponding processing on the analog test signal. As shown in fig. 7, the second test module 323 may further include one or more analog boards 323C, where the one or more analog boards 323C may generate corresponding analog test signals under the control of the main control board 322 and transmit the analog test signals to the chip to be tested. After processing the analog test signal, the chip to be tested may transmit the corresponding output signal to the upper computer 312 in the control module 310 through the main control board 322, so that the upper computer 312 determines whether the analog IP test corresponding to the chip to be tested passes or not according to the output signal. It should be noted that, when the test apparatus provided in the embodiment of the present application is used for performing an analog IP test on a chip with BIST capability, the analog test signal required by the analog IP test may also be generated by the chip under test under the control of a digital control signal. Therefore, when performing an analog IP test on a chip with BIST capability, the second test module 323 may not include the analog board 323C.

As described above, the control module 310 and the test heads 320 are configured with backplanes, such as the first backplane 311 in the control module 310 and the second backplane 321 in each of the M test heads 320. In the embodiment of the present application, the first backplane 311 and the second backplane 321 may be customized high-speed backplanes supporting a PCI-Express (PCI-e) high-speed bus. The first backplane 311 may provide an interface corresponding to the second backplane 321, so as to implement fast interaction of signals between the two backplanes.

It should be noted that, in some implementation manners of the embodiment of the present application, the slots on the second backplane 321 for bearing boards with different functions included in the second test module 323 may be slots in a normalized design. For example, a first slot and Q second slots are disposed on the second backplane 321. The main control board card may be plugged in the second backplane 321 through the first slot. Any board card, such as a power board card, a clock board card or an analog board card, included in the other second test modules may be plugged into the second backplane 321 through any one of the Q second slots. For example, a total of 8 slots are provided on the second backplane 321, which are respectively identified as #0, #1, #2, #3, #4, #5, #6 and # 7. The #0 slot may be a corresponding slot of the master card 322. Any of the other slots identified as #1- #7 may be used to plug in power strip 323A, clock strip 323B, or analog strip 323C. Thus, when a larger power signal is required, a plurality of power boards 323A can be plugged into the second backplane 321 to provide the larger power signal. When multiple clock signals are required, multiple clock boards 323B may be plugged into the second backplane 321 to provide multiple different clock signals. When a plurality of analog test signals are required, a plurality of analog boards 323C may be plugged into the second backplane 321 to provide a plurality of different analog test signals. Compared with the common back plate which can only be inserted into the corresponding slots by different functional board cards, the high-speed back plate after the normalized design can allocate the resources on the board more flexibly so as to meet more diversified test requirements. Experiments prove that resources can be allocated more flexibly, so that simultaneous testing of more chips can be realized on one testing head. When a plurality of chips are tested on one test head at the same time, the test single board bearing the chips can realize sharing of partial circuits, and simultaneously can reduce the complexity of the test single board, thereby reducing the preparation cost of the test single board by at least 40 percent.

As described above, the chip testing apparatus 300 according to the embodiment of the present disclosure can implement synchronous testing of a plurality of test heads (e.g., test head 1-test head M) under the control of one control module 310. For example, the upper computer 312 may send a synchronous clock control signal to different test heads to be subjected to the ATE test through the first backplane 311 and the second backplane 312. Because the first backplane 311 and the second backplane 312 are high-speed backplanes supporting PCI-e high-speed transmission, synchronous transmission of synchronous clock control signals can be realized, and thus the purpose that one upper computer 312 controls a plurality of test heads 320 to perform ATE testing can be realized. Therefore, the cost of human resources caused by relative independence of the ATE test environment can be greatly reduced, and the test cost of the chip is further reduced while the test efficiency of the ATE is improved.

It should be understood that the above components and functions of the control module 310 and the test head 320 in the chip testing apparatus 300 shown in fig. 3, fig. 4, fig. 5, fig. 6, and fig. 7 are only exemplary descriptions, and other components that meet the above functional characteristics should also be included in the scope of the present invention.

Like this, the chip testing device that this application embodiment provided, through reducing the integrated level, effectively reduces test equipment's volume, through verifying, the volume of the test head of the chip testing device that this application embodiment provided reduces at least 70% than the volume of the test head of current ATE. Through customizing the back plate and the normalization interface, one upper computer can simultaneously control a plurality of test heads to test, and the chip test efficiency is greatly improved. Meanwhile, the test head can more flexibly configure the test resources so as to solve the bottleneck caused by insufficient test resources. Based on the characteristics, the chip testing device and the chip testing method provided by the embodiment of the application can obviously reduce the chip testing cost. This effect is particularly pronounced when large batches of ATE tests are required.

The testing method provided by the embodiment of the present application can be applied to the chip testing apparatus 300 having the composition shown in fig. 3, fig. 4, fig. 5, fig. 6 or fig. 7.

For example, a chip testing apparatus includes 8 testing heads, and the 8 testing heads are simultaneously started to respectively perform ATE testing on 8 chips to be tested. That is, the number of test heads M =8, and the number of test heads N =8 for the ATE test is started, each test head being used to test 1 chip under test, while the number of chips under test P =8 that can be subjected to the ATE test.

The composition of the chip test apparatus is shown in fig. 8. The control module is connected with the second back plates of all 8 test heads through the first back plate and the communication cables, so that the 8 test heads are controlled to synchronously carry out ATE (automatic test equipment) test on the chips to be tested 1-8 loaded on the corresponding test heads by sending control signals.

As an example, based on the chip testing apparatus shown in fig. 8, fig. 9 shows a schematic flowchart of a testing method provided in an embodiment of the present application. As shown in fig. 9, the method may include S901-S907. In this case, the first test signal is taken as the test signal 2, and the second test signal is taken as the test signal 1.

And S901, the upper computer sends test messages to the 8 test heads through the first back plate respectively, wherein the test messages comprise control signals and synchronous clock control signals.

And S902, the upper computer controls the first test module to generate a test signal 1, and sends the test signal 1 to 8 test heads through the first back plate.

And S903, for each test head in the 8 test heads, the main control board card receives the control signal and the test signal 1 through the second back board.

And S904, the main control board card controls the second test module to generate a test signal 2 according to the control signal in the test message.

And S905, the main control board cards in the 8 test heads synchronously input the test signal 1 and the test signal 2 to the corresponding chips to be tested through the corresponding test single boards according to the synchronous clock control signals included in the test messages.

And S906, for each test head in the 8 test heads, the main control board card obtains the output signal and transmits the output signal to the first backboard through the second backboard.

And S907, the upper computer receives output signals respectively corresponding to the 8 test heads through the first back plate, and determines whether the ATE test of the corresponding chip to be tested passes or not according to the output signals.

It is understood that, in general, before starting the ATE test, a tester determines a corresponding ATE test scheme according to the type of the chip to be tested. The test scheme may include control signals corresponding to the ATE test. Because the data size of the control signal is also large when some complex ATE tests are performed, in some embodiments of the present application, the control signal and the identifier corresponding to the control signal may be stored in a storage module of the main control board in the test head in advance (in the embodiments of the present application, this process may be referred to as initialization). Therefore, when the control signal needs to be sent, the upper computer can send the identification with the data volume far smaller than the identification corresponding to the control signal of the control signal, so that the data interaction pressure between the upper computer and the main control board card is reduced. The main control board card can receive the identifier corresponding to the control signal, inquire the configuration signal corresponding to the identifier in the storage module of the main control board card, and control the first test module to generate the corresponding test signal 1 according to the inquiry result.

It should be noted that, because the number of the corresponding relationships pre-stored in the main control board card in the initialization process is limited, a situation may also occur in which the main control board card cannot determine the corresponding configuration signal from the pre-stored corresponding relationships according to the timing identifier and the level identifier carried in the control information. For example, in some ATE tests, the control signal may be dynamically adjusted according to the last ATE test result, and therefore, the primary signal stored in the initialization may not include the configuration information corresponding to the timing identifier and the level identifier included in the dynamically adjusted control signal.

For such a situation, in the embodiment of the present application, the main control board may determine the configuration information by the following method:

the method comprises the following steps: the main control board card determines that in all primary signals stored, no configuration information corresponding to the level identification and/or the timing identification included in the received control signal exists. The main control board card sends a feedback message to the first backplane through the second backplane for instructing the upper computer to retransmit the configuration information corresponding to the identifier sent last time. And the upper computer receives the feedback message through the first back plate and sends detailed configuration information to the main control board card according to the feedback message.

The method 2 comprises the following steps: the main control board card determines that in all primary signals stored, no configuration information corresponding to the level identification and/or the timing identification included in the received control signal exists. And the main control board card generates corresponding configuration information according to the preset generation relationship between the identifier and the configuration information and according to the level identifier and the timing identifier included in the received control signal.

In the actual execution process, the method for determining the configuration information by the main control board card may flexibly select the two methods, or may determine the configuration information by other methods, which is not limited in the embodiment of the present application.

It should be noted that, in the embodiment of the present application, the manipulator may be used in conjunction with the chip testing apparatus to improve the automation degree of ATE testing, and further improve the testing efficiency.

For example, the ATE test is performed by the chip tester shown in fig. 8. A manipulator may be provided for each test head for loading a chip to be tested on the test head. The manipulator can also be used for taking off the chips which are subjected to the ATE test from the test head and placing the chips in a classified mode. The testing method shown in fig. 9 is implemented in combination with a robot as an example. As shown in fig. 10, the method may include: S1001-S1005.

And S1001, the upper computer sends a first message to the 8 manipulators, and the first message is used for indicating the manipulators to load the chips to be tested into the 8 test heads.

And S1002, the machine loads the chip to be tested into 8 test heads according to the first message, and feeds back a second message for indicating that the upper computer finishes loading.

S1003 and the upper computer receive the second feedback information from the 8 manipulators, and execute the test method shown in fig. 9.

And S1004, the upper computer sends third messages to the 8 mechanical hands respectively, the third messages are used for instructing the mechanical hands to take down the corresponding chips to be tested from the test head, and the chips to be tested which are taken down are placed in a classified mode according to the instructions of the third messages. For example, when the ATE test result of a certain chip to be tested is passed, the upper computer may control the corresponding manipulator to take down the chip to be tested and place the chip in the chip placement area where the test is passed through, through the third message. And when the ATE test result of a certain chip to be tested is failed, the upper computer can control the corresponding manipulator to take down the chip to be tested and place the chip in the chip placement area where the test is failed through the third message. And realizing classified placement of the chips.

And S1005, taking down the corresponding chip and placing the chip at the corresponding position according to the third message by the machine.

In the above example, the description is given taking an example in which one manipulator is disposed for each test head. It will be appreciated that the provision of a robot for each test head maximises the efficiency of loading and removal and sorting of chips. In other embodiments, a common manipulator may be configured for a plurality of test heads, so that the problem of excessive occupied space due to excessive manipulators is avoided, and the increase of test cost caused by configuring a plurality of manipulators is reduced. In the actual execution process, the manipulator can be flexibly configured, which is not limited in the embodiment of the present application.

Referring to fig. 11, a schematic composition diagram of a chip system 1100 according to an embodiment of the present disclosure is shown. The chip system 1100 may include: a processor 1101 and a communication interface 1102 for supporting the implementation of the test methods referred to in the above embodiments. In one possible design, the chip system 1100 may further include a memory for storing program instructions and data necessary for the terminal. The chip system may be formed by a chip, or may include a chip and other discrete devices.

The functions or actions or operations or steps, etc., in the above embodiments may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using a software program, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. The procedures or functions described in accordance with the embodiments of the present application are all or partially generated upon loading and execution of computer program instructions on a computer. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored on a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website, computer, server, or data center to another website, computer, server, or data center via wire (e.g., coaxial cable, fiber optic, digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or can comprise one or more data storage devices, such as servers, data centers, etc., that can be integrated with the medium. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a Solid State Disk (SSD)), among others.

Although the present application has been described in conjunction with specific features and embodiments thereof, it will be evident that various modifications and combinations can be made thereto without departing from the spirit and scope of the application. Accordingly, the specification and drawings are merely illustrative of the present application as defined in the appended claims and are intended to cover any and all modifications, variations, combinations, or equivalents within the scope of the application. It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, to the extent that such modifications and variations of the present application fall within the scope of the claims and their equivalents, it is intended that the present application also cover such modifications and variations.

Claims

A chip testing apparatus, comprising: the test system comprises a control module and M test heads, wherein M is an integer greater than 1;

wherein the control module comprises: the first backboard is respectively coupled with the upper computer and the first test module; each of the M test heads includes: the main control board card and the second test module are respectively coupled with the second backboard; the M second back plates are connected with the first back plate through cables;

when the chip testing device is used for testing a chip to be tested through the N testing heads, the upper computer is used for transmitting control signals to the main control board cards of the N testing heads through the first back plate and the second back plates of the N testing heads respectively; each of the N main control board cards is used for controlling the second test module to generate a first test signal according to the control signal;

the upper computer is also used for controlling the first test module to generate a second test signal and transmitting the second test signal to the N test heads through the first back plate;

the second test signal and the first test signal generated by each of the N test heads are used for testing a chip to be tested connected with the test head; n is a positive integer less than or equal to M.
The chip test apparatus according to claim 1,

the first test module comprises one or more digital board cards;

the second test signal is a digital test signal.
Chip testing device according to claim 1 or 2,

the second test module comprises one or more clock board cards and one or more power board cards;

the first test signal comprises a clock signal and a power signal;

the clock signals are generated by the one or more clock boards under the control of the main control board card, and the power signals are generated by the one or more power boards under the control of the main control board card.
The chip test apparatus according to claim 3,

the second test module further comprises one or more analog boards, the first test signal further comprises an analog test signal;

the simulation test signal is generated by the one or more simulation boards under the control of the main control board card.
The chip test apparatus according to any one of claims 1 to 4,

the upper computer is also used for respectively sending synchronous clock control signals to the second back plates of the N test heads through the first back plate;

and the master control board card of the N test heads is also used for acquiring the synchronous clock control signal and controlling the N test heads to test the connected chip to be tested simultaneously according to the synchronous clock control signal.
The chip test apparatus according to claim 3 or 4,

a first clamping groove and Q second clamping grooves are formed in the second backboard;

the main control board card and the second test module are respectively coupled to the second backplane, and include:

the main control board card is clamped on the second back board through the first clamping groove;

any board card included by the second test module is clamped on the second back plate through any one of the Q second clamping grooves.
The chip testing device according to any one of claims 1 to 6, wherein the main control board comprises a processing module and at least one operation module;

the main control board card is used for controlling the second test module to generate a first test signal according to the control signal, and comprises:

and the processing module of the main control board card is used for controlling the at least one operation module to generate a configuration signal according to the control signal and controlling the second test module to generate the first test signal according to the configuration signal.
A testing method applied to the chip testing apparatus according to any one of claims 1 to 7, the method comprising:

when the chip testing device is used for testing a chip to be tested through the N testing heads, the upper computer transmits control signals to the main control board cards of the N testing heads through the first back plate and the second back plates of the N testing heads respectively;

each of the N main control board cards controls the second test module to generate a first test signal according to the control signal;

the upper computer controls the first test module to generate a second test signal and transmits the second test signal to the main control board cards of the N test heads through the first back plate;

and the main control board card of each of the N test heads transmits the first test signal and the second test signal generated by the test head to a chip to be tested connected with the test head, and is used for testing the chip to be tested.
The method of claim 8,

the second test signal is a digital test signal.
The method according to claim 8 or 9,

the first test signal includes a clock signal and a power signal.
The method of claim 10, wherein the first test signal further comprises: a test signal is simulated.
The method according to any one of claims 8-11, further comprising:

the upper computer respectively sends synchronous clock control signals to the second back plates of the N test heads through the first back plate;

and the main control board card of the N test heads receives the synchronous clock control signal through the second backboard and controls the N test heads to test the connected chips to be tested at the same time according to the synchronous clock control signal.
A method according to any of claims 8-12, wherein the control signal is a configuration signal for controlling the second test module to generate the first test signal; or the like, or, alternatively,

the control signal includes: voltage amplitude level identification and time sequence timing identification; the main control board card controls the second test module to generate a first test signal according to the control signal, and the method comprises the following steps: the main control board card determines the configuration signal according to the level identification and the timing identification; and the main control board card controls the second test module to generate the first test signal according to the configuration signal.
The method according to claim 13, wherein an initial primary signal is stored in a storage area of the master control board card, and the primary signal is used to indicate a corresponding relationship between the level identifier and the timing identifier and the configuration signal;

the main control board card determines the configuration signal according to the level identifier and the timing identifier, and the determining includes:

and the main control board card determines the configuration signal according to the level identifier, the timing identifier and the primary signal.
The method according to claim 14, wherein before the main control board determines a configuration signal according to the level identifier and the timing identifier, the method further comprises:

the upper computer sends the primary signal to the second backboard through the backboard;

and the primary control board card receives and stores the primary signal through the second backboard.
A chip system, wherein the chip comprises processing circuitry and an interface; the processing circuit is configured to call and run a computer program stored in a storage medium from the storage medium to perform the test method according to any one of claims 8 to 15.
A computer-readable storage medium, comprising computer instructions which, when executed, perform the communication method of any one of claims 8-15.