CN113608935B - Method, system, equipment and medium for testing network card - Google Patents

Method, system, equipment and medium for testing network card Download PDF

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Publication number
CN113608935B
CN113608935B CN202110682314.4A CN202110682314A CN113608935B CN 113608935 B CN113608935 B CN 113608935B CN 202110682314 A CN202110682314 A CN 202110682314A CN 113608935 B CN113608935 B CN 113608935B
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fpga
test
network card
testing
bmc chip
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CN113608935A (en
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陈贝
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Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
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Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2273—Test methods
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/50—Testing arrangements

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

The invention discloses a method, a system, equipment and a storage medium for testing a network card, wherein the method comprises the following steps: connecting a BMC chip in a network card with an FPGA in the network card through NCSI, and connecting the BMC chip with a host inserted into the network card through an I2C interface; transmitting a test instruction to the BMC chip based on a management network port, and transmitting the test instruction to the FPGA through the NCSI; responding to the FPGA to receive the test instruction, analyzing the test instruction, acquiring test object information, and sending the test instruction to a peripheral connected with the FPGA according to the test object information so as to execute a test; and responding to the completion of the peripheral test, and returning a test result to the BMC chip through the FPGA. According to the invention, the network card is simply optimized, and the BMC chip is connected with the FPGA through the NCSI, so that the BMC chip can directly transmit the command of the test application end to the FPGA for processing.

Description

Method, system, equipment and medium for testing network card
Technical Field
The present invention relates to the field of digital circuit design, and more particularly, to a method, a system, a computer device, and a readable medium for testing a network card.
Background
With development of cloud computing technology, the scale of a cloud computing center is larger and larger, a network topology architecture is more and more complex, and management of network ports and forwarding pressure of network data occupy more and more computing resources in a cloud computing data center server. In order to release the computing resources of the server and improve the processing efficiency, the data center generally applies an intelligent network card software and hardware scheme to offload the network processing forwarding work which is originally required to be processed by a server CPU (Central Processing Unit ) to the intelligent network card processing, thereby improving the performance of the network virtualization processing of the data center and expanding the architecture of the data center service. Therefore, the intelligent network card gets more and more attention, and the related technologies such as design and test of the intelligent network card develop faster and faster.
In order to adapt to different application characteristics of various industries and simultaneously provide network processing performance of hardware level, an intelligent network card generally uses an FPGA (Field Programmable GATE ARRAY ) as a processing carrier of a data plane, and simultaneously integrates chips such as a CPU (central processing unit) and a BMC (Baseboard Manager Controller, baseboard management controller) as a carrier of a management plane. Meanwhile, the intelligent network card is limited by the server case, and the intelligent network card is generally expressed as a PCIe interface card with a common size so as to be compatible with a hardware platform of a traditional network card. Therefore, the whole intelligent network card is called a multi-chip and high-integration complex system, and challenges of complexity and efficiency of a testing platform are faced during hardware production testing.
As shown in figure 1, the general architecture of the intelligent network card is that the debugging scheme of an FPGA chip and the peripheral equipment of the intelligent network card generally directly uses the conventional debugging scheme of the FPGA, and the signal data to be observed is transmitted to the special debugging software of the PC end through a JTAG interface for observation by utilizing the online debugging tool of the FPGA; or connecting the signal to be observed to the pin by utilizing the reserved FPGA pin, and then observing the signal by utilizing equipment such as an oscilloscope and the like. The CPU chip and the peripheral device thereof observe the running condition of the CPU chip generally by checking BIOS printing information or by means of serial port printing information, and then perform the function test of the peripheral device.
The above-mentioned debugging method is general, but the above-mentioned debugging method involves many debugging cables and use of debugging software, for example FPGA needs to use the specialized FPGA online debugging tool to debug, and CPU needs to use serial port line connecting wire and serial port debugging tool to debug again. Therefore, the complexity of the test system environment required to be built in the production test is improved, so that the connection operation of a plurality of cables is required to be carried out in each test, the connection stability is checked, and the test efficiency of the intelligent network card production is affected.
In addition, some test schemes are specially designed for network cards by designing special debugging hardware adapter plates, and a plurality of chip test interfaces on the intelligent network card are respectively connected through the adapter plates and then are converged to be presented to a test application end. This approach can reduce the interface complexity at the test application to some extent, but introduces additional hardware design effort and cost.
Disclosure of Invention
Therefore, an object of the embodiments of the present invention is to provide a method, a system, a computer device, and a computer readable storage medium for testing a network card, where the network card is simply optimized, and a BMC chip is connected to an FPGA through an NCSI, so that the BMC chip can directly transmit a command of a test application end to the FPGA for processing, so that hardware debugging cables and cable connection operations required for an intelligent network card hardware production test are greatly reduced, complexity of an intelligent network card hardware production test platform is reduced, and hardware production test efficiency is improved.
Based on the above objects, an aspect of the embodiments of the present invention provides a method for testing a network card, including the following steps: connecting a BMC chip in a network card with an FPGA in the network card through NCSI, and connecting the BMC chip with a host inserted into the network card through an I2C interface; transmitting a test instruction to the BMC chip based on a management network port, and transmitting the test instruction to the FPGA through the NCSI; responding to the FPGA to receive the test instruction, analyzing the test instruction, acquiring test object information, and sending the test instruction to a peripheral connected with the FPGA according to the test object information so as to execute a test; and responding to the completion of the peripheral test, and returning a test result to the BMC chip through the FPGA.
In some embodiments, the method further comprises: and controlling the CPU of the host or the CPU of the network card to test the PCIe interface based on the BMC chip.
In some embodiments, the controlling the CPU of the host or the CPU of the network card to test the PCIe interface based on the BMC chip includes: and controlling the CPU of the host or the CPU of the network card to perform rescanning enumeration of PCIe equipment based on the BMC chip so as to confirm whether the functions of a first PCIe interface connected with the host by the FPGA and a second PCIe interface connected with the CPU of the network card by the FPGA are all normal.
In some embodiments, the method further comprises: and directly judging whether the flash memory connected with the FPGA is normal or not based on the BMC chip.
In some embodiments, the method further comprises: and responding to the fact that the flash memory connected with the FPGA is normal, and programming the flash memory connected with the FPGA through the BMC chip to update the FPGA firmware.
In some embodiments, the method further comprises: and responding to the completion of programming, and controlling the FPGA to start and load a test program of the FPGA based on the BMC chip.
In some embodiments, the method further comprises: and controlling the CPU of the network card to update and upgrade based on the BMC chip.
In another aspect of the embodiment of the present invention, a system for testing a network card is provided, including: the setting module is configured to connect a BMC chip in a network card with an FPGA in the network card through NCSI and connect the BMC chip with a host inserted into the network card through an I2C interface; the transmission module is configured to transmit a test instruction to the BMC chip based on a management network port and transmit the test instruction to the FPGA through the NCSI; the testing module is configured to respond to the receiving of the testing instruction by the FPGA, analyze the testing instruction, acquire testing object information and send the testing instruction to the peripheral connected with the FPGA according to the testing object information so as to execute testing; and the return module is configured to return a test result to the BMC chip through the FPGA in response to the completion of the peripheral test.
In yet another aspect of the embodiment of the present invention, there is also provided a computer apparatus, including: at least one processor; and a memory storing computer instructions executable on the processor, which when executed by the processor, perform the steps of the method as above.
In yet another aspect of the embodiments of the present invention, there is also provided a computer-readable storage medium storing a computer program which, when executed by a processor, implements the method steps as described above.
The invention has the following beneficial technical effects: through simple optimization of the network card, the BMC chip is connected with the FPGA through the NCSI, so that the BMC chip can directly transmit the command of the test application end to the FPGA for processing, the hardware debugging cable and cable connection operation required by the intelligent network card hardware production test is greatly reduced, the complexity of the intelligent network card hardware production test platform is reduced, and the hardware production test efficiency can be improved.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are necessary for the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention and that other embodiments may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a network card in the prior art;
FIG. 2 is a schematic diagram of an embodiment of a method for testing a network card according to the present invention;
Fig. 3 is a schematic diagram of a network card according to an embodiment of the invention;
Fig. 4 is a schematic diagram of an FPGA architecture in a network card according to an embodiment of the present invention;
Fig. 5 is a schematic hardware structure diagram of an embodiment of a computer device for testing a network card according to the present invention;
fig. 6 is a schematic diagram of an embodiment of a computer storage medium of a test network card according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention will be described in further detail with reference to the accompanying drawings.
It should be noted that, in the embodiments of the present invention, all the expressions "first" and "second" are used to distinguish two entities with the same name but different entities or different parameters, and it is noted that the "first" and "second" are only used for convenience of expression, and should not be construed as limiting the embodiments of the present invention, and the following embodiments are not described one by one.
In a first aspect of the embodiment of the present invention, an embodiment of a method for testing a network card is provided. Fig. 2 is a schematic diagram of an embodiment of a method for testing a network card according to the present invention. As shown in fig. 2, the embodiment of the present invention includes the following steps:
S1, connecting a BMC chip in a network card with an FPGA in the network card through NCSI, and connecting the BMC chip with a host inserted into the network card through an I2C interface;
s2, transmitting a test instruction to the BMC chip based on a management network port, and transmitting the test instruction to the FPGA through the NCSI;
S3, responding to the FPGA to receive the test instruction, analyzing the test instruction, acquiring test object information, and sending the test instruction to the peripheral connected with the FPGA according to the test object information so as to execute a test; and
And S4, responding to the completion of the peripheral test, and returning a test result to the BMC chip through the FPGA.
And connecting a BMC chip in the network card with an FPGA in the network card through an NCSI (Network Controller Sideband Interface ), and connecting the BMC chip with a host inserted into the network card through an I2C (Inter-INTEGRATED CIRCUIT, internal integrated circuit) interface. Fig. 3 is a schematic diagram of an architecture of a network card according to an embodiment of the present invention, and as shown in fig. 3, an intelligent network card architecture mainly includes an FPGA chip, a CPU chip, and a BMC chip. Because the FPGA chip is responsible for main network processing and forwarding operations, the FPGA is connected with a high-speed network interface, a HOST golden finger PCIe (PERIPHERAL COMPONENT INTERFACE EXPRESS, bus and interface standard) interface 1, an on-board CPU PCIe interface 2, and DDR (Double Data Rate), FLASH memory, and general control IO (input output) peripherals. The intelligent network card carries a CPU and also mounts devices (general architecture, not shown) such as a memory and a hard disk, so as to operate a service management plane for managing the intelligent network card by using an operating system. The intelligent network card board carries the BMC chip for later remote management. The BMC chip is connected with the FPGA through NCSI, so that the BMC chip can directly transmit some commands of the test application terminal to the FPGA for processing. And connecting the BMC chip with a host inserted into the intelligent network card through the I2C interface, so that the BMC chip can directly control the host end to execute program matching for carrying out hardware test of the intelligent network card. The I2C connection signals between the BMC chip and the host are few, the signal wires reserved in the PCIe golden finger of the intelligent network card can be directly used, and a cable mode can also be adopted.
And transmitting a test instruction to the BMC chip based on a management network port, and transmitting the test instruction to the FPGA through the NCSI. The BMC is directly connected to the test application end through the management network port, receives the test instruction sent by the test application end, and transmits the test instruction to the FPGA through the NCSI.
And responding to the FPGA to receive the test instruction, analyzing the test instruction, acquiring test object information, and sending the test instruction to the peripheral connected with the FPGA according to the test object information so as to execute the test.
Fig. 4 is a schematic diagram of an FPGA architecture in a network card according to an embodiment of the present invention. As shown in fig. 4, the FPGA includes an interconnection module, a PCIe test module 1, a PCIe test module 2, a high-speed network interface test, a DDR test module, a FLASH test module, and an NC-SI. The NCSI is responsible for analyzing the command message transmitted by the BMC chip, analyzing a test object in the command message, and transmitting the command message to an interconnection module in the FPGA. The interconnection module is responsible for distributing the commands to each test module of the FPGA according to the test object, and starting the test operation of each hardware peripheral.
And responding to the completion of the peripheral test, and returning a test result to the BMC chip through the FPGA.
In some embodiments, the method further comprises: and controlling the CPU of the host or the CPU of the network card to test the PCIe interface based on the BMC chip.
In some embodiments, the controlling the CPU of the host or the CPU of the network card to test the PCIe interface based on the BMC chip includes: and controlling the CPU of the host or the CPU of the network card to perform rescanning enumeration of PCIe equipment based on the BMC chip so as to confirm whether the functions of a first PCIe interface connected with the host by the FPGA and a second PCIe interface connected with the CPU of the network card by the FPGA are all normal.
The test function realized by each test module of the FPGA can be tested by adopting a general hardware method, but when the PCIe interface is tested, the BMC is required to control a host CPU or an intelligent network card board CPU to perform rescanning enumeration of PCIe equipment, and the PCIe interface 1 connected with the host by the FPGA and the PCI interface 2 connected with the intelligent network card board CPU by the FPGA are confirmed to have normal functions, so that the subsequent further PCIe test can be executed. According to the embodiment of the invention, the BMC is used for directly controlling the host CPU and the network card CPU, and the connection signal from the BMC to the host is increased so as to be matched with the test flow of the PCIe interface 1.
In some embodiments, the method further comprises: and directly judging whether the flash memory connected with the FPGA is normal or not based on the BMC chip.
In some embodiments, the method further comprises: and responding to the fact that the flash memory connected with the FPGA is normal, and programming the flash memory connected with the FPGA through the BMC chip to update the FPGA firmware.
In some embodiments, the method further comprises: and responding to the completion of programming, and controlling the FPGA to start and load a test program of the FPGA based on the BMC chip.
The test program in the FPGA can directly burn the FLASH of the FPGA on the intelligent network card through the BMC to update the FPGA firmware, and after the burn-in is finished, the BMC controls the FPGA to start and load the test program of the FPGA, so that the use of an external JTAG debugger is not needed.
In some embodiments, the method further comprises: and controlling the CPU of the network card to update and upgrade based on the BMC chip.
The testing of the hardware interface corresponding to the CPU is also controlled by the BMC. Because the BMC can support updating BIOS (Basic Input/Output System) of the CPU on the intelligent network card, the BMC also supports installing the CPU to install the operating System. Besides the traditional firmware updating function of the BMC management board card, the BMC can develop and integrate additional hardware test related command modules, and analyze and forward test commands to the intelligent network card BMC and the CPU, so that the intelligent network card BMC can control the board to load the CPU to install and execute corresponding test programs, and transmit test running conditions back to the BMC.
In the embodiment of the invention, the test control and test result feedback of each hardware interface test module of the FPGA are converged to the intelligent network card board BMC through NCSI, and the related hardware test of the intelligent network card board CPU can be controlled through the intelligent network card BMC. Therefore, the design method carries out centralized control on hardware test of the integrated board card through the board-mounted BMC, then the BMC is directly connected to the test application end through the management network port, the test application end can support the intelligent network card hardware unfolding test work without additional test cables or adapter plates, the complexity of the intelligent network card hardware test platform is greatly reduced, and even the operation that one test platform is remotely connected with a plurality of intelligent network cards for testing can be supported by means of equipment such as a switch and the like, so that the test efficiency is greatly improved.
The method for testing the intelligent network card can greatly reduce the hardware debugging cable and cable connection operation required by the intelligent network card hardware production test by combining a targeted software testing framework in a simple hardware optimization mode, reduce the complexity of an intelligent network card hardware production testing platform and improve the hardware production testing efficiency. The testing method of the invention presents a universal network interface for the upper layer of the testing application, which is convenient for expanding the testing platform by means of equipment such as a switch and the like to test a plurality of intelligent network cards at the same time. In addition, the connection between the BMC and the FPGA and the connection between the BMC and the host can be realized by using a customized cable, and the connection signals are simpler and have low speed, and can be realized only by simple hardware cost.
It should be noted that, in the above embodiments of the method for testing a network card, the steps may be intersected, replaced, added and subtracted, so that the method for testing a network card by using the reasonable permutation and combination should also belong to the protection scope of the present invention, and the protection scope of the present invention should not be limited to the embodiments.
Based on the above object, a second aspect of the embodiments of the present invention provides a system for testing a network card, including: the setting module is configured to connect a BMC chip in a network card with an FPGA in the network card through NCSI and connect the BMC chip with a host inserted into the network card through an I2C interface; the transmission module is configured to transmit a test instruction to the BMC chip based on a management network port and transmit the test instruction to the FPGA through the NCSI; the testing module is configured to respond to the receiving of the testing instruction by the FPGA, analyze the testing instruction, acquire testing object information and send the testing instruction to the peripheral connected with the FPGA according to the testing object information so as to execute testing; and the return module is configured to return a test result to the BMC chip through the FPGA in response to the completion of the peripheral test.
In some embodiments, the system further comprises a second test module configured to: and controlling the CPU of the host or the CPU of the network card to test the PCIe interface based on the BMC chip.
In some embodiments, the second test module is configured to: and controlling the CPU of the host or the CPU of the network card to perform rescanning enumeration of PCIe equipment based on the BMC chip so as to confirm whether the functions of a first PCIe interface connected with the host by the FPGA and a second PCIe interface connected with the CPU of the network card by the FPGA are all normal.
In some embodiments, the system further comprises a determination module configured to: and directly judging whether the flash memory connected with the FPGA is normal or not based on the BMC chip.
In some embodiments, the system further comprises a programming module configured to: and responding to the fact that the flash memory connected with the FPGA is normal, and programming the flash memory connected with the FPGA through the BMC chip to update the FPGA firmware.
In some embodiments, the system further comprises a control module configured to: and responding to the completion of programming, and controlling the FPGA to start and load a test program of the FPGA based on the BMC chip.
In some embodiments, the system further comprises a second control module configured to: and controlling the CPU of the network card to update and upgrade based on the BMC chip.
In view of the above object, a third aspect of the embodiments of the present invention provides a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions being executable by the processor to perform the steps of: s1, connecting a BMC chip in a network card with an FPGA in the network card through NCSI, and connecting the BMC chip with a host inserted into the network card through an I2C interface; s2, transmitting a test instruction to the BMC chip based on a management network port, and transmitting the test instruction to the FPGA through the NCSI; s3, responding to the FPGA to receive the test instruction, analyzing the test instruction, acquiring test object information, and sending the test instruction to the peripheral connected with the FPGA according to the test object information so as to execute a test; and S4, responding to the completion of the peripheral test, and returning a test result to the BMC chip through the FPGA.
In some embodiments, the steps further comprise: and controlling the CPU of the host or the CPU of the network card to test the PCIe interface based on the BMC chip.
In some embodiments, the controlling the CPU of the host or the CPU of the network card to test the PCIe interface based on the BMC chip includes: and controlling the CPU of the host or the CPU of the network card to perform rescanning enumeration of PCIe equipment based on the BMC chip so as to confirm whether the functions of a first PCIe interface connected with the host by the FPGA and a second PCIe interface connected with the CPU of the network card by the FPGA are all normal.
In some embodiments, the steps further comprise: and directly judging whether the flash memory connected with the FPGA is normal or not based on the BMC chip.
In some embodiments, the steps further comprise: and responding to the fact that the flash memory connected with the FPGA is normal, and programming the flash memory connected with the FPGA through the BMC chip to update the FPGA firmware.
In some embodiments, the steps further comprise: and responding to the completion of programming, and controlling the FPGA to start and load a test program of the FPGA based on the BMC chip.
In some embodiments, the steps further comprise: and controlling the CPU of the network card to update and upgrade based on the BMC chip.
The method for testing the intelligent network card can greatly reduce the hardware debugging cable and cable connection operation required by the intelligent network card hardware production test by combining a targeted software testing framework in a simple hardware optimization mode, reduce the complexity of an intelligent network card hardware production testing platform and improve the hardware production testing efficiency. The testing method of the invention presents a universal network interface for the upper layer of the testing application, which is convenient for expanding the testing platform by means of equipment such as a switch and the like to test a plurality of intelligent network cards at the same time. In addition, the connection between the BMC and the FPGA and the connection between the BMC and the host can be realized by using a customized cable, and the connection signals are simpler and have low speed, and can be realized only by simple hardware cost.
Fig. 4 is a schematic hardware structure of an embodiment of the computer device for testing a network card according to the present invention.
Taking the example of the apparatus shown in fig. 4, the apparatus includes a processor 201 and a memory 202, and may further include: an input device 203 and an output device 204.
The processor 201, memory 202, input devices 203, and output devices 204 may be connected by a bus or other means, for example in fig. 4.
The memory 202 is used as a non-volatile computer readable storage medium for storing non-volatile software programs, non-volatile computer executable programs and modules, such as program instructions/modules corresponding to the method for testing a network card in the embodiment of the present application. The processor 201 executes various functional applications of the server and data processing, that is, a method of testing a network card implementing the above-described method embodiment, by running nonvolatile software programs, instructions, and modules stored in the memory 202.
Memory 202 may include a storage program area that may store an operating system, at least one application program required for functionality, and a storage data area; the storage data area may store data created according to the use of the method of testing the network card, etc. In addition, memory 202 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 202 may optionally include memory located remotely from processor 201, which may be connected to the local module via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The input device 203 may receive input information such as a user name and a password. The output device 204 may include a display device such as a display screen.
Program instructions/modules corresponding to one or more methods of testing a network card are stored in the memory 202, which when executed by the processor 201, perform the method of testing a network card in any of the method embodiments described above.
Any one embodiment of the computer device executing the method for testing the network card can achieve the same or similar effects as any one embodiment of the method corresponding to the embodiment.
The invention also provides a computer readable storage medium storing a computer program which when executed by a processor performs a method of testing a network card. The method for testing the network card comprises the following steps: connecting a BMC chip in a network card with an FPGA in the network card through NCSI, and connecting the BMC chip with a host inserted into the network card through an I2C interface; transmitting a test instruction to the BMC chip based on a management network port, and transmitting the test instruction to the FPGA through the NCSI; responding to the FPGA to receive the test instruction, analyzing the test instruction, acquiring test object information, and sending the test instruction to a peripheral connected with the FPGA according to the test object information so as to execute a test; and responding to the completion of the peripheral test, and returning a test result to the BMC chip through the FPGA.
In some embodiments, the method further comprises: and controlling the CPU of the host or the CPU of the network card to test the PCIe interface based on the BMC chip.
In some embodiments, the controlling the CPU of the host or the CPU of the network card to test the PCIe interface based on the BMC chip includes: and controlling the CPU of the host or the CPU of the network card to perform rescanning enumeration of PCIe equipment based on the BMC chip so as to confirm whether the functions of a first PCIe interface connected with the host by the FPGA and a second PCIe interface connected with the CPU of the network card by the FPGA are all normal.
In some embodiments, the method further comprises: and directly judging whether the flash memory connected with the FPGA is normal or not based on the BMC chip.
In some embodiments, the method further comprises: and responding to the fact that the flash memory connected with the FPGA is normal, and programming the flash memory connected with the FPGA through the BMC chip to update the FPGA firmware.
In some embodiments, the method further comprises: and responding to the completion of programming, and controlling the FPGA to start and load a test program of the FPGA based on the BMC chip.
In some embodiments, the method further comprises: and controlling the CPU of the network card to update and upgrade based on the BMC chip.
Fig. 5 is a schematic diagram of an embodiment of a computer storage medium of the above test network card according to the present invention. Taking a computer storage medium as shown in fig. 5 as an example, the computer readable storage medium 3 stores a computer program 31 that when executed by a processor performs the above method.
Finally, it should be noted that, as will be understood by those skilled in the art, all or part of the processes in the methods of the embodiments described above may be implemented by a computer program to instruct related hardware, and the program of the method for testing a network card may be stored in a computer readable storage medium, where the program may include the processes of the embodiments of the methods described above when executed. The storage medium of the program may be a magnetic disk, an optical disk, a read-only memory (ROM), a random-access memory (RAM), or the like. The computer program embodiments described above may achieve the same or similar effects as any of the method embodiments described above.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that as used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The foregoing embodiment of the present invention has been disclosed with reference to the number of embodiments for the purpose of description only, and does not represent the advantages or disadvantages of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program for instructing relevant hardware, and the program may be stored in a computer readable storage medium, where the storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will appreciate that: the above discussion of any embodiment is merely exemplary and is not intended to imply that the scope of the disclosure of embodiments of the invention, including the claims, is limited to such examples; combinations of features of the above embodiments or in different embodiments are also possible within the idea of an embodiment of the invention, and many other variations of the different aspects of the embodiments of the invention as described above exist, which are not provided in detail for the sake of brevity. Therefore, any omission, modification, equivalent replacement, improvement, etc. of the embodiments should be included in the protection scope of the embodiments of the present invention.

Claims (10)

1. A method of testing a network card, comprising the steps of:
Connecting a BMC chip in a network card with an FPGA in the network card through NCSI, and connecting the BMC chip with a host inserted into the network card through an I2C interface;
transmitting a test instruction to the BMC chip based on a management network port, and transmitting the test instruction to the FPGA through the NCSI;
Analyzing the test instruction and acquiring test object information in response to the test instruction received by the FPGA, and sending the test instruction to the peripheral connected with the FPGA according to the test object information to execute a test, wherein NCSI is responsible for analyzing the test instruction transmitted by the BMC chip, analyzing the test object in the test instruction, then transmitting the test instruction to an interconnection module in the FPGA, and the interconnection module is responsible for distributing the test instruction to each test module of the FPGA according to the test object and starting the test operation of each hardware peripheral; and
And responding to the completion of the peripheral test, and returning a test result to the BMC chip through the FPGA.
2. The method according to claim 1, wherein the method further comprises:
And controlling the CPU of the host or the CPU of the network card to test the PCIe interface based on the BMC chip.
3. The method of claim 2, wherein the controlling the CPU of the host or the CPU of the network card to test the PCIe interface based on the BMC chip comprises:
And controlling the CPU of the host or the CPU of the network card to perform rescanning enumeration of PCIe equipment based on the BMC chip so as to confirm whether the functions of a first PCIe interface connected with the host by the FPGA and a second PCIe interface connected with the CPU of the network card by the FPGA are all normal.
4. The method according to claim 1, wherein the method further comprises:
and directly judging whether the flash memory connected with the FPGA is normal or not based on the BMC chip.
5. The method according to claim 4, wherein the method further comprises:
And responding to the fact that the flash memory connected with the FPGA is normal, and programming the flash memory connected with the FPGA through the BMC chip to update the FPGA firmware.
6. The method of claim 5, wherein the method further comprises:
And responding to the completion of programming, and controlling the FPGA to start and load a test program of the FPGA based on the BMC chip.
7. The method according to claim 1, wherein the method further comprises:
And controlling the CPU of the network card to update and upgrade based on the BMC chip.
8. A system for testing a network card, comprising:
The setting module is configured to connect a BMC chip in a network card with an FPGA in the network card through NCSI and connect the BMC chip with a host inserted into the network card through an I2C interface;
The transmission module is configured to transmit a test instruction to the BMC chip based on a management network port and transmit the test instruction to the FPGA through the NCSI;
The testing module is configured to respond to the FPGA to receive the testing instruction, analyze the testing instruction, acquire testing object information, and send the testing instruction to the peripheral connected with the FPGA according to the testing object information to execute testing, wherein NCSI is responsible for analyzing the testing instruction transmitted by the BMC chip, analyzing the testing object in the testing instruction, then transmitting the testing instruction to an interconnection module in the FPGA, and the interconnection module is responsible for distributing the testing instruction to each testing module of the FPGA according to the testing object to start the testing operation of each hardware peripheral; and
And the return module is configured to return a test result to the BMC chip through the FPGA in response to the completion of the peripheral test.
9. A computer device, comprising:
At least one processor; and
A memory storing computer instructions executable on the processor, which when executed by the processor, perform the steps of the method of any one of claims 1-7.
10. A computer readable storage medium storing a computer program, characterized in that the computer program when executed by a processor implements the steps of the method of any one of claims 1-7.
CN202110682314.4A 2021-06-20 2021-06-20 Method, system, equipment and medium for testing network card Active CN113608935B (en)

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