CN116679251A - Sensor chip test calibration system and test calibration method - Google Patents
Sensor chip test calibration system and test calibration method Download PDFInfo
- Publication number
- CN116679251A CN116679251A CN202310664968.3A CN202310664968A CN116679251A CN 116679251 A CN116679251 A CN 116679251A CN 202310664968 A CN202310664968 A CN 202310664968A CN 116679251 A CN116679251 A CN 116679251A
- Authority
- CN
- China
- Prior art keywords
- test
- testing
- tested
- sensor
- sensor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 258
- 238000000034 method Methods 0.000 title claims abstract description 13
- 230000007246 mechanism Effects 0.000 claims abstract description 161
- 238000004891 communication Methods 0.000 claims abstract description 6
- 239000002699 waste material Substances 0.000 claims description 5
- 238000007599 discharging Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000001514 detection method Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 230000009471 action Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 239000008358 core component Substances 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R35/00—Testing or calibrating of apparatus covered by the other groups of this subclass
- G01R35/005—Calibrating; Standards or reference devices, e.g. voltage or resistance standards, "golden" references
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
- G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
- G01R1/0425—Test clips, e.g. for IC's
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Testing Or Calibration Of Command Recording Devices (AREA)
Abstract
The application discloses a sensor chip test calibration system and a test calibration method, relates to the technical field of sensor tests, and is used for improving the test calibration efficiency of a sensor chip so as to reduce the test calibration cost. The sensor chip test calibration system includes: the control device is in communication connection with the first grabbing mechanism, the second grabbing mechanism, the first testing mechanism and the second testing mechanism. The control device controls the first grabbing mechanism to integrally move the plurality of sensor chips to be tested which are arranged according to the preset positions to a plurality of test areas of the second testing mechanism after the plurality of sensor chips to be tested are placed on the first testing mechanism according to the preset positions, and simultaneously controls the second grabbing mechanism to move out the plurality of sensor chips which are tested and/or calibrated on the second testing mechanism from the second testing mechanism; each test area is used for accommodating a plurality of sensor chips to be tested. The control device also controls the second testing mechanism to test and/or calibrate the sensor chip to be tested.
Description
Technical Field
The application relates to the technical field of sensor testing, in particular to a sensor chip testing and calibrating system and a sensor chip testing and calibrating method.
Background
The sensor is used as a detection device, and can convert measured information into electric signals or other signals to be output according to a certain rule, so that the requirements of information transmission, processing, storage, display, recording, control and the like are met, and the sensor is a primary link for realizing automatic detection and automatic control. As a core component of the sensor, testing and calibration of the sensor chip is particularly important.
Currently, chip testing is generally performed by using a single-station or four-station test socket. When testing a sensor chip using a conventional chip test socket, the sensor chip needs to wait for a long enough time (several tens of seconds) to ensure the stability of the test environment.
Based on this, how to improve the test calibration efficiency of the sensor chip and reduce the test calibration time cost becomes a problem to be solved.
Disclosure of Invention
The application aims to provide a sensor chip test calibration system and a test calibration method, which are used for improving the test calibration efficiency of a sensor chip so as to reduce the test calibration cost.
In order to achieve the above object, the present application provides the following technical solutions:
in a first aspect, the present application provides a sensor chip test calibration system comprising: the control device is in communication connection with the first grabbing mechanism, the second grabbing mechanism, the first testing mechanism and the second testing mechanism. The control device is used for controlling the first grabbing mechanism to integrally move the plurality of sensor chips to be tested which are arranged according to the preset positions to a plurality of test areas of the second testing mechanism after the plurality of sensor chips to be tested are placed on the first testing mechanism according to the preset positions, and simultaneously controlling the second grabbing mechanism to move out the plurality of sensor chips which are tested and/or calibrated on the second testing mechanism from the second testing mechanism; wherein each test area is used for accommodating a plurality of sensor chips to be tested. The control device is also used for controlling the second testing mechanism to test and/or calibrate the sensor chip to be tested.
Compared with the prior art, in the sensor chip test calibration system provided by the application, the second test mechanism is provided with the plurality of test areas, and each test area can accommodate a plurality of sensor chips to be tested, so that the second test mechanism can test the plurality of sensor chips to be tested under the action of the control device.
In addition, after the plurality of sensor chips to be tested are placed on the first testing mechanism according to the preset positions, the control device can control the first grabbing mechanism to integrally move the plurality of sensor chips to be tested which are arranged according to the preset positions into a plurality of testing areas of the second testing mechanism, and meanwhile, control the second grabbing mechanism to move the sensor chips which are tested and/or calibrated out of the second testing mechanism. That is, in the time of waiting for the plurality of sensor chips to be tested to be placed on the first test mechanism according to the preset sequence, the plurality of sensor chips to be tested which are already placed on the second test mechanism are synchronously tested and/or calibrated, and when the plurality of sensor chips to be tested are completely placed on the first test mechanism according to the preset positions, the second test mechanism also synchronously completes the test and/or calibration of the plurality of sensor chips to be tested, so that the waiting time consumed by the plurality of sensor chips to be tested for ensuring the stability of the test environment is saved to a certain extent, the test and calibration efficiency is improved, and the time cost of the test and calibration is saved.
Therefore, the sensor chip test calibration system provided by the application can improve the test calibration efficiency of the sensor chip, thereby reducing the test calibration cost.
In a second aspect, the present application further provides a sensor chip test calibration method, which is applied to the sensor chip test calibration system according to the above first aspect, where the sensor chip test calibration method includes: the control device controls the first grabbing mechanism to integrally move the plurality of sensor chips to be tested which are arranged according to the preset positions to a plurality of test areas of the second testing mechanism after the plurality of sensor chips to be tested are placed on the first testing mechanism according to the preset positions, and simultaneously controls the second grabbing mechanism to move out the plurality of sensor chips which are tested and/or calibrated on the second testing mechanism from the second testing mechanism; wherein each test area is used for accommodating a plurality of sensor chips to be tested. The control device also controls the second testing mechanism to test and/or calibrate the sensor chip to be tested.
Compared with the prior art, the beneficial effects of the sensor chip test calibration method provided by the application are the same as those of the sensor chip test calibration system in the technical scheme, and the description is omitted here.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. In the drawings:
FIG. 1 is a schematic diagram of a sensor chip test calibration system according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of a second testing mechanism according to an embodiment of the present application.
Reference numerals:
1-a control device, 2-a first test mechanism,
3-a first grabbing mechanism, 4-a second testing mechanism,
5-second gripping means, 41-test area,
411-reference chip, 412-recess,
413-channel.
Detailed Description
In order to clearly describe the technical solution of the embodiments of the present application, in the embodiments of the present application, the words "first", "second", etc. are used to distinguish the same item or similar items having substantially the same function and effect. For example, the first threshold and the second threshold are merely for distinguishing between different thresholds, and are not limited in order. It will be appreciated by those of skill in the art that the words "first," "second," and the like do not limit the amount and order of execution, and that the words "first," "second," and the like do not necessarily differ.
In the present application, the words "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.
In the present application, "at least one" means one or more, and "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a alone, a and B together, and B alone, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b or c may represent: a, b, c, a and b, a and c, b and c, or a, b and c, wherein a, b, c can be single or multiple.
The sensor is used as a detection device, and can convert measured information into electric signals or other signals to be output according to a certain rule, so that the requirements of information transmission, processing, storage, display, recording, control and the like are met, and the sensor is a primary link for realizing automatic detection and automatic control. As a core component of the sensor, testing and calibration of the sensor chip is particularly important.
The existing chip test system generally adopts a single-station or four-station test seat for testing, and the bottleneck of the test speed is the grabbing time of the chip because the test time of the chip is very short (millisecond level). While for the sensor chip it is necessary to wait a long enough time (tens of seconds) to ensure the stability of the test environment (temperature, humidity, gas concentration, etc.). If a test system with a few stations is also used, the test speed bottleneck of the system is no longer the capture time, but rather the settling time of the sensor chip.
Based on this, how to improve the test calibration efficiency of the sensor chip and reduce the test calibration time cost becomes a problem to be solved.
In order to solve the above technical problems, as shown in fig. 1, an embodiment of the present application provides a sensor chip test calibration system, including: the control device 1, a first grabbing mechanism 3, a second grabbing mechanism 5, a first testing mechanism 2 and a second testing mechanism 4 which are in communication connection with the control device 1. The control device 1 is configured to control, after a plurality of sensor chips to be tested are placed on the first testing mechanism 2 according to a preset position, the first grabbing mechanism 3 to integrally move the plurality of sensor chips to be tested arranged according to the preset position to a plurality of testing areas 41 of the second testing mechanism 4, and simultaneously control the second grabbing mechanism 5 to move out a plurality of sensor chips tested and/or calibrated on the second testing mechanism 4 from the second testing mechanism 4; wherein each test area 41 is adapted to accommodate a plurality of sensor chips to be tested. The control device 1 is further used for controlling the second test mechanism 4 to test and/or calibrate the sensor chip to be tested.
Under the condition of adopting the technical scheme, the method comprises the following steps: the second testing mechanism 4 is provided with a plurality of testing areas 41, and each testing area 41 can accommodate a plurality of sensor chips to be tested, so that the second testing mechanism 4 can test the plurality of sensor chips to be tested simultaneously under the action of the control device 1.
In addition, after the plurality of sensor chips to be tested are placed on the first testing mechanism 2 according to the preset positions, the control device 1 may control the first grabbing mechanism 3 to integrally move the plurality of sensor chips to be tested arranged according to the preset positions into the plurality of testing areas 41 of the second testing mechanism 4, and at the same time, control the second grabbing mechanism 5 to move the sensor chips that have been tested and/or calibrated out of the second testing mechanism 4. That is, in the time of waiting for the plurality of sensor chips to be tested to be placed on the first testing mechanism 2 in the preset order, the plurality of sensor chips to be tested that have been placed on the second testing mechanism 4 are also being tested and/or calibrated synchronously, and when the plurality of sensor chips to be tested are completely placed on the first testing mechanism 2 in the preset position, the second testing mechanism 4 also completes testing and/or calibrating the plurality of sensor chips to be tested synchronously, thereby saving waiting time consumed by the plurality of sensor chips to be tested for ensuring stable testing environment to a certain extent, further improving testing and calibrating efficiency and saving time cost of testing and calibrating.
Therefore, the sensor chip test calibration system provided by the embodiment of the application can improve the test calibration efficiency of the sensor chip, thereby reducing the test calibration cost.
In the present application, the first grabbing mechanism 3 and the second grabbing mechanism 5 may be suction cups or any mechanical arm or manipulator capable of implementing grabbing operation, which is not limited in particular in the embodiment of the present application.
In one possible implementation, as shown in fig. 2, each test area 41 is provided with a reference chip 411, and a plurality of grooves 412 at the outer periphery of the reference chip 411. The plurality of grooves 412 are configured to receive corresponding sensor chips to be tested. The reference chip 411 is used to provide reference parameters for testing and/or calibration to the sensor chip under test when the sensor chip under test is placed in the recess 412.
Based on this, when the sensor chip to be measured is placed on the recess 412, its neighboring reference chip 411 may provide a reference parameter so that the relevant parameter of the sensor chip to be measured may be calibrated to coincide with the reference parameter of the reference chip 411, thereby ensuring the accuracy of the test and/or calibration.
In practice, in order to ensure the accuracy of the test and/or calibration, each groove 412 should be adjacent to at least the reference chip 411, but if one reference chip 411 is disposed around each groove 412, this will result in too many reference chips 411, and thus an excessively large area of the second test mechanism 4, so that the grooves 412 may be disposed on the outer periphery of the reference chip 411 to meet the purpose that each groove 412 can be adjacent to the reference chip 411, while also reducing the number of reference chips 411.
In some embodiments, the second testing mechanism 4 is further provided with a plurality of channels 413 for communicating each of the grooves 412 with the corresponding reference chip 411. By the arrangement, air flow between the reference chip 411 and the tested sensor chip can be kept smooth, and the test environments of the reference chip 411 and the tested sensor chip are further guaranteed to be strictly consistent, such as parameters of ambient temperature, ambient humidity or gas concentration, so that stability of the test environments is guaranteed, and accuracy of testing and/or calibration is improved.
In practice, not only the channel 413 may be formed between the reference chip 411 and the groove 412, but also the channel 413 may be formed between the groove 412 and the groove 412, so that the test environments of the plurality of test areas 41 on the second test mechanism 4 can be kept consistent, errors in testing and/or calibrating the sensor chips to be tested in the same batch are avoided, and the accuracy in testing and/or calibrating the sensor chips to be tested in the same batch is further improved.
In some embodiments, each reference chip 411 is located at the geometric center of the formed geometry surrounded by a plurality of grooves 412 on the periphery.
Specifically, when the reference chip 411 is located at the geometric center of the geometric shape formed by surrounding the plurality of grooves 412 on the periphery, the distance between each groove 412 on the periphery of the reference chip 411 and the corresponding reference chip 411 is approximately equal, so that testing and/or calibration errors caused by the distance between the sensor chip to be tested and the reference chip 411 can be further avoided. For example, when the geometry formed by surrounding the plurality of grooves 412 is a circle, the reference chip 411 may be disposed at the center of the circle; when the geometry of the plurality of grooves 412 is rectangular, the reference chip 411 may be disposed at the intersection of the diagonal lines of the rectangle; when the geometry of the plurality of grooves 412 is formed in an equilateral triangle, the reference chip 411 may be disposed at the midpoint of the equilateral triangle. In practice, the geometry formed by surrounding the plurality of grooves 412 may be any other regular geometry according to the area and shape of the second testing mechanism 4, which is not particularly limited in the embodiment of the present application.
Exemplary, as shown in fig. 2, an embodiment of the present application provides an arrangement of a reference chip 411 and a plurality of grooves 412. When each test area 41 includes 8 grooves 412, the geometry formed by surrounding the 8 grooves 412 is square, and the corresponding reference chip 411 is located at the geometric center of the square.
Specifically, each 8 grooves 412 and the reference chip 411 may be arranged according to a nine-grid structure, that is, each 8 grooves 412 and the reference chip 411 in the center thereof form a test area 41, and during testing and/or calibration, 8 sensor chips to be tested placed in the surrounding 8 grooves 412 are aligned with the enclosed reference chip 411.
Fig. 2 illustrates a case in which the number of test areas 41 is 4, whereby 4*8 =32 sensor chips to be tested can be tested and/or calibrated at one time on the second test mechanism 4. In practice, the number of the test areas 41 may be set to 2, 3, 5 or more according to the area size of the second test mechanism 4, which is not particularly limited in the embodiment of the present application.
In some embodiments, the sensor chip test calibration system further includes a third grabbing mechanism, where the third grabbing mechanism is in communication with the control device 1, and the control device 1 is further configured to control the third grabbing mechanism to place each sensor chip to be tested on the first test mechanism 2 according to a preset position.
In a specific implementation, the third grabbing mechanism may be any mechanical arm or mechanical arm capable of implementing pick-up and placement operations, and the control device 1 may control the third grabbing mechanism to take out the sensor chip to be tested from the braid or the tray, and place the sensor chip to be tested on the first test mechanism 2 according to a preset position, so that the first grabbing mechanism 3 integrally moves the plurality of sensor chips to be tested arranged according to the preset position onto the second test mechanism 4.
In some embodiments, when the number of sensor chips to be measured that are gripped by the third gripping mechanism per second is n, and the test and/or calibration time of each sensor chip to be measured on the second testing mechanism 4 is m seconds, the number of grooves 412 on the second testing mechanism 4 is m×n.
In practice, the number of grooves 412 provided on the second testing mechanism 4 needs to comprehensively consider the testing and/or calibration time of each sensor chip to be tested, and the time for the third grabbing mechanism to grab and place the sensor chip to be tested. When the number of the sensor chips to be tested gripped by the third gripping mechanism per second is n, and the test and/or calibration time of each sensor chip to be tested on the second testing mechanism 4 is m seconds, preferably, the number of the grooves 412 on the second testing mechanism 4 is m×n.
When the number of grooves 412 on the second testing mechanism 4 is less than m×n, the overall testing and/or calibration speed is lower than the speed of grabbing and placing by the third grabbing mechanism, and the advantage of high speed of the mechanical arm or the mechanical arm cannot be exerted. When the number of grooves 412 on the second test mechanism 4 is greater than m×n, the overall test and/or calibration speed is equal to the speed of grasping and placing by the third grasping mechanism, but the complexity of the second test mechanism 4 is increased. Meanwhile, since a plurality of sensor chips to be tested need to be tested at the same time, the model reliability and the possibility of signal crosstalk of each sensor chip to be tested need to be considered, and the complexity of a test circuit can be further increased. Based on this, in order to achieve an optimal test efficiency of the sensor chip test calibration system while reducing the complexity of the test circuit, the number of grooves 412 on the second test mechanism 4 is optimally selected to be m×n.
In some embodiments, the arrangement of the plurality of sensor chips under test on the first testing mechanism 2, the arrangement of the plurality of sensor chips under test on the first grabbing mechanism 3, and the arrangement of the plurality of sensor chips under test on the second grabbing mechanism 5 are matched to the arrangement of the plurality of grooves 412 on the second testing mechanism 4.
It can be appreciated that, in order to further improve the efficiency of the sensor chip testing and calibrating system, the handling time of the first grabbing mechanism 3 and the second grabbing mechanism 5 is shortened, so that the arrangement shape of the plurality of sensor chips to be tested on the first testing mechanism 2, the arrangement shape of the plurality of sensor chips to be tested on the first grabbing mechanism 3, and the arrangement shape of the plurality of sensor chips to be tested on the second grabbing mechanism 5 are all matched with the arrangement shape of the plurality of grooves 412 on the second testing mechanism 4, so that when the third grabbing mechanism places the plurality of sensor chips to be tested on the first testing mechanism 2 according to the preset position, the first grabbing mechanism 3 can integrally handle the plurality of sensor chips to be tested on the second testing mechanism 4, thereby avoiding the time for placing the plurality of sensor chips to be tested on the second testing mechanism 4.
For example, when the arrangement of the grooves 412 on the second testing mechanism 4 is as shown in fig. 2, the corresponding chip placement positions on the first testing mechanism 2 should also be as shown in fig. 2, and only the positions of the reference chips 411 need to be left empty. Similarly, the chip placement position on the first gripper 3 and the chip placement position on the second gripper 5 can be referred to as the groove 412 position shown in fig. 2.
It can be appreciated that, in order to distinguish between a sensor chip that is qualified for testing and/or calibration and a sensor chip that is unqualified for testing and/or calibration, the sensor chip testing and calibration system provided by the embodiment of the application further includes a discharging seat and a waste seat. The control device 1 is also used for controlling the second grabbing mechanism 5 to move a plurality of sensor chips which are qualified in test and/or calibration from the second testing mechanism 4 to the discharging seat. Or, the control device 1 is further used for controlling the second grabbing mechanism 5 to move the plurality of sensor chips which are not qualified in test and/or calibration from the second testing mechanism 4 to the waste seat.
Based on this, when the second testing mechanism 4 finishes testing and/or calibrating the plurality of sensor chips to be tested, the control device 1 may control the second grabbing mechanism 5 to move the qualified sensor chips to the discharging seat, and control the second grabbing mechanism 5 to move the unqualified sensor chips to the waste seat. It should be noted that the failed sensor chip should have undergone at least one test-calibration-test procedure, and only the sensor chip that is not passed by the test after the calibration can be regarded as the failed sensor chip, so as to avoid wasting and increase the test cost.
The embodiment of the application also provides a sensor chip test calibration method which is applied to the sensor chip test calibration system provided in the embodiment, and comprises the following steps: the control device controls the first grabbing mechanism to integrally move a plurality of sensor chips to be tested which are arranged in an array on the first testing mechanism to a plurality of testing areas which are arranged in an array on the second testing mechanism, and also simultaneously controls the second grabbing mechanism to move out the plurality of sensor chips which are tested and/or calibrated on the second testing mechanism from the second testing mechanism; wherein each test area is used for accommodating a plurality of sensor chips to be tested. The control device also controls the second testing mechanism to test and/or calibrate the plurality of sensor chips to be tested.
Compared with the prior art, the beneficial effects of the sensor chip test calibration method provided by the embodiment of the application are the same as those of the sensor chip test calibration system provided in the above embodiment, and the description thereof is omitted here.
Although the application is described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
Although the application has been described in connection with specific features and embodiments thereof, it will be apparent that various modifications and combinations can be made without departing from the spirit and scope of the application. Accordingly, the specification and drawings are merely exemplary illustrations of the present application as defined in the appended claims and are considered to cover any and all modifications, variations, combinations, or equivalents that fall within the scope of the application. It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (10)
1. A sensor chip test calibration system, comprising: the control device, with the first mechanism that snatchs, second snatchs mechanism, first testing mechanism and second testing mechanism of controlling means communication connection, wherein:
the control device is used for controlling the first grabbing mechanism to integrally move the plurality of sensor chips to be tested, which are arranged according to the preset positions, to a plurality of test areas of the second testing mechanism after the plurality of sensor chips to be tested are placed on the first testing mechanism according to the preset positions, and simultaneously controlling the second grabbing mechanism to move the plurality of sensor chips which are tested and/or calibrated on the second testing mechanism out of the second testing mechanism; wherein each test area is used for accommodating a plurality of sensor chips to be tested;
the control device is also used for controlling the second testing mechanism to test and/or calibrate the sensor chip to be tested.
2. The sensor chip test calibration system of claim 1, wherein each of the test areas is provided with a reference chip and a plurality of grooves on an outer periphery of the reference chip;
the grooves are used for accommodating the corresponding sensor chips to be tested;
the reference chip is used for providing reference parameters for testing and/or calibrating to the sensor chip to be tested when the sensor chip to be tested is placed in the groove.
3. The sensor chip testing and calibration system of claim 2, further comprising a third grasping mechanism in communication with the control device, the control device being configured to place each of the sensor chips under test on the first test mechanism in the predetermined position, respectively, when controlling the third grasping mechanism.
4. A sensor chip test calibration system according to claim 3, wherein when the number of the sensor chips to be tested gripped by the third gripping mechanism per second is n and the test and/or calibration time of each sensor chip to be tested on the second testing mechanism is m seconds, the number of grooves on the second testing mechanism is m x n.
5. The sensor chip testing and calibration system of claim 2, wherein the second testing mechanism is further provided with a plurality of channels for communicating each of the grooves with the corresponding reference chip.
6. The sensor chip test calibration system of claim 2, wherein each reference chip is located at a geometric center of a geometric shape defined by a plurality of said grooves of the periphery.
7. The sensor chip testing calibration system of claim 6, wherein when each test area includes 8 of said grooves, the geometry of the surrounding formation of the 8 grooves is square, and the corresponding reference chip is located at the geometric center of the square.
8. The sensor chip testing and calibration system of claim 2, wherein the arrangement of the plurality of sensor chips under test on the first test mechanism, the arrangement of the plurality of sensor chips under test on the first capture mechanism, and the arrangement of the plurality of sensor chips under test on the second capture mechanism all match the arrangement of the plurality of grooves on the second test mechanism.
9. The sensor chip testing calibration system of claim 1, further comprising a outfeed tray and a waste tray;
the control device is also used for controlling the second grabbing mechanism to move the plurality of sensor chips which are qualified in test and/or calibration from the second testing mechanism to the discharging seat;
or, the control device is further used for controlling the second grabbing mechanism to move the plurality of sensor chips which are unqualified in testing and/or calibration from the second testing mechanism to the waste seat.
10. A sensor chip test calibration method applied to the sensor chip test calibration system of any one of claims 1 to 9, characterized in that the sensor chip test calibration method comprises:
the control device controls the first grabbing mechanism to integrally move the plurality of sensor chips to be tested, which are arranged according to the preset positions, to a plurality of test areas of the second testing mechanism after the plurality of sensor chips to be tested are placed on the first testing mechanism according to the preset positions, and simultaneously controls the second grabbing mechanism to move out the plurality of sensor chips which are tested and/or calibrated on the second testing mechanism from the second testing mechanism; wherein each test area is used for accommodating a plurality of sensor chips to be tested;
the control device also controls the second testing mechanism to test and/or calibrate the sensor chip to be tested.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202310664968.3A CN116679251A (en) | 2023-06-06 | 2023-06-06 | Sensor chip test calibration system and test calibration method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202310664968.3A CN116679251A (en) | 2023-06-06 | 2023-06-06 | Sensor chip test calibration system and test calibration method |
Publications (1)
Publication Number | Publication Date |
---|---|
CN116679251A true CN116679251A (en) | 2023-09-01 |
Family
ID=87783257
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202310664968.3A Pending CN116679251A (en) | 2023-06-06 | 2023-06-06 | Sensor chip test calibration system and test calibration method |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN116679251A (en) |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106768487A (en) * | 2017-01-16 | 2017-05-31 | 中国科学院半导体研究所 | The construction method and system of the temperature environment of temperature sensor chip detection calibration |
CN109712924A (en) * | 2018-12-29 | 2019-05-03 | 哈工大机器人(山东)智能装备研究院 | A kind of infrared focal plane array chip automated test device |
CN210154610U (en) * | 2019-08-07 | 2020-03-17 | 河南省计量科学研究院 | Sensor arrangement device for calibration of constant temperature and humidity test box |
CN111965527A (en) * | 2020-08-24 | 2020-11-20 | 前海晶云(深圳)存储技术有限公司 | Chip testing assembly line and chip testing method |
WO2021189322A1 (en) * | 2020-03-25 | 2021-09-30 | 华为技术有限公司 | Chip testing apparatus and chip testing method |
CN215893841U (en) * | 2021-09-23 | 2022-02-22 | 浙大城市学院 | Novel temperature sensor's that hexagon was arranged high accuracy test device |
CN115200747A (en) * | 2022-08-26 | 2022-10-18 | 中国科学院半导体研究所 | Calibration device for temperature sensor |
-
2023
- 2023-06-06 CN CN202310664968.3A patent/CN116679251A/en active Pending
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106768487A (en) * | 2017-01-16 | 2017-05-31 | 中国科学院半导体研究所 | The construction method and system of the temperature environment of temperature sensor chip detection calibration |
CN109712924A (en) * | 2018-12-29 | 2019-05-03 | 哈工大机器人(山东)智能装备研究院 | A kind of infrared focal plane array chip automated test device |
CN210154610U (en) * | 2019-08-07 | 2020-03-17 | 河南省计量科学研究院 | Sensor arrangement device for calibration of constant temperature and humidity test box |
WO2021189322A1 (en) * | 2020-03-25 | 2021-09-30 | 华为技术有限公司 | Chip testing apparatus and chip testing method |
CN111965527A (en) * | 2020-08-24 | 2020-11-20 | 前海晶云(深圳)存储技术有限公司 | Chip testing assembly line and chip testing method |
CN215893841U (en) * | 2021-09-23 | 2022-02-22 | 浙大城市学院 | Novel temperature sensor's that hexagon was arranged high accuracy test device |
CN115200747A (en) * | 2022-08-26 | 2022-10-18 | 中国科学院半导体研究所 | Calibration device for temperature sensor |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI803012B (en) | TESTING APPARATUS, METHOD OF TESTING DUTs AND TESTING SYSTEM | |
US6897670B2 (en) | Parallel integrated circuit test apparatus and test method | |
JP3412114B2 (en) | IC test equipment | |
US20230197185A1 (en) | Carrier based high volume system level testing of devices with pop structures | |
US9551740B2 (en) | Parallel concurrent test system and method | |
WO1997005496A1 (en) | Semiconductor device tester and semiconductor device testing system with a plurality of semiconductor device testers | |
US5872458A (en) | Method for electrically contacting semiconductor devices in trays and test contactor useful therefor | |
KR20210035308A (en) | Carrier-based test system | |
US20070164771A1 (en) | Apparatus for testing a chip and methods of making and using the same | |
KR20060019572A (en) | Transportation device, electronic component-handling device, and transportation method in electronic component-handling device | |
JP2000065894A (en) | Method and device for testing electronic parts | |
CN108792121A (en) | Automatic labeling based on RFID tag and minute mark system | |
CN113578781A (en) | Chip sorting method, device, equipment and storage medium | |
US7109740B2 (en) | Method for retesting semiconductor device | |
CN116679251A (en) | Sensor chip test calibration system and test calibration method | |
CN112014604A (en) | Wafer testing device, testing system and testing method | |
CN101211808B (en) | Picker for use in a handler and method for enabling the picker to place packaged chips | |
CN105983538B (en) | High-yield test sorting machine system | |
KR100498496B1 (en) | Testing method of remnant semiconductor device | |
WO2014003238A1 (en) | Insert assembly and electronic component accommodation apparatus including same | |
US20110254579A1 (en) | Semiconductor test method and semiconductor test system | |
WO2019064876A1 (en) | Testing system and testing method | |
US6781363B2 (en) | Memory sorting method and apparatus | |
US8346498B2 (en) | Programmable device testing | |
KR20030003125A (en) | Improvement in testing methodology for smd bga and csp packages |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination |