CN115148852B - Preparation method of double-sided topcon battery - Google Patents
Preparation method of double-sided topcon battery Download PDFInfo
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- CN115148852B CN115148852B CN202210778644.8A CN202210778644A CN115148852B CN 115148852 B CN115148852 B CN 115148852B CN 202210778644 A CN202210778644 A CN 202210778644A CN 115148852 B CN115148852 B CN 115148852B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 142
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 142
- 239000010703 silicon Substances 0.000 claims abstract description 142
- 238000002161 passivation Methods 0.000 claims abstract description 33
- 238000000151 deposition Methods 0.000 claims abstract description 25
- 238000009792 diffusion process Methods 0.000 claims abstract description 25
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 11
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052796 boron Inorganic materials 0.000 claims abstract description 11
- 239000011574 phosphorus Substances 0.000 claims abstract description 11
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 11
- 238000000137 annealing Methods 0.000 claims abstract description 10
- 238000005498 polishing Methods 0.000 claims abstract description 10
- 238000005245 sintering Methods 0.000 claims abstract description 10
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 24
- KWYUFKZDYYNOTN-UHFFFAOYSA-M potassium hydroxide Substances [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 claims description 24
- 230000000903 blocking effect Effects 0.000 claims description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 19
- 229920005591 polysilicon Polymers 0.000 claims description 19
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 18
- 239000008367 deionised water Substances 0.000 claims description 12
- 229910021641 deionized water Inorganic materials 0.000 claims description 12
- 239000003480 eluent Substances 0.000 claims description 12
- JVTAAEKCZFNVCJ-UHFFFAOYSA-N lactic acid Chemical compound CC(O)C(O)=O JVTAAEKCZFNVCJ-UHFFFAOYSA-N 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 10
- 239000011259 mixed solution Substances 0.000 claims description 7
- 238000004381 surface treatment Methods 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 6
- 239000004310 lactic acid Substances 0.000 claims description 6
- 235000014655 lactic acid Nutrition 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 238000002791 soaking Methods 0.000 claims description 6
- 239000000853 adhesive Substances 0.000 claims description 5
- 230000001070 adhesive effect Effects 0.000 claims description 5
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 4
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 239000003822 epoxy resin Substances 0.000 claims description 3
- 229920000647 polyepoxide Polymers 0.000 claims description 3
- WNROFYMDJYEPJX-UHFFFAOYSA-K aluminium hydroxide Chemical compound [OH-].[OH-].[OH-].[Al+3] WNROFYMDJYEPJX-UHFFFAOYSA-K 0.000 claims description 2
- AXCZMVOFGPJBDE-UHFFFAOYSA-L calcium dihydroxide Chemical compound [OH-].[OH-].[Ca+2] AXCZMVOFGPJBDE-UHFFFAOYSA-L 0.000 claims description 2
- 239000000920 calcium hydroxide Substances 0.000 claims description 2
- 229910001861 calcium hydroxide Inorganic materials 0.000 claims description 2
- 239000003795 chemical substances by application Substances 0.000 claims description 2
- 239000013530 defoamer Substances 0.000 claims description 2
- FPAFDBFIGPHWGO-UHFFFAOYSA-N dioxosilane;oxomagnesium;hydrate Chemical compound O.[Mg]=O.[Mg]=O.[Mg]=O.O=[Si]=O.O=[Si]=O.O=[Si]=O.O=[Si]=O FPAFDBFIGPHWGO-UHFFFAOYSA-N 0.000 claims description 2
- 239000004408 titanium dioxide Substances 0.000 claims description 2
- 230000005641 tunneling Effects 0.000 abstract description 15
- 230000008021 deposition Effects 0.000 abstract description 3
- 235000012431 wafers Nutrition 0.000 abstract 13
- 238000010586 diagram Methods 0.000 description 13
- 238000005468 ion implantation Methods 0.000 description 10
- 238000006243 chemical reaction Methods 0.000 description 5
- 239000012634 fragment Substances 0.000 description 5
- 239000002002 slurry Substances 0.000 description 5
- 239000007767 bonding agent Substances 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 4
- 239000000243 solution Substances 0.000 description 3
- 238000010521 absorption reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000005215 recombination Methods 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- BSYNFGPFPYSTTM-UHFFFAOYSA-N 2-hydroxypropanoic acid;hydrate Chemical compound O.CC(O)C(O)=O BSYNFGPFPYSTTM-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000011056 performance test Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000004804 winding Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
- H01L31/1868—Passivation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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Abstract
The invention relates to the technical field of solar cells, and particularly discloses a preparation method of a double-sided topcon battery. The preparation method comprises the following steps: double-sided texturing is carried out on the N-type silicon wafer; polishing the back surface of the textured silicon wafer; bonding a hollowed mask plate on the front surface of the polished silicon wafer to obtain a pretreated silicon wafer; forming first silicon wafers with passivation structures on the front and back surfaces of the pretreated silicon wafers respectively; removing the hollowed mask plate on the front surface of the first silicon wafer; performing boron diffusion on the front surface of the silicon wafer; performing phosphorus diffusion on the back surface of the silicon wafer; annealing the silicon wafer; and depositing an alumina layer on the front surface of the silicon wafer, then respectively depositing an antireflection film on the front surface and the back surface, printing a grid line electrode, and sintering to obtain the double-sided topcon battery. The application adopts the bonding mode to attach the hollowed mask plate to the front surface of the silicon wafer, and can realize the one-time completion of the deposition of the tunneling passivation layer on the front surface and the back surface of the silicon wafer.
Description
Technical Field
The invention relates to the technical field of solar cells, in particular to a preparation method of a double-sided topcon battery.
Background
The Topcon cell is a tunneling oxide layer passivation contact cell, and the double-sided tunneling passivation layer is prepared on the front side and the back side of the silicon wafer. When the tunneling passivation layer is used on the back of the battery, excellent back surface passivation and carrier collection capability can be provided, and the overall performance of the device is greatly improved. However, the polysilicon layer in the tunneling passivation layer has serious parasitic absorption effect, and can absorb sunlight with a certain wavelength when being used on the front surface of the silicon wafer, so that short-circuit current is reduced. In order to avoid higher parasitic absorption effect, a polysilicon passivation layer is usually prepared at the bottom of a grid line on the front surface of the battery to form a selective structure so as to ensure that passivation of a non-shielding region is not affected. However, in the current preparation process of the above structure, it is necessary to deposit the tunneling passivation layer twice, that is, the tunneling passivation layers on the front and back surfaces are respectively completed in different steps, which not only results in unavoidable influence on the other surface due to plating around after the single surface is completed (that is, the tunneling passivation layer is generated around the periphery of the edge on the other surface), reducing the efficiency of the battery, but also requires printing mask slurry to realize formation of a selective structure on the front surface. Due to the existence of the wrapping plating phenomenon, chemical cleaning is also needed for removal so as to ensure the battery efficiency, and the process steps are additionally added. When the front surface forms the selective structure, the common method is to print mask slurry to form local protection and then to carry out slurry removal process, which results in complicated process steps, greatly reduces the yield of the battery, intangibly increases the production cost, and greatly increases the difficulty of the battery preparation due to the fact that the mask slurry is easy to cause damage to the battery piece in the process of printing and removing the mask slurry. In addition, when diffusion is carried out in the existing preparation process, the winding and the expansion are easy to cause, and the battery efficiency is influenced.
Disclosure of Invention
Aiming at the problems of complicated process steps, low yield and the like of the existing double-sided topcon battery, the invention provides a preparation method of the double-sided topcon battery.
In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:
a method of preparing a double sided topcon battery, the method comprising the steps of:
step one, double-sided texturing is carried out on an N-type silicon wafer;
step two, polishing the back surface of the silicon wafer after texturing;
bonding a hollowed mask plate on the front surface of the polished silicon wafer to obtain a pretreated silicon wafer;
step four, respectively depositing a silicon oxide layer and a polysilicon layer on the front side and the back side of the pretreated silicon wafer in sequence to form a first silicon wafer with a passivation structure on both sides;
step five, removing the hollowed mask plate on the front surface of the first silicon wafer to obtain a second silicon wafer;
step six, performing boron diffusion on the front surface of the second silicon wafer to obtain a third silicon wafer;
step seven, performing phosphorus diffusion on the back surface of the third silicon wafer to obtain a fourth silicon wafer;
step eight, annealing the fourth silicon wafer to obtain a fifth silicon wafer;
and step nine, depositing an alumina layer on the front surface of the fifth silicon wafer, then respectively depositing an antireflection film on the front surface and the back surface, printing a grid line electrode, and sintering to obtain the double-sided topcon battery.
Compared with the prior art, the preparation method of the double-sided topcon battery has the following advantages:
the hollowed mask plate is attached to the front surface of the silicon wafer in a bonding mode, so that the deposition of the tunneling passivation layer on the front surface and the back surface of the silicon wafer can be completed at one time, the preparation process is greatly simplified, excessive technological processes are avoided, and the production cost is remarkably reduced; meanwhile, due to the simplification of the technological process, the influence on the efficiency of the battery is reduced, and the yield of the battery is improved.
The mode of the hollowed mask plate can be matched with a subsequent printed metal electrode, a selective passivation structure is formed in a local tunneling layer deposited area formed in a hollowed area of the hollowed mask plate, the gate line electrode is correspondingly printed on the selective passivation structure, heavy doping of the gate line electrode area can be achieved, and the efficiency of the battery is improved.
Optionally, the adhesive used for bonding comprises a component A and a component B in a mass ratio of 0.8-1.2:0.8-1.2, wherein the component A comprises the following components in parts by mass: 60-80 parts of epoxy resin, 10-30 parts of calcium hydroxide and 1-2 parts of titanium dioxide; the component B comprises the following components in parts by weight: 50 to 70 parts of curing agent, 10 to 30 parts of aluminum hydroxide, 5 to 10 parts of talcum powder and 0.5 to 1.5 parts of defoamer.
Further preferably, the binder is commercially available from Guangzhou Biscow New Material Co., ltd., model SK-807AB.
Alternatively, the adhesive used for bonding is applied in an amount of 0.07g/cm 2 ～0.09g/cm 2 。
Optionally, in the fifth step, the first silicon wafer is placed in an eluent with the temperature of 60-80 ℃ for soaking for 8-12 min, and the front hollow mask plate is removed, wherein the eluent is a mixed solution of lactic acid and water with the volume of 0.5-1.5:1-3.
The applicant finds that the hollow mask plate is directly placed on the surface of the silicon wafer, and because the tunneling passivation layer is prepared under the gas atmosphere condition of the tube furnace, gas inevitably enters a gap where the hollow mask plate contacts with the silicon wafer to react, so that the protection of the hollow mask plate on the silicon wafer coverage area cannot be realized to form local deposition of the silicon wafer, and a certain tunneling passivation layer can still be deposited in the shielding area. The applicant also finds that if the silicon wafer is adhered to the hollowed mask plate, fragments are easy to generate during adhesion and detachment because the silicon wafer is thinner (the thickness is 150-180 mu m), and the fragment rate is about 10% -20%, so that the application adopts the high-temperature-resistant epoxy resin adhesive which is easy to remove to adhere the silicon wafer and the hollowed mask plate, the gap between the silicon wafer and the hollowed mask plate is removed, the tunneling passivation layer is prevented from depositing at the joint of the silicon wafer and the hollowed mask plate, and meanwhile, the simpler and more convenient preparation flow of the double-sided topcon is realized.
The preferable coating amount can tightly bond the hollowed mask plate on the surface of the silicon wafer, and then the silicon wafer is soaked in a lactic acid water mixed solution with the temperature of 60-80 ℃ so that the mask plate is separated from the silicon wafer, and the fragment rate of the silicon wafer is obviously reduced.
Optionally, a plurality of blocking areas with identical widths are distributed on the surface of the hollowed-out mask plate at intervals up and down, hollowed-out areas are arranged between adjacent blocking areas, and the total area of all the hollowed-out areas accounts for 2% -20% of the area of the hollowed-out mask plate, as shown in fig. 2.
Optionally, n gate line modules distributed in an array are disposed on the hollowed mask plate, each gate line module includes a plurality of blocking areas with identical widths, hollowed-out areas located between adjacent blocking areas, and hollowed-out main lines penetrating through all hollowed-out areas, n is 1-12, wherein the total area of hollowed-out areas disposed on the hollowed mask plate accounts for 2% -20% of the area of the hollowed mask plate, as shown in fig. 4 or 6.
Optionally, the hollow mask plate is provided with a plurality of hollow rings which are sequentially distributed from the center to the periphery in a ring-sleeve manner, and is also provided with hollow line holes which radiate and extend from the center to the periphery to be communicated with the hollow rings, the hollow mask plate is provided with a cross-shaped blocking area, the cross-shaped blocking area is used for dividing each hollow ring into four parts, and the total area of all the hollow rings accounts for 2% -20% of the area of the hollow mask plate, as shown in fig. 8.
The optimized hollowed mask plate structure is provided with a locally deposited tunneling passivation layer formed in a hollowed area or a hollowed ring, a grid line electrode is designed on the locally passivation layer, and the area of the hollowed area or the hollowed ring is limited, so that the light absorption of polysilicon is avoided, meanwhile, the metal contact recombination can be effectively reduced, the lower positive surface recombination current density is obtained, the open circuit voltage is obviously improved, the higher short circuit current is ensured, and the higher battery conversion efficiency is obtained.
Optionally, the sheet resistance formed by boron diffusion is 100 to 180 Ω.
Optionally, the sheet resistance formed by phosphorus diffusion is 20 to 40 Ω.
And the boron diffusion and the phosphorus diffusion are carried out in an ion implantation mode, and the sheet resistance is limited to form a boron doped polysilicon layer and a phosphorus doped polysilicon layer respectively, so that the battery conversion efficiency of the battery is improved.
Optionally, the annealing treatment is carried out at 800-950 ℃ for 20-40 min.
The preferable annealing temperature enables the silicon wafer to recover the regular arrangement of atoms on the silicon surface in the high temperature process, eliminates the lattice damage caused by ion implantation, and further improves the minority carrier lifetime.
Optionally, the sintering temperature is 700-950 ℃.
The ohmic contact of the printed grid line electrode is completed at the preferred sintering temperature, so that the normal use of the solar cell is ensured.
Optionally, the thickness of the silicon oxide layer is 1 nm-2 nm.
Optionally, the thickness of the polysilicon layer is 100 nm-200 nm.
The preferred thickness of the silicon oxide layer and the thickness of the polysilicon enable the tunneling passivation layer formed on the two sides of the silicon wafer to have excellent passivation and carrier collection capability, and the conversion efficiency of the battery is improved.
Optionally, the thickness of the alumina layer is 3 nm-8 nm.
And depositing an alumina layer with specific thickness on the front surface of the silicon wafer to form surface passivation, so as to improve the conversion efficiency of the battery.
Optionally, the anti-reflection film is silicon nitride.
Optionally, the thickness of the antireflection film is 50-90 nm.
Optionally, in the first step, KOH and H with the volume ratio of 0.8-1.5:8-10:80-120 are adopted 2 O 2 Carrying out surface treatment on the N-type silicon wafer by deionized water at 70-80 ℃, and then carrying out double-sided texturing on the N-type silicon wafer by KOH and deionized water with the volume ratio of 2-5:30-60; the concentration of KOH is 45-55wt%, and the concentration of H is 45-55wt% 2 O 2 The concentration of (2) is 28-33 wt%.
The preferred treatment mode is that firstly, surface treatment is carried out to remove the damage on the surface of the N-type silicon wafer, and then, the surface of the silicon wafer is textured to successfully prepare the pyramid structure.
Optionally, in the second step, HF and HNO with the volume ratio of 5-10:80-120 are adopted 3 The back surface polishing is carried out on the silicon wafer after the texturing, wherein the concentration of HF is 48wt%About 50wt%, of said HNO 3 The concentration of (2) is 60-67 wt%.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a double-sided topcon battery according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a hollowed mask plate provided in embodiment 1 of the present invention;
FIG. 3 is a schematic diagram of the pattern of the electrode gate line according to embodiment 1 of the present invention;
fig. 4 is a schematic structural diagram of a hollowed mask plate provided in embodiment 2 of the present invention;
fig. 5 is a schematic diagram of a pattern of an electrode gate line according to embodiment 2 of the present invention;
fig. 6 is a schematic structural diagram of a hollowed mask plate provided in embodiment 3 of the present invention;
fig. 7 is a schematic diagram of a pattern of an electrode gate line according to embodiment 3 of the present invention;
fig. 8 is a schematic structural diagram of a hollowed mask plate provided in embodiment 4 of the present invention;
fig. 9 is a schematic diagram of a pattern of an electrode gate line according to embodiment 4 of the present invention;
1. the barrier region, 2, the hollowed-out area, 3, the grid line electrode area, 4, the hollowed-out ring, 5, the hollowed-out line hole, 6, the N-type silicon wafer, 7, the silicon oxide layer, 8, the polysilicon layer, 9, the antireflection film, 10, the aluminum oxide layer, 11, the p+ emitter, 12 and the electrode.
Detailed Description
The present invention will be described in further detail with reference to the following examples in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Example 1
The embodiment of the invention provides a preparation method of a double-sided topcon battery, which comprises the following steps:
step one, KOH and H with the volume ratio of 1:9:100 are adopted 2 O 2 Carrying out surface treatment on the N-type silicon wafer by deionized water at the temperature of 75 ℃, removing damage on the surface of the N-type silicon wafer, and carrying out double-sided texturing by adopting KOH and deionized water in a volume ratio of 3:50; the KOH concentration was 50wt%, the H 2 O 2 The concentration of (2) is 30wt%;
step two, HF and HNO with the volume ratio of 8:100 are adopted 3 The back surface polishing is carried out on the silicon wafer after the texturing, wherein the concentration of HF is 49 weight percent, and HNO is adopted 3 The concentration of (2) is 65wt%;
step three, bonding a hollowed mask plate on the front surface of the polished silicon wafer, wherein the bonding agent is SK-807AB, and the coating amount is 0.08g/cm 2 The method comprises the steps of obtaining a pretreated silicon wafer, wherein the structure of a hollowed mask is shown in figure 2, a plurality of blocking areas with the same width are distributed on the surface of the hollowed mask at intervals up and down, hollowed areas are arranged between adjacent blocking areas, and the total area of all hollowed areas accounts for 5% of the area of the hollowed mask;
sequentially depositing a silicon oxide layer and a polysilicon layer on the front side and the back side of the pretreated silicon wafer respectively to form a first silicon wafer with a passivation structure on both sides, wherein the thickness of the oxide layer is 1.5nm, and the thickness of the polysilicon layer is 160nm;
step five, placing the first silicon wafer in an eluent with the temperature of 70 ℃ for soaking for 10min, and removing the hollow mask plate on the front surface to obtain a second silicon wafer, wherein the eluent is a mixed solution of lactic acid and water with the volume of 1:2;
step six, carrying out boron ion implantation diffusion on the front surface of the second silicon wafer, wherein the diffusion sheet resistance is 150Ω, and obtaining a third silicon wafer;
step seven, performing phosphorus ion implantation diffusion on the back surface of the third silicon wafer, wherein the back surface field sheet resistance is 30Ω, and obtaining a fourth silicon wafer;
step eight, annealing the fourth silicon wafer at 900 ℃ for 30min to obtain a fifth silicon wafer;
and step nine, depositing an alumina layer with the thickness of 5nm on the front surface of the fifth silicon wafer for surface passivation, then respectively depositing a silicon nitride antireflection film with the thickness of 90nm on the front surface and the back surface, printing a grid line electrode, and sintering at 900 ℃ to form an electrode grid line pattern schematic diagram shown in fig. 3, thus obtaining the double-sided topcon battery.
The schematic structure of the double-sided topcon battery is shown in fig. 1.
Example 2
The embodiment of the invention provides a preparation method of a double-sided topcon battery, which comprises the following steps:
step one, KOH and H with the volume ratio of 0.8:10:120 are adopted 2 O 2 Surface treatment is carried out on the N-type silicon wafer by deionized water at the temperature of 70 ℃, damage on the surface of the N-type silicon wafer is removed, and then KOH and deionized water with the volume ratio of 2:60 are adopted for double-sided texturing; the KOH concentration was 55wt%, the H 2 O 2 The concentration of (2) is 28wt%;
step two, HF and HNO with the volume ratio of 5:120 are adopted 3 The back surface polishing is carried out on the silicon wafer after the texturing, wherein the concentration of HF is 48 weight percent, and HNO is adopted 3 The concentration of (2) is 60wt%;
step three, bonding a hollowed mask plate on the front surface of the polished silicon wafer, wherein the bonding agent is SK-807AB, and the coating amount is 0.09g/cm 2 The method comprises the steps of obtaining a pretreated silicon wafer, wherein the structure of a hollowed mask is shown in fig. 4, 3 grid line modules distributed in an array are arranged on the hollowed mask, each grid line module comprises a plurality of blocking areas with the same width, hollowed-out areas positioned between the adjacent blocking areas and hollowed-out main lines penetrating through all the hollowed-out areas, and each blocking area is distributed at intervals up and down, wherein the total area of all the hollowed-out areas accounts for 10% of the area of the hollowed mask;
sequentially depositing a silicon oxide layer and a polysilicon layer on the front side and the back side of the pretreated silicon wafer respectively to form a first silicon wafer with a passivation structure on both sides, wherein the thickness of the oxide layer is 1nm, and the thickness of the polysilicon layer is 200nm;
step five, placing the first silicon wafer in an eluent with the temperature of 60 ℃ for soaking for 12min, and removing the hollow mask plate on the front surface to obtain a second silicon wafer, wherein the eluent is a mixed solution of lactic acid and water with the volume of 1.5:1;
step six, carrying out boron ion implantation diffusion on the front surface of the second silicon wafer, wherein the diffusion sheet resistance is 100 omega, and obtaining a third silicon wafer;
step seven, performing phosphorus ion implantation diffusion on the back surface of the third silicon wafer, wherein the back surface field sheet resistance is 40 omega, and obtaining a fourth silicon wafer;
step eight, annealing the fourth silicon wafer at 800 ℃ for 40min to obtain a fifth silicon wafer;
and step nine, depositing an aluminum oxide layer with the thickness of 3nm on the front surface of the fifth silicon wafer for surface passivation, then respectively depositing silicon nitride antireflection films with the thickness of 50nm on the front surface and the back surface, printing a grid line electrode, and sintering at 700 ℃ to form an electrode grid line pattern schematic diagram shown in fig. 5, thus obtaining the double-sided topcon battery.
The schematic structure of the double-sided topcon battery is shown in fig. 1.
Example 3
The embodiment of the invention provides a preparation method of a double-sided topcon battery, which comprises the following steps:
step one, KOH and H with the volume ratio of 1.5:8:80 are adopted 2 O 2 Surface treatment is carried out on the N-type silicon wafer by deionized water at the temperature of 80 ℃, damage on the surface of the N-type silicon wafer is removed, and then double-sided texturing is carried out by adopting KOH and deionized water in a volume ratio of 5:30; the KOH concentration was 45wt%, the H 2 O 2 Is 33wt%;
step two, HF and HNO with the volume ratio of 10:80 are adopted 3 The back surface polishing is carried out on the silicon wafer after the texturing, wherein the concentration of HF is 50 weight percent, and HNO is adopted 3 The concentration of (2) was 67wt%;
step three, bonding a hollowed mask plate on the front surface of the polished silicon wafer, wherein the bonding agent is SK-807AB, and the coating amount is 0.07g/cm 2 The pretreated silicon wafer is obtained, the structure of the hollowed mask is shown in figure 6, and 9 grid lines distributed in an array are arranged on the hollowed maskEach grid line module comprises a plurality of blocking areas with the same width, hollow areas positioned between the adjacent blocking areas and a hollow main line penetrating through all the hollow areas, wherein the total area of all the hollow areas accounts for 2% of the area of the hollow mask plate;
sequentially depositing a silicon oxide layer and a polysilicon layer on the front side and the back side of the pretreated silicon wafer respectively to form a first silicon wafer with a passivation structure on both sides, wherein the thickness of the oxide layer is 2nm, and the thickness of the polysilicon layer is 150nm;
step five, placing the first silicon wafer in an eluent with the temperature of 80 ℃ for soaking for 8min, and removing the hollowed mask plate on the front surface to obtain a second silicon wafer, wherein the eluent is a mixed solution of lactic acid and water with the volume of 0.5:3;
step six, carrying out boron ion implantation diffusion on the front surface of the second silicon wafer, wherein the diffusion sheet resistance is 180Ω, and obtaining a third silicon wafer;
step seven, performing phosphorus ion implantation diffusion on the back surface of the third silicon wafer, wherein the back surface field sheet resistance is 20Ω, and obtaining a fourth silicon wafer;
step eight, annealing the fourth silicon wafer at 950 ℃ for 20min to obtain a fifth silicon wafer;
and step nine, depositing an aluminum oxide layer with the thickness of 8nm on the front surface of the fifth silicon wafer for surface passivation, then respectively depositing silicon nitride antireflection films with the thickness of 75nm on the front surface and the back surface, printing a grid line electrode, and sintering at 950 ℃ to form an electrode grid line pattern schematic diagram shown in fig. 7, thus obtaining the double-sided topcon battery.
The schematic structure of the double-sided topcon battery is shown in fig. 1.
Example 4
The embodiment of the invention provides a preparation method of a double-sided topcon battery, which comprises the following steps:
step one, KOH and H with the volume ratio of 1.2:9:105 are adopted 2 O 2 Surface treatment is carried out on the N-type silicon wafer by deionized water at the temperature of 75 ℃, damage on the surface of the N-type silicon wafer is removed, and then KOH and deionized water with the volume ratio of 3.5:40 are adopted for double-sided texturing;the KOH concentration was 50wt%, the H 2 O 2 The concentration of (2) is 30wt%;
step two, HF and HNO with the volume ratio of 8:110 are adopted 3 The back surface polishing is carried out on the silicon wafer after the texturing, wherein the concentration of HF is 49 weight percent, and HNO is adopted 3 The concentration of (2) is 65wt%;
step three, bonding a hollowed mask plate on the front surface of the polished silicon wafer, wherein the bonding agent is SK-807AB, and the coating amount is 0.08g/cm 2 The method comprises the steps of obtaining a pretreated silicon wafer, wherein the structure of a hollowed mask is shown in fig. 8, the hollowed mask is provided with a plurality of hollowed rings which are sequentially sleeved from the center to the periphery, and is also provided with hollowed line holes which extend from the center to the periphery in a radiation manner to be communicated with the hollowed rings, the hollowed mask is provided with a cross-shaped blocking area, the cross-shaped blocking area is used for dividing each hollowed ring into four parts, and the total area of all hollowed rings accounts for 20% of the area of the hollowed mask;
sequentially depositing a silicon oxide layer and a polysilicon layer on the front side and the back side of the pretreated silicon wafer respectively to form a first silicon wafer with a passivation structure on both sides, wherein the thickness of the oxide layer is 1.5nm, and the thickness of the polysilicon layer is 100nm;
step five, placing the first silicon wafer in an eluent with the temperature of 75 ℃ for soaking for 10min, and removing the hollowed mask plate on the front surface to obtain a second silicon wafer, wherein the eluent is a mixed solution of lactic acid and water with the volume of 1:2.5;
step six, carrying out boron ion implantation diffusion on the front surface of the second silicon wafer, wherein the diffusion sheet resistance is 120 omega, and obtaining a third silicon wafer;
step seven, performing phosphorus ion implantation diffusion on the back surface of the third silicon wafer, wherein the back surface field sheet resistance is 35 omega, and obtaining a fourth silicon wafer;
step eight, annealing the fourth silicon wafer for 30min at 890 ℃ to obtain a fifth silicon wafer;
and step nine, depositing an aluminum oxide layer with the thickness of 4nm on the front surface of the fifth silicon wafer for surface passivation, then respectively depositing silicon nitride antireflection films with the thickness of 65nm on the front surface and the back surface, printing a grid line electrode, and sintering at the temperature of 850 ℃, wherein the schematic diagram of the formed electrode grid line pattern is shown in fig. 9, and thus the double-sided topcon battery is obtained.
The schematic structure of the double-sided topcon battery is shown in fig. 1.
The double-sided topcon batteries in the above examples 1-4 basically did not generate fragments during the step five mask removal process, with a fragment rate of only 0.5%.
In order to better illustrate the technical solutions of the present invention, the following is further compared with examples of the present invention.
Comparative example 1
The comparative example provides a preparation method of a double-sided topcon battery, which comprises the following specific processes: and placing a hollowed mask plate on the front surface of the polished silicon wafer to obtain a pretreated silicon wafer, wherein the structure of the hollowed mask plate is consistent with that in the embodiment 3, and the rest steps are consistent with the embodiment 3, so that the details are not repeated.
To better illustrate the characteristics of the double-sided topcon batteries provided in the examples of the present invention, the batteries prepared in examples 1 to 4 and comparative example 1 were subjected to performance test, and the test results are shown in table 1.
TABLE 1
| Voc(V) | Isc(A) | FF(％) | Eff(％) | |
| Example 1 | 0.7012 | 10.237 | 83.33 | 23.736 |
| Example 2 | 0.6998 | 10.198 | 83.49 | 23.644 |
| Example 3 | 0.7015 | 10.282 | 83.4 | 23.871 |
| Example 4 | 0.7001 | 10.037 | 84.71 | 23.621 |
| Comparative example 1 | 0.6973 | 10.189 | 83.49 | 23.539 |
Wherein Voc is the open circuit voltage;
isc is short circuit current;
FF is the fill factor;
eff is the conversion efficiency.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, or alternatives falling within the spirit and principles of the invention.
Claims (9)
1. A preparation method of a double-sided topcon battery is characterized by comprising the following steps: the preparation method comprises the following steps:
step one, double-sided texturing is carried out on an N-type silicon wafer;
step two, polishing the back surface of the silicon wafer after texturing;
bonding a hollowed mask plate on the front surface of the polished silicon wafer to obtain a pretreated silicon wafer;
step four, respectively depositing a silicon oxide layer and a polysilicon layer on the front side and the back side of the pretreated silicon wafer in sequence to form a first silicon wafer with a passivation structure on both sides;
step five, removing the hollowed mask plate on the front surface of the first silicon wafer to obtain a second silicon wafer;
step six, performing boron diffusion on the front surface of the second silicon wafer to obtain a third silicon wafer;
step seven, performing phosphorus diffusion on the back surface of the third silicon wafer to obtain a fourth silicon wafer;
step eight, annealing the fourth silicon wafer to obtain a fifth silicon wafer;
step nine, depositing an alumina layer on the front surface of the fifth silicon wafer, then respectively depositing an antireflection film on the front surface and the back surface, printing a grid line electrode, and sintering to obtain the double-sided topcon battery;
the adhesive used for bonding comprises a component A and a component B in a mass ratio of 0.8-1.2:0.8-1.2, wherein the component A comprises the following components in parts by mass: 60-80 parts of epoxy resin, 10-30 parts of calcium hydroxide and 1-2 parts of titanium dioxide; the component B comprises the following components in parts by weight: 50 to 70 parts of curing agent, 10 to 30 parts of aluminum hydroxide, 5 to 10 parts of talcum powder and 0.5 to 1.5 parts of defoamer;
a plurality of blocking areas with the same width are distributed on the surface of the hollowed-out mask plate at intervals up and down, hollowed-out areas are arranged between adjacent blocking areas, and the total area of all the hollowed-out areas accounts for 2% -20% of the area of the hollowed-out mask plate.
2. The method for manufacturing a double-sided topcon battery of claim 1, wherein: the adhesive used for bonding has a coating amount of 0.07g/cm 2 ～0.09g/cm 2 。
3. The method for manufacturing a double-sided topcon battery of claim 1, wherein: and fifthly, placing the first silicon wafer in an eluent with the temperature of 60-80 ℃ for soaking for 8-12 min, and removing the hollowed mask plate on the front surface, wherein the eluent is a mixed solution of lactic acid and water with the volume of 0.5-1.5:1-3.
4. The method for manufacturing a double-sided topcon battery of claim 1, wherein: the novel mask plate is characterized in that n grid line modules distributed in an array are arranged on the hollow mask plate, each grid line module comprises a plurality of blocking areas with the same width, hollow areas located between the adjacent blocking areas and a hollow main line penetrating through all the hollow areas, wherein the n grid line modules are distributed in an up-down interval mode, n is 1-12, and the total area of the hollow areas arranged on the hollow mask plate accounts for 2% -20% of the area of the hollow mask plate.
5. The method for manufacturing a double-sided topcon battery of claim 1, wherein: the hollowed mask plate is provided with a plurality of hollowed rings which are sequentially distributed from the center to the periphery in a ring-sleeved mode, and is also provided with hollowed line holes which radiate and extend from the center to the periphery to be communicated with the hollowed rings, the hollowed mask plate is provided with a cross-shaped blocking area, the cross-shaped blocking area is used for dividing each hollowed ring into four parts, and the total area of all the hollowed rings accounts for 2% -20% of the area of the hollowed mask plate.
6. The method for manufacturing a double-sided topcon battery of claim 1, wherein: the square resistance formed by boron diffusion is 100-180Ω;
the sheet resistance formed by the phosphorus diffusion is 20 to 40 omega.
7. The method for manufacturing a double-sided topcon battery of claim 1, wherein: the temperature of the annealing treatment is 800-950 ℃ and the time is 20-40 min;
the sintering temperature is 700-950 ℃.
8. The method for manufacturing a double-sided topcon battery of claim 1, wherein: the thickness of the silicon oxide layer is 1 nm-2 nm;
the thickness of the polysilicon layer is 100 nm-200 nm;
the thickness of the alumina layer is 3 nm-8 nm;
the antireflection film is silicon nitride;
the thickness of the antireflection film is 50-90 nm.
9. The method for manufacturing a double-sided topcon battery of claim 1, wherein: in the first step, KOH and H with the volume ratio of 0.8-1.5:8-10:80-120 are adopted 2 O 2 Carrying out surface treatment on the N-type silicon wafer by deionized water at 70-80 ℃, and then carrying out double-sided texturing on the N-type silicon wafer by KOH and deionized water with the volume ratio of 2-5:30-60; the concentration of KOH is 45-55wt%, and the concentration of H is 45-55wt% 2 O 2 The concentration of (2) is 28-33 wt%;
in the second step, HF and HNO with the volume ratio of 5-10:80-120 are adopted 3 Polishing the back surface of the silicon wafer after texturing, wherein the concentration of HF is 48-50wt% and HNO is used for polishing the back surface of the silicon wafer after texturing 3 The concentration of (2) is 60-67 wt%.
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