CN115148852A - Preparation method of double-sided topcon battery - Google Patents

Preparation method of double-sided topcon battery Download PDF

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CN115148852A
CN115148852A CN202210778644.8A CN202210778644A CN115148852A CN 115148852 A CN115148852 A CN 115148852A CN 202210778644 A CN202210778644 A CN 202210778644A CN 115148852 A CN115148852 A CN 115148852A
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silicon wafer
double
hollowed
mask plate
sided
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CN115148852B (en
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王红芳
徐卓
潘明翠
郎芳
翟金叶
李锋
陈志军
闫小兵
史金超
于波
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Yingli Energy Development Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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    • H01—ELECTRIC ELEMENTS
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
    • H01L31/1868—Passivation
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Abstract

The invention relates to the technical field of solar cells, and particularly discloses a preparation method of a double-sided topcon cell. The preparation method comprises the following steps: carrying out double-sided texturing on the N-type silicon wafer; polishing the back of the silicon wafer after texturing; bonding a hollow mask plate on the front surface of the polished silicon wafer to obtain a pretreated silicon wafer; respectively forming first silicon wafers with passivation structures on two sides on the front and back sides of the pretreated silicon wafer; removing the hollow mask plate on the front surface of the first silicon wafer; performing boron diffusion on the front side of the silicon wafer; performing phosphorus diffusion on the back of the silicon wafer; annealing the silicon wafer; and depositing an aluminum oxide layer on the front surface of the silicon wafer, then respectively depositing an antireflection film on the front surface and the back surface, printing a grid line electrode, and sintering to obtain the double-sided topcon battery. This application adopts the bonding mode to laminate the fretwork mask plate in the silicon chip openly, can realize once only accomplishing the deposit of tunneling passivation layer at the silicon chip obverse and reverse side.

Description

Preparation method of double-sided topcon battery
Technical Field
The invention relates to the technical field of solar cells, in particular to a preparation method of a double-sided topcon cell.
Background
The Topcon battery is a tunneling oxide layer passivation contact battery, and the double-sided tunneling passivation layer is prepared on the front side and the back side of a silicon wafer. When the tunneling passivation layer is used for the back surface of the battery, excellent back surface passivation and carrier collection capacity can be provided, and the overall performance of the device is greatly improved. However, the polysilicon layer in the tunneling passivation layer has a severe parasitic absorption effect, and can absorb sunlight with a certain wavelength when being used on the front surface of a silicon wafer, so that short-circuit current is reduced. In order to avoid a higher parasitic absorption effect, a polysilicon passivation layer is usually prepared at the bottom of a grid line on the front surface of the battery to form a selective structure, so that passivation of a non-shielding region is not influenced. However, in the preparation process of the above structure, the tunnel passivation layer needs to be deposited twice, that is, the tunnel passivation layer on the front and back sides is completed in different steps, which not only causes the inevitable effect of the wraparound plating on the other side after the completion of the single side (that is, the tunnel passivation layer is formed around the edge on the periphery of the other side), and reduces the efficiency of the cell, but also requires the printing of the mask paste to realize the formation of the selective structure on the front side. Due to the phenomenon of plating, chemical cleaning is needed for removal so as to ensure the efficiency of the battery, and additional process steps are added. When a selective structure is formed on the front surface, a common method is to print mask slurry to form local protection and then perform a slurry removal process, so that the process steps are complicated, the yield of the battery is greatly reduced, the production cost is invisibly increased, and the battery piece is easily damaged due to the mask slurry printing and removal processes, and the difficulty in battery preparation is greatly increased. In addition, when diffusion is carried out in the existing preparation process, the diffusion is easy to cause, and the battery efficiency is influenced.
Disclosure of Invention
Aiming at the problems of complex steps, low yield and the like of the existing double-sided topcon battery preparation process, the invention provides a preparation method of a double-sided topcon battery.
In order to achieve the purpose of the invention, the embodiment of the invention adopts the following technical scheme:
a method for preparing a double-sided topcon battery, the method comprising the steps of:
firstly, carrying out double-sided texturing on an N-type silicon wafer;
step two, polishing the back of the silicon wafer after texturing;
bonding a hollow mask plate on the front surface of the polished silicon wafer to obtain a pretreated silicon wafer;
depositing a silicon oxide layer and a polycrystalline silicon layer on the front surface and the back surface of the pretreated silicon wafer respectively in sequence to form a first silicon wafer with passivation structures on two surfaces;
fifthly, removing the hollow mask plate on the front side of the first silicon wafer to obtain a second silicon wafer;
sixthly, performing boron diffusion on the front side of the second silicon wafer to obtain a third silicon wafer;
seventhly, performing phosphorus diffusion on the back of the third silicon wafer to obtain a fourth silicon wafer;
step eight, annealing the fourth silicon wafer to obtain a fifth silicon wafer;
and step nine, depositing an aluminum oxide layer on the front surface of the fifth silicon wafer, then respectively depositing an antireflection film on the front surface and the back surface, then printing a grid line electrode, and sintering to obtain the double-sided topcon battery.
Compared with the prior art, the preparation method of the double-sided topcon battery has the following advantages:
the method has the advantages that the hollowed-out mask plate is attached to the front side of the silicon wafer in a bonding mode, so that the deposition of the tunneling passivation layer on the front side and the back side of the silicon wafer can be completed at one time, the preparation flow is greatly simplified, too many process flows are avoided, and the production cost is remarkably reduced; meanwhile, the influence on the efficiency of the battery is reduced and the yield of the battery is improved due to the simplification of the process.
This application adopts the mode of fretwork mask plate can also match subsequent printing metal electrode, forms local tunnel layer sedimentary region in the fretwork district of fretwork mask plate and forms selective passivation structure promptly to correspond printing grid line electrode on this selective passivation structure, can also realize grid line electrode region heavy doping, improve the efficiency of battery.
Optionally, the adhesive used for adhesion comprises a component A and a component B, wherein the mass ratio of the component A to the component B is 0.8-1.2, and the component A comprises the following components in parts by mass: 60 to 80 parts of epoxy resin, 10 to 30 parts of calcium hydroxide and 1 to 2 parts of titanium dioxide; the component B comprises the following components in parts by mass: 50 to 70 parts of curing agent, 10 to 30 parts of aluminum hydroxide, 5 to 10 parts of talcum powder and 0.5 to 1.5 parts of defoaming agent.
More preferably, the adhesive is available from Guangzhou Bisco New Material Co., ltd, model SK-807AB.
Optionally, the coating amount of the adhesive used for bonding is 0.07g/cm 2 ～0.09g/cm 2 。
Optionally, in the fifth step, the first silicon wafer is placed in an eluent with the temperature of 60-80 ℃ for soaking for 8-12 min, and the front-side hollow mask plate is removed, wherein the eluent is a mixed solution of lactic acid and water with the volume of 0.5-1.5.
The applicant finds that the hollowed mask plate is directly placed on the surface of the silicon wafer, and the tunneling passivation layer is prepared under the atmosphere condition of the tube furnace, so that gas inevitably enters gaps where the hollowed mask plate is in contact with the silicon wafer to react, the hollowed mask plate cannot protect the silicon wafer coverage area to form local deposition of the silicon wafer, and a certain tunneling passivation layer can still be deposited in the shielding area. The applicant also finds that if the silicon wafer is bonded on the hollowed-out mask plate, because the silicon wafer is thin (the thickness is 150-180 mu m), fragments are easily generated during bonding and separation, and the fragment rate is as high as about 10% -20%, so that the silicon wafer and the hollowed-out mask plate are bonded by the high-temperature-resistant epoxy resin adhesive which is easy to remove, gaps between the silicon wafer and the hollowed-out mask plate are removed, the deposition of a tunneling passivation layer at the joint of the silicon wafer and the hollowed-out mask plate is avoided, and meanwhile, a simpler and more convenient preparation flow of the double-sided topcon is realized.
The preferred coating amount can enable the hollow mask plate to be tightly bonded on the surface of the silicon wafer, and then the silicon wafer is soaked in a lactic acid water mixed solution at the temperature of 60-80 ℃, so that the mask plate is separated from the silicon wafer, and the fragment rate of the silicon wafer is remarkably reduced.
Optionally, a plurality of blocking areas with the same width are distributed on the surface of the hollowed-out mask plate at intervals up and down, hollowed-out areas are arranged between every two adjacent blocking areas, and the total area of all the hollowed-out areas accounts for 2% -20% of the area of the hollowed-out mask plate, as shown in fig. 2.
Optionally, n gate line modules distributed in an array are arranged on the hollowed-out mask plate, each gate line module includes a plurality of blocking areas with the same width, hollowed-out areas located between the adjacent blocking areas, and hollowed-out main lines penetrating through all the hollowed-out areas, and n is 1 to 12, where the total area of the hollowed-out areas on the hollowed-out mask plate accounts for 2 to 20% of the area of the hollowed-out mask plate, as shown in fig. 4 or fig. 6.
Optionally, the hollowed-out mask is provided with a plurality of hollowed-out rings which are sequentially sleeved from the center to the periphery, and further provided with hollowed-out wire holes which extend from the center to the periphery in a radiation manner to communicate with the hollowed-out rings, the hollowed-out mask is provided with a cross-shaped blocking area, the cross-shaped blocking area is used for dividing the hollowed-out rings into four parts, and the total area of all the hollowed-out rings accounts for 2% -20% of the area of the hollowed-out mask, as shown in fig. 8.
According to the optimized hollow mask structure, a local deposition tunneling passivation layer is formed in a hollow-out area or a hollow-out ring, a grid line electrode is designed on the local passivation layer, and by limiting the area of the hollow-out area or the hollow-out ring, light absorption of polycrystalline silicon is avoided, and metal contact recombination can be effectively reduced, so that lower front surface recombination current density is obtained, open-circuit voltage is remarkably improved, higher short-circuit current is guaranteed, and higher battery conversion efficiency is obtained.
Optionally, the sheet resistance formed by boron diffusion is 100 Ω to 180 Ω.
Optionally, the sheet resistance formed by the phosphorus diffusion is 20 Ω to 40 Ω.
The method adopts an ion implantation mode to carry out boron diffusion and phosphorus diffusion, and forms a boron-doped polycrystalline silicon layer and a phosphorus-doped polycrystalline silicon layer respectively by limiting the sheet resistance of the boron-doped polycrystalline silicon layer and the phosphorus-doped polycrystalline silicon layer, thereby being more beneficial to improving the battery conversion efficiency of the battery.
Optionally, the temperature of the annealing treatment is 800-950 ℃, and the time is 20-40 min.
The preferred annealing temperature ensures that the silicon wafer recovers the regular arrangement of silicon surface atoms in the high-temperature process, eliminates the lattice damage caused by ion implantation, and further improves the minority carrier lifetime.
Optionally, the sintering temperature is 700 ℃ to 950 ℃.
And the ohmic contact of the printed grid line electrode is completed at the optimal sintering temperature, so that the normal use of the solar cell is ensured.
Optionally, the thickness of the silicon oxide layer is 1nm to 2nm.
Optionally, the thickness of the polysilicon layer is 100nm to 200nm.
Due to the preferable thickness of the silicon oxide layer and the polysilicon layer, the tunneling passivation layer formed on the two sides of the silicon wafer has excellent passivation and carrier collection capability, and the conversion efficiency of the cell is improved.
Optionally, the thickness of the aluminum oxide layer is 3nm to 8nm.
And depositing an aluminum oxide layer with a specific thickness on the front surface of the silicon wafer to form surface passivation, thereby improving the conversion efficiency of the cell.
Optionally, the antireflection film is silicon nitride.
Optionally, the thickness of the antireflection film is 50-90 nm.
Optionally, in the first step, KOH and H with a volume ratio of 0.8-1.5 2 O 2 And deionized water are used for carrying out surface treatment on the N-type silicon wafer at the temperature of 70-80 ℃, and then KOH and the deionized water with the volume ratio of 2-5; the concentration of the KOH is 45wt% -55 wt%, and the H is 2 O 2 The concentration of (A) is 28wt% -33 wt%.
The preferable processing mode is that firstly, the damage on the surface of the N-type silicon wafer is removed by surface treatment, then, the two sides of the silicon wafer are subjected to texturing, and the pyramid structure is successfully prepared.
Optionally, in the second step, HF and HNO with the volume ratio of 5-10 3 Back polishing the silicon wafer after texturing, wherein the concentration of HF is 48wt% -50 wt%, and HNO is added 3 The concentration of (A) is 60wt% -67 wt%.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a double-sided topcon cell provided by an embodiment of the invention;
fig. 2 is a schematic structural diagram of a hollow mask provided in embodiment 1 of the present invention;
fig. 3 is a pattern diagram of an electrode grid line provided in embodiment 1 of the present invention;
fig. 4 is a schematic structural view of a hollow mask provided in embodiment 2 of the present invention;
fig. 5 is a schematic diagram of a pattern of an electrode gate line provided in embodiment 2 of the present invention;
fig. 6 is a schematic structural view of a hollow mask provided in embodiment 3 of the present invention;
fig. 7 is a schematic diagram of a pattern of an electrode gate line provided in embodiment 3 of the present invention;
fig. 8 is a schematic structural view of a hollow mask provided in embodiment 4 of the present invention;
fig. 9 is a schematic diagram of a pattern of an electrode gate line provided in embodiment 4 of the present invention;
1. the solar cell comprises a blocking area, 2, a hollowed-out area, 3, a grid line electrode area, 4, a hollowed-out ring, 5, a hollowed-out line hole, 6, an N-type silicon wafer, 7, a silicon oxide layer, 8, a polycrystalline silicon layer, 9, an antireflection film, 10, an aluminum oxide layer, 11, a p + emitter, 12 and an electrode.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the invention.
Example 1
The embodiment of the invention provides a preparation method of a double-sided topcon battery, which comprises the following steps:
step one, adopting KOH and H with the volume ratio of 1 2 O 2 Carrying out surface treatment on the N-type silicon wafer by using deionized water at 75 ℃, removing the damage on the surface of the N-type silicon wafer, and then carrying out double-sided texturing by using KOH and the deionized water with the volume ratio of 3; the concentration of KOH is 50wt%, H 2 O 2 Is 30wt%;
step two, adopting HF and HNO with the volume ratio of 8 3 Back polishing the textured silicon wafer, wherein the concentration of HF is 49wt%, and HNO is added 3 Has a concentration of 65wt%;
thirdly, bonding a hollow mask plate on the front surface of the polished silicon wafer, wherein the bonding agent is SK-807AB, and the coating amount is 0.08g/cm 2 Obtaining a pretreated silicon wafer, wherein the structure of the hollow mask plate is shown in fig. 2, a plurality of blocking areas with consistent width are distributed on the surface of the hollow mask plate at intervals from top to bottom, hollow areas are formed between every two adjacent blocking areas, and the total area of all the hollow areas accounts for 5% of the area of the hollow mask plate;
depositing a silicon oxide layer and a polysilicon layer on the front surface and the back surface of the pretreated silicon wafer respectively in sequence to form a first silicon wafer with a passivation structure on two surfaces, wherein the thickness of the oxide layer is 1.5nm, and the thickness of the polysilicon layer is 160nm;
step five, soaking the first silicon wafer in an eluant with the temperature of 70 ℃ for 10min, and removing the front hollow mask plate to obtain a second silicon wafer, wherein the eluant is a mixed solution of lactic acid and water with the volume of 1:2;
sixthly, performing boron ion implantation diffusion on the front side of the second silicon wafer, wherein the diffusion sheet resistance is 150 omega, and obtaining a third silicon wafer;
seventhly, implanting and diffusing phosphorus ions into the back surface of the third silicon wafer, wherein the square resistance of a back surface field is 30 omega, and obtaining a fourth silicon wafer;
step eight, annealing the fourth silicon wafer at 900 ℃ for 30min to obtain a fifth silicon wafer;
and ninthly, depositing an aluminum oxide layer with the thickness of 5nm on the front surface of the fifth silicon wafer for surface passivation, then respectively depositing silicon nitride antireflection films with the thicknesses of 90nm on the front surface and the back surface, then printing grid line electrodes, sintering at 900 ℃, and obtaining the double-sided topcon battery, wherein the schematic diagram of the formed electrode grid line patterns is shown in figure 3.
The structure of the double-sided topcon battery is schematically shown in fig. 1.
Example 2
The embodiment of the invention provides a preparation method of a double-sided topcon battery, which comprises the following steps:
step one, adopting KOH and H with the volume ratio of 0.8 2 O 2 Carrying out surface treatment on the N-type silicon wafer by using deionized water at 70 ℃, removing the damage on the surface of the N-type silicon wafer, and then carrying out double-sided texturing by using KOH and the deionized water with the volume ratio of 2; the concentration of KOH is 55wt%, the H 2 O 2 Is 28wt%;
step two, adopting HF and HNO with the volume ratio of 5 3 Back polishing the textured silicon wafer, wherein the concentration of HF is 48wt%, and HNO is added 3 Is 60wt%;
thirdly, bonding a hollow mask plate on the front surface of the polished silicon wafer, wherein the bonding agent is SK-807AB, and the coating amount is 0.09g/cm 2 Obtaining a preprocessed silicon wafer, wherein the structure of the hollowed mask plate is shown in fig. 4, the hollowed mask plate is provided with 3 grid line modules distributed in an array manner, each grid line module comprises a plurality of blocking areas with consistent width, hollowed-out areas positioned between every two adjacent blocking areas and hollowed-out main lines penetrating through all the hollowed-out areas, and the total area of all the hollowed-out areas accounts for 10% of the area of the hollowed-out mask plate;
depositing a silicon oxide layer and a polycrystalline silicon layer on the front side and the back side of the pretreated silicon wafer respectively in sequence to form a first silicon wafer with a passivation structure on two sides, wherein the thickness of the oxide layer is 1nm, and the thickness of the polycrystalline silicon layer is 200nm;
step five, placing the first silicon wafer in an eluant with the temperature of 60 ℃ for soaking for 12min, and removing the front hollow mask plate to obtain a second silicon wafer, wherein the eluant is a mixed solution of lactic acid and water with the volume of 1.5;
sixthly, performing boron ion implantation diffusion on the front side of the second silicon wafer, wherein the diffusion sheet resistance is 100 omega, and obtaining a third silicon wafer;
seventhly, implanting and diffusing phosphorus ions into the back surface of the third silicon wafer, wherein the square resistance of a back surface field is 40 ohms, and obtaining a fourth silicon wafer;
step eight, annealing the fourth silicon wafer at 800 ℃ for 40min to obtain a fifth silicon wafer;
and ninthly, depositing an aluminum oxide layer with the thickness of 3nm on the front surface of the fifth silicon wafer for surface passivation, then respectively depositing silicon nitride antireflection films with the thicknesses of 50nm on the front surface and the back surface, printing grid line electrodes, and sintering at 700 ℃, wherein the schematic diagram of the formed electrode grid line patterns is shown in fig. 5, so that the double-sided topcon battery is obtained.
The structure of the double-sided topcon battery is schematically shown in fig. 1.
Example 3
The embodiment of the invention provides a preparation method of a double-sided topcon battery, which comprises the following steps:
step one, adopting KOH and H with the volume ratio of 1.5 2 O 2 Carrying out surface treatment on the N-type silicon wafer by using deionized water at the temperature of 80 ℃, removing the damage on the surface of the N-type silicon wafer, and carrying out double-sided texturing by using KOH and the deionized water in a volume ratio of 5; the concentration of KOH is 45wt%, and H 2 O 2 Is 33wt%;
step two, adopting HF and HNO with the volume ratio of 10 3 Back polishing the textured silicon wafer, wherein the concentration of HF is 50wt%, and HNO is added 3 At a concentration of 67wt%;
thirdly, bonding a hollow mask plate on the front surface of the polished silicon wafer, wherein the bonding agent SK-807AB coating amount is 0.07g/cm 2 Obtaining a preprocessed silicon wafer, wherein the structure of the hollowed mask plate is shown in fig. 6, the hollowed mask plate is provided with 9 grid line modules distributed in an array manner, each grid line module comprises a plurality of blocking areas with consistent width, hollowed-out areas positioned between every two adjacent blocking areas and hollowed-out main lines penetrating through all the hollowed-out areas, and the total area of all the hollowed-out areas accounts for 2% of the area of the hollowed-out mask plate;
depositing a silicon oxide layer and a polysilicon layer on the front side and the back side of the pretreated silicon wafer respectively in sequence to form a first silicon wafer with passivation structures on two sides, wherein the thickness of the oxide layer is 2nm, and the thickness of the polysilicon layer is 150nm;
step five, soaking the first silicon wafer in an eluant with the temperature of 80 ℃ for 8min, and removing the front hollowed mask plate to obtain a second silicon wafer, wherein the eluant is a mixed solution of lactic acid and water with the volume of 0.5;
sixthly, performing boron ion implantation diffusion on the front side of the second silicon wafer, wherein the diffusion sheet resistance is 180 omega, and obtaining a third silicon wafer;
seventhly, implanting and diffusing phosphorus ions into the back surface of the third silicon wafer, wherein the square resistance of a back surface field is 20 omega, and obtaining a fourth silicon wafer;
step eight, annealing the fourth silicon wafer at 950 ℃ for 20min to obtain a fifth silicon wafer;
and ninthly, depositing an aluminum oxide layer with the thickness of 8nm on the front surface of the fifth silicon wafer for surface passivation, then respectively depositing silicon nitride antireflection films with the thicknesses of 75nm on the front surface and the back surface, printing a grid line electrode, and sintering at 950 ℃, wherein the schematic diagram of the formed electrode grid line pattern is shown in fig. 7, so as to obtain the double-sided topcon battery.
The schematic structure of the double-sided topcon cell is shown in fig. 1.
Example 4
The embodiment of the invention provides a preparation method of a double-sided topcon battery, which comprises the following steps:
step one, adopting KOH and H with the volume ratio of 1.2 2 O 2 Carrying out surface treatment on the N-type silicon wafer by using deionized water at 75 ℃ to remove damage on the surface of the N-type silicon wafer, and then carrying out double-sided texturing by using KOH and the deionized water in a volume ratio of 3.5; the concentration of KOH is 50wt%, H 2 O 2 Is 30wt%;
step two, adopting HF and HNO with the volume ratio of 8 3 Back polishing the textured silicon wafer, wherein the concentration of HF is 49wt%, and HNO is added 3 Has a concentration of 65wt%;
bonding a hollow mask plate on the front surface of the polished silicon wafer, wherein the bonding agent is SK-807AB, and the coating amount is 0.08g/cm 2 Obtaining a pretreated silicon wafer, wherein the structure of the hollowed-out mask plate is shown in fig. 8, the hollowed-out mask plate is provided with a plurality of hollowed-out rings which are sequentially arranged from the center to the periphery in a ring sleeving manner, and hollowed-out line holes which are extended from the center to the periphery in a radiation manner so as to communicate with the hollowed-out rings, the hollowed-out mask plate is provided with a cross-shaped blocking area, the cross-shaped blocking area is used for cutting the hollowed-out rings into four parts, and the total area of all the hollowed-out rings accounts for 20% of the area of the hollowed-out mask plate;
depositing a silicon oxide layer and a polysilicon layer on the front surface and the back surface of the pretreated silicon wafer respectively in sequence to form a first silicon wafer with a passivation structure on two surfaces, wherein the thickness of the oxide layer is 1.5nm, and the thickness of the polysilicon layer is 100nm;
step five, soaking the first silicon wafer in eluent at the temperature of 75 ℃ for 10min, and removing the front hollowed mask plate to obtain a second silicon wafer, wherein the eluent is a mixed solution of lactic acid and water with the volume of 1;
sixthly, performing boron ion implantation diffusion on the front surface of the second silicon wafer, wherein the diffusion sheet resistance is 120 omega, and obtaining a third silicon wafer;
seventhly, injecting and diffusing phosphorus ions into the back surface of the third silicon wafer, wherein the square resistance of a back surface field is 35 omega, and obtaining a fourth silicon wafer;
step eight, annealing the fourth silicon wafer at 890 ℃ for 30min to obtain a fifth silicon wafer;
and ninthly, depositing an aluminum oxide layer with the thickness of 4nm on the front surface of the fifth silicon wafer for surface passivation, then respectively depositing silicon nitride antireflection films with the thicknesses of 65nm on the front surface and the back surface, then printing grid line electrodes, sintering at 850 ℃, and obtaining the double-sided topcon battery, wherein the schematic diagram of the formed electrode grid line patterns is shown in fig. 9.
The structure of the double-sided topcon battery is schematically shown in fig. 1.
In the above embodiments 1 to 4, the double-sided topcon battery does not generate fragments substantially in the process of removing the mask plate in the step five, and the fragment rate is only 0.5%.
In order to better illustrate the technical solution of the present invention, further comparison is made below by comparing examples of the present invention with comparative examples.
Comparative example 1
The comparative example provides a preparation method of a double-sided topcon battery, and the specific process of the third step is as follows: and placing a hollow mask plate on the front surface of the polished silicon wafer to obtain a pretreated silicon wafer, wherein the structure of the hollow mask plate is consistent with that in embodiment 3, and the rest steps are consistent with that in embodiment 3 and are not repeated.
To better illustrate the characteristics of the double-sided topcon cells provided in the examples of the present invention, the cells prepared in examples 1 to 4 and comparative example 1 were tested for their performance, and the results are shown in table 1.
TABLE 1
Voc(V) Isc(A) FF(％) Eff(％)
Example 1 0.7012 10.237 83.33 23.736
Example 2 0.6998 10.198 83.49 23.644
Example 3 0.7015 10.282 83.4 23.871
Example 4 0.7001 10.037 84.71 23.621
Comparative example 1 0.6973 10.189 83.49 23.539
Wherein Voc is an open circuit voltage;
isc is short-circuit current;
FF is a fill factor;
eff is the conversion efficiency.
The above description is intended to be illustrative of the preferred embodiment of the present invention and should not be taken as limiting the invention, but rather, the invention is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

Claims (10)

1. A preparation method of a double-sided topcon battery is characterized by comprising the following steps: the preparation method comprises the following steps:
firstly, carrying out double-sided texturing on an N-type silicon wafer;
step two, polishing the back of the silicon wafer after texturing;
bonding a hollow mask plate on the front surface of the polished silicon wafer to obtain a pretreated silicon wafer;
depositing a silicon oxide layer and a polycrystalline silicon layer on the front surface and the back surface of the pretreated silicon wafer respectively in sequence to form a first silicon wafer with passivation structures on two surfaces;
fifthly, removing the hollow mask plate on the front side of the first silicon wafer to obtain a second silicon wafer;
sixthly, performing boron diffusion on the front side of the second silicon wafer to obtain a third silicon wafer;
seventhly, performing phosphorus diffusion on the back of the third silicon wafer to obtain a fourth silicon wafer;
step eight, annealing the fourth silicon wafer to obtain a fifth silicon wafer;
and step nine, depositing an aluminum oxide layer on the front surface of the fifth silicon wafer, then respectively depositing an antireflection film on the front surface and the back surface, then printing a grid line electrode, and sintering to obtain the double-sided topcon battery.
2. A method of making a double-sided topcon cell of claim 1, wherein: the adhesive used for adhesion comprises a component A and a component B, wherein the mass ratio of the component A to the component B is 0.8-1.2, and the component A comprises the following components in parts by mass: 60 to 80 parts of epoxy resin, 10 to 30 parts of calcium hydroxide and 1 to 2 parts of titanium dioxide; the component B comprises the following components in parts by mass: 50 to 70 parts of curing agent, 10 to 30 parts of aluminum hydroxide, 5 to 10 parts of talcum powder and 0.5 to 1.5 parts of defoaming agent; and/or
The coating amount of the adhesive used for bonding is 0.07g/cm 2 ～0.09g/cm 2 。
3. A method of making a double-sided topcon cell of claim 1, wherein: and step five, soaking the first silicon wafer in an eluant at the temperature of 60-80 ℃ for 8-12 min to remove the front hollowed mask plate, wherein the eluant is a mixed solution of lactic acid and water with the volume of 0.5-1.5.
4. A method of making a double-sided topcon cell of claim 1, wherein: a plurality of blocking areas with the same width are distributed on the surface of the hollowed-out mask plate at intervals up and down, hollowed-out areas are arranged between every two adjacent blocking areas, and the total area of all the hollowed-out areas accounts for 2% -20% of the area of the hollowed-out mask plate.
5. The method of making a double-sided topcon battery of claim 1, wherein: the mask plate is characterized in that n grid line modules distributed in an array mode are arranged on the hollowed mask plate, each grid line module comprises a plurality of blocking areas with the same width, hollowed-out areas located between every two adjacent blocking areas and hollowed-out main lines penetrating through all the hollowed-out areas, and n is 1-12%, wherein the total area of the hollowed-out areas on the hollowed-out mask plate accounts for 2% -20% of the area of the hollowed-out mask plate.
6. A method of making a double-sided topcon cell of claim 1, wherein: the hollow mask plate is provided with a plurality of hollow rings which are sequentially sleeved from the center to the periphery, and hollow wire holes which are extended from the center to the periphery in a radiation mode to communicate with the hollow rings, a cross-shaped blocking area is arranged on the hollow mask plate and used for dividing the hollow rings into four parts, and the total area of all the hollow rings accounts for 2% -20% of the area of the hollow mask plate.
7. A method of making a double-sided topcon cell of claim 1, wherein: the sheet resistance formed by boron diffusion is 100-180 omega; and/or
The sheet resistance formed by the phosphorus diffusion is 20-40 omega.
8. The method of making a double-sided topcon battery of claim 1, wherein: the temperature of the annealing treatment is 800-950 ℃, and the time is 20-40 min; and/or
The sintering temperature is 700-950 ℃.
9. The method of making a double-sided topcon battery of claim 1, wherein: the thickness of the silicon oxide layer is 1 nm-2 nm; and/or
The thickness of the polycrystalline silicon layer is 100 nm-200 nm; and/or
The thickness of the aluminum oxide layer is 3 nm-8 nm; and/or
The antireflection film is silicon nitride; and/or
The thickness of the antireflection film is 50-90 nm.
10. A method of making a double-sided topcon cell of claim 1, wherein: in the first step, KOH and H with the volume ratio of 0.8-1.5 2 O 2 And toCarrying out surface treatment on an N-type silicon wafer by using ionized water at the temperature of 70-80 ℃, and carrying out double-sided texturing on the N-type silicon wafer by using KOH and deionized water in a volume ratio of 2-5; the concentration of the KOH is 45wt% -55 wt%, and the H is 2 O 2 The concentration of (A) is 28wt% -33 wt%; and/or
In the second step, HF and HNO with the volume ratio of 5-10 3 Back polishing the silicon wafer after texturing, wherein the concentration of HF is 48wt% -50 wt%, and HNO is added 3 The concentration of (A) is 60wt% -67 wt%.
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