CN115037331A - Asynchronous burst signal timing synchronization method based on reverse extrapolation - Google Patents
Asynchronous burst signal timing synchronization method based on reverse extrapolation Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/7073—Synchronisation aspects
- H04B1/7075—Synchronisation aspects with code phase acquisition
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/7073—Synchronisation aspects
- H04B1/7085—Synchronisation aspects using a code tracking loop, e.g. a delay-locked loop
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/7073—Synchronisation aspects
- H04B1/7087—Carrier synchronisation aspects
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Abstract
The invention discloses an asynchronous burst signal timing synchronization method based on reverse extrapolation, which utilizes the measurement result of the locking time of the traditional code ring to extrapolate the initial phase and code Doppler of the code on the reverse time axis, simultaneously carries out reverse order arrangement on the stored received data from the locking time of the traditional code ring, and sends the data into another code ring together with the extrapolated initial phase and code Doppler results, quickly aligns the local code on the reverse time axis, and starts demodulation after the demodulation condition is reached. The invention utilizes the received data reverse order and reverse time axis information to extrapolate, solves the problems that the traditional code ring is limited by loop convergence time, cannot synchronously align the data before convergence and cannot synchronize short-time signals, realizes the reduction of the length of the transmitted data under the condition that the burst/burst communication system transmits the same effective information, enhances the interception resistance of the system, and can process the influence of code Doppler introduced by the high dynamic of the transmitting/receiving end on the reverse code ring.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a method, an apparatus, a device, and a storage medium for timing synchronization of asynchronous burst signals based on reverse extrapolation.
Background
In spread spectrum communication, data demodulation relies on the process of signal acquisition and tracking, which is a two-dimensional replication process of spreading codes and carrier signals. For the reproduction of the spread spectrum code, the receiver uses the sharp autocorrelation characteristic of the pseudo-random code to perform the correlation operation on the received signal and the pseudo-random code generated locally to form an acquisition result, but when the period of the pseudo-code is longer, a large amount of delay and addition operations are needed, the resource consumption is large, generally, the acquisition success is indicated as long as the phase difference between the received pseudo-code sequence and the local pseudo-code is controlled within 0.5 chip in the acquisition process, and the receiver sends the acquisition result into a code ring to perform the fine synchronization of the chip phase. The code loop also utilizes sharp autocorrelation characteristics of pseudo-random codes to construct a phase discrimination curve of a chip phase, and accurate alignment of the local code phase and the code phase of a received signal is realized through a negative feedback loop.
Under the continuous wave spread spectrum communication system, the data length is long enough, the useful information bearing can fall on the data bit after the synchronization is completed, and under the assistance of the carrier ring, the code ring can adapt to the high dynamic state of the transmitter/receiver under the condition of a lower order number.
Under the spread spectrum burst communication system, the signal duration is short, and the starting point and the starting position of the signal are uncertain. The traditional solution is to embed partial pilot data in front of the useful information position as a data segment captured and precisely synchronized by a receiving end. The method can compress the proportion of effective information in the transmitted signal, so that the transmission efficiency of a communication link is reduced, and the probability of interception of the signal by an undesired party is increased under the condition of needing concealed communication.
A new solution is to store all received signals under the condition that a transmitting end has no pilot data, send the signals into a code synchronization ring after carrying out forward and reverse sequence preprocessing, carry out code synchronization by utilizing a pre-stored pseudo code lookup table and recover all received data information. The method solves the problem of phase jump in the signal splicing process, but cannot adapt to the code Doppler problem caused by high dynamic of a transmitter/receiver, and has a limited application range.
The above is only for the purpose of assisting understanding of the technical solution of the present invention, and does not represent an admission that the above is the prior art.
Disclosure of Invention
The invention mainly aims to provide a method, a device, equipment and a storage medium for timing synchronization of asynchronous burst signals based on reverse extrapolation, and aims to solve the technical problems that the existing short-time burst spread spectrum signal code synchronization method is large in calculation amount or is not suitable for a scene with larger code Doppler frequency offset.
In order to achieve the above object, the present invention provides an asynchronous burst signal timing synchronization method based on reverse extrapolation, the method comprising the following steps:
after the received signal is captured, carrying out carrier synchronization on the received signal, and stripping the carrier of the received signal according to the carrier synchronization result to obtain stripped data;
loop tracking is carried out on the stripped data until loop locking or data ending, and the loop locking time or the data ending time is recorded as T time;
carrying out reverse sequence arrangement on the stripped data from the last sampling point to the first sampling point in the T-time integration period to obtain reverse sequence data;
determining an initial phase value of the reverse order data based on an accumulated phase value during loop locking, and updating an initial code frequency value according to the initial phase value;
and performing loop iteration on the reverse-order data by using the initial phase value and the initial code frequency value until the reverse-order data completes the synchronization process.
Optionally, the step of capturing the received signal specifically includes: the received signal is acquired by a receiver such that the code phase error of the received signal with a local spreading code is within a half chip period.
Optionally, the loop tracking of the stripped data is performed until the loop locking or data ending step, which specifically includes:
initializing loop tracking parameters of a traditional code synchronization circuit to obtain loop tracking initialization parameters;
acquiring a local advanced spreading code and a local delayed spreading code generated by a local code NCO in a traditional code synchronization circuit, and respectively carrying out integral zero clearing on the stripped data and the multiplication result of the advanced spreading code and the delayed spreading code so as to obtain a correlation accumulation result;
determining a code phase error of the local code and the received signal based on the correlation accumulation result;
processing the loop tracking initialization parameter and the code phase error by using a loop filter to update a loop tracking parameter;
if the loop does not reach the locking state, judging whether the received data of the next integration period exist, if so, returning to execute the step of acquiring the local advanced spreading code and the delayed spreading code generated by the local code NCO; if not, recording the loop tracking parameters and the accumulated phase value at the current moment, and finishing the loop tracking;
and if the loop reaches the locking state, recording the loop tracking parameters and the accumulated phase value at the locking moment to finish loop tracking.
Optionally, the loop tracking initialization parameter includes setting the phase detection error in the previous integration period to zero and setting the output result of the loop filter to zero.
Optionally, the expression of determining the initial phase value of the reverse order data based on the accumulated phase value during loop locking is as follows:
phInit=-phCode；
in the formula, phInit is an initial phase value of the reverse order data, and phCode is an accumulated phase value when the loop is locked.
Optionally, the loop tracking initialization parameters further include initialization of an initial code frequency; the step of updating the initial code frequency value according to the initial phase value specifically includes:
taking the initial phase value of the reverse order data as the initial phase of a local reverse code NCO, and updating the frequency of the initial code by utilizing the output result of the loop filter; wherein, the expression of the updated initial code frequency is:
fchip 1 =fNCo0+fchip 0 ；
in the formula, fchip 1 For the updated initial code frequency, fNCo0 is the loop filter output result, fchip 0 Is the initial code frequency before updating.
Optionally, the performing loop iteration on the inverted sequence data by using the initial phase value and the initial code frequency value until the inverted sequence data completes a synchronization process step specifically includes:
initializing loop tracking parameters of a reverse code synchronization circuit to obtain loop tracking initialization parameters;
acquiring a local advanced spreading code and a local delayed spreading code generated by a local reverse code NCO in a reverse code synchronization circuit according to the initial phase value and the initial code frequency value, and performing integral zero clearing on the advanced spreading code and the delayed spreading code respectively with a multiplication result of stripped data to obtain a correlation accumulation result;
determining a code phase error of the local code and the received signal based on the correlation accumulation result;
processing the code phase error and the loop tracking initialization parameter by using a loop filter to update a loop tracking parameter;
judging whether the iteration of the reverse order data is finished, if not, returning to the step of acquiring the local advanced spreading code and the delayed spreading code generated by the local reverse code NCO in the reverse code synchronous circuit according to the initial phase value and the initial code frequency value; if yes, the synchronization process is completed.
In addition, in order to achieve the above object, the present invention further provides an inverse extrapolation-based asynchronous burst signal timing synchronization apparatus, including:
the stripping module is used for carrying out carrier synchronization on the received signals after the received signals are captured and stripping the carriers of the received signals according to the carrier synchronization result to obtain stripping data;
the loop tracking module is used for performing loop tracking on the stripped data until loop locking or data ending and recording the loop locking time or the data ending time as T time;
the arrangement module is used for carrying out reverse order arrangement on the stripped data from the last sampling point to the first sampling point in the T-time integration period to obtain reverse order data;
an updating module, configured to determine an initial phase value of the reverse order data based on an accumulated phase value during loop locking, and update an initial code frequency value according to the initial phase value;
and the synchronization module is used for performing loop iteration on the reverse-order data by using the initial phase value and the initial code frequency value until the reverse-order data completes the synchronization process.
In addition, in order to achieve the above object, the present invention also provides an asynchronous burst signal timing synchronization apparatus based on reverse extrapolation, including: a memory, a processor and a reverse extrapolation based asynchronous burst signal timing synchronization method program stored on the memory and executable on the processor, the reverse extrapolation based asynchronous burst signal timing synchronization method program when executed by the processor implementing the steps of the reverse extrapolation based asynchronous burst signal timing synchronization method as described above.
In addition, in order to achieve the above object, the present invention further provides a storage medium having stored thereon a reverse extrapolation-based asynchronous burst signal timing synchronization method program, which when executed by a processor implements the steps of the reverse extrapolation-based asynchronous burst signal timing synchronization method as described above.
The method extrapolates the initial phase and code Doppler of the code on the reverse time axis by using the measurement result of the locking time of the traditional code ring, simultaneously carries out reverse sequence arrangement on the stored received data from the locking time of the traditional code ring, sends the result of the initial phase and the code Doppler of the extrapolation together into another code ring, quickly aligns the local code on the reverse time axis, and starts demodulation after the demodulation condition is reached. The invention solves the problems that the traditional code ring is limited by the loop convergence time and cannot synchronously align the data before convergence and cannot synchronize the short-time signal by utilizing the information extrapolation of the reverse time axis and the reverse sequence of the received data, can reduce the length of the transmitted data and enhance the interception resistance of the system under the condition of transmitting the same effective information under a burst/burst communication system, and can process the influence of code Doppler introduced by the high dynamic of a transmitting/receiving end on the reverse code ring compared with the prior art.
Drawings
FIG. 1 is a schematic diagram of an asynchronous burst signal timing synchronization apparatus based on reverse extrapolation according to the present invention;
FIG. 2 is a flow chart of an asynchronous burst signal timing synchronization method based on reverse extrapolation according to the present invention;
FIG. 3 is a schematic diagram illustrating the asynchronous burst timing synchronization method based on reverse extrapolation in accordance with the present invention;
FIG. 4 is a detailed flowchart of the asynchronous burst signal timing synchronization method based on reverse extrapolation according to the present invention;
FIG. 5 is a schematic diagram showing the relationship between the sampling point and the integration period of the signal during the synchronization process of the present invention;
FIG. 6 is a forward tracking integrated amplitude curve for a 50ms signal duration during synchronization in accordance with the present invention;
FIG. 7 is an integrated amplitude curve of reverse fine synchronization when the signal lasts 50ms in the synchronization process of the present invention;
FIG. 8 is a plot of the integrated amplitude of the forward trace of the present invention during synchronization with a signal lasting 25 ms;
FIG. 9 is an integrated amplitude curve for reverse continuous tracking with a signal duration of 25ms during synchronization according to the present invention;
fig. 10 is a block diagram of an asynchronous burst signal timing synchronization apparatus based on reverse extrapolation according to the present invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an asynchronous burst signal timing synchronization apparatus based on reverse extrapolation according to an embodiment of the present invention.
The device may be a User Equipment (UE) such as a Mobile phone, smart phone, laptop, digital broadcast receiver, Personal Digital Assistant (PDA), tablet computer (PAD), handheld device, vehicular device, wearable device, computing device or other processing device connected to a wireless modem, Mobile Station (MS), or the like. The device may be referred to as a user terminal, portable terminal, desktop terminal, etc.
In general, an asynchronous burst signal timing synchronization apparatus based on inverse extrapolation includes: at least one processor 301, a memory 302, and a reverse extrapolation based asynchronous burst signal timing synchronization program stored on the memory and executable on the processor, the reverse extrapolation based asynchronous burst signal timing synchronization program configured to implement the steps of the reverse extrapolation based asynchronous burst signal timing synchronization method as previously described.
The processor 301 may include one or more processing cores, such as a 4-core processor, an 8-core processor, and so on. The processor 301 may be implemented in at least one hardware form of a DSP (Digital Signal Processing), an FPGA (Field-Programmable Gate Array), and a PLA (Programmable Logic Array). The processor 301 may also include a main processor and a coprocessor, where the main processor is a processor for processing data in an awake state, and is also called a Central Processing Unit (CPU); a coprocessor is a low power processor for processing data in a standby state. In some embodiments, the processor 301 may be integrated with a GPU (Graphics Processing Unit) that is responsible for rendering and drawing content that the display screen needs to display. Processor 301 may also include an AI (Artificial Intelligence) processor for processing operations related to inverse extrapolation based asynchronous burst timing synchronization such that inverse extrapolation based asynchronous burst timing synchronization models may train learning autonomously, improving efficiency and accuracy.
In some embodiments, the terminal may further include: a communication interface 303 and at least one peripheral device. The processor 301, the memory 302 and the communication interface 303 may be connected by a bus or signal lines. Various peripheral devices may be connected to communication interface 303 via a bus, signal line, or circuit board. Specifically, the peripheral device includes: at least one of radio frequency circuitry 304, a display screen 305, and a power source 306.
The communication interface 303 may be used to connect at least one peripheral device related to I/O (Input/Output) to the processor 301 and the memory 302. The communication interface 303 is used for receiving the movement tracks of the plurality of mobile terminals uploaded by the user and other data through the peripheral device. In some embodiments, processor 301, memory 302, and communication interface 303 are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor 301, the memory 302 and the communication interface 303 may be implemented on a single chip or circuit board, which is not limited in this embodiment.
The Radio Frequency circuit 304 is used for receiving and transmitting RF (Radio Frequency) signals, also called electromagnetic signals. The radio frequency circuit 304 communicates with a communication network and other communication devices through electromagnetic signals, so as to obtain the movement tracks and other data of a plurality of mobile terminals. The rf circuit 304 converts an electrical signal into an electromagnetic signal to transmit, or converts a received electromagnetic signal into an electrical signal. Optionally, the radio frequency circuit 304 comprises: an antenna system, an RF transceiver, one or more amplifiers, a tuner, an oscillator, a digital signal processor, a codec chipset, a subscriber identity module card, and so forth. The radio frequency circuitry 304 may communicate with other terminals via at least one wireless communication protocol. The wireless communication protocols include, but are not limited to: metropolitan area networks, various generation mobile communication networks (2G, 3G, 4G, and 5G), Wireless local area networks, and/or WiFi (Wireless Fidelity) networks. In some embodiments, the rf circuit 304 may further include NFC (Near Field Communication) related circuits, which are not limited in this application.
The display screen 305 is used to display a UI (User Interface). The UI may include graphics, text, icons, video, and any combination thereof. When the display screen 305 is a touch display screen, the display screen 305 also has the ability to capture touch signals on or above the surface of the display screen 305. The touch signal may be input to the processor 301 as a control signal for processing. At this point, the display screen 305 may also be used to provide virtual buttons and/or a virtual keyboard, also referred to as soft buttons and/or a soft keyboard. In some embodiments, the display screen 305 may be one, the front panel of the electronic device; in other embodiments, the display screens 305 may be at least two, respectively disposed on different surfaces of the electronic device or in a folded design; in still other embodiments, the display screen 305 may be a flexible display screen disposed on a curved surface or a folded surface of the electronic device. Even further, the display screen 305 may be arranged in a non-rectangular irregular figure, i.e. a shaped screen. The Display screen 305 may be made of LCD (liquid crystal Display), OLED (Organic Light-Emitting Diode), and the like.
The power supply 306 is used to power various components in the electronic device. The power source 306 may be alternating current, direct current, disposable or rechargeable. When the power source 306 includes a rechargeable battery, the rechargeable battery may support wired or wireless charging. The rechargeable battery may also be used to support fast charge technology.
Those skilled in the art will appreciate that the architecture shown in fig. 1 does not constitute a limitation of an asynchronous burst signal timing synchronization apparatus based on reverse extrapolation, and may include more or fewer components than those shown, or some components in combination, or a different arrangement of components.
An embodiment of the present invention provides an asynchronous burst signal timing synchronization method based on reverse extrapolation, and referring to fig. 2, fig. 2 is a schematic flow diagram of the asynchronous burst signal timing synchronization method based on reverse extrapolation according to the present invention.
In this embodiment, the asynchronous burst signal timing synchronization method based on reverse extrapolation includes the following steps:
step S100, after the received signal is captured, the received signal is subjected to carrier synchronization, and the carrier of the received signal is stripped according to the carrier synchronization result to obtain stripped data.
Specifically, the received signal acquisition step specifically includes: the received signal is captured by the receiver so that the code phase error of the received signal and the local spreading code is within a half chip period to achieve coarse synchronization of the received data.
And step S200, performing loop tracking on the stripped data until loop locking or data ending, and recording the loop locking time or the data ending time as T time.
Specifically, in the process of performing loop tracking on the stripped data until the loop is locked or the data is ended, the following steps may be specifically adopted:
initializing loop tracking parameters of a traditional code synchronization circuit to obtain loop tracking initialization parameters; acquiring a local advanced spreading code and a local delayed spreading code generated by a local code NCO in a traditional code synchronization circuit, and respectively carrying out integral zero clearing on the stripped data and the multiplication result of the advanced spreading code and the delayed spreading code so as to obtain a correlation accumulation result; determining a code phase error of the local code and the received signal based on the correlation accumulation result; processing the loop tracking initialization parameter and the code phase error with a loop filter to update a loop tracking parameter.
If the loop does not reach the locking state, judging whether the received data of the next integral period exist, if so, returning to the step of acquiring the local advanced spreading code and the delayed spreading code generated by the local code NCO; if not, recording the loop tracking parameters and the accumulated phase value at the current moment, and finishing loop tracking; and if the loop reaches the locking state, recording the loop tracking parameters and the accumulated phase value at the locking moment to finish loop tracking.
It should be noted that the loop tracking initialization parameter includes zeroing the phase detection error in the previous integration period and zeroing the output result of the loop filter.
Initializing the loop tracking parameters comprises zeroing a phase discrimination error in the last integration period and zeroing an output result of a loop filter.
And step S300, carrying out reverse sequence arrangement on the stripped data from the last sampling point to the first sampling point in the integration period at the moment T to obtain reverse sequence data.
It should be noted that the reverse order should satisfy: and taking the last sampling point in the last integration period before the reverse order operation as the 1 st sampling point after the reverse order, and sequentially exchanging one by one until the 1 st sampling point in the original sampling data.
Step S400, determining an initial phase value of the reverse order data based on the accumulated phase value during loop locking, and updating an initial code frequency value according to the initial phase value.
Specifically, based on the accumulated phase value at the time of loop locking, the expression for determining the initial phase value of the reverse order data is as follows:
phInit=-phCode；
in the formula, phInit is an initial phase value of the reverse order data, and phCode is an accumulated phase value when the loop is locked.
Furthermore, the loop tracking initialization parameter further comprises initialization of the initial code frequency; the step of updating the initial code frequency value according to the initial phase value specifically includes:
taking the initial phase value of the reverse order data as the initial phase of a local reverse code NCO, and updating the frequency of the initial code by utilizing the output result of the loop filter; wherein, the expression of the updated initial code frequency is:
fchip 1 =fNCo0+fchip 0 ；
in the formula, fchip 1 For the updated initial code frequency, fNCo0 is the loop filter output result, fchip 0 Is the initial code frequency before updating.
And S500, performing loop iteration on the reverse-order data by using the initial phase value and the initial code frequency value until the reverse-order data completes the synchronization process.
Specifically, in the process of performing loop iteration on the reverse-order data, the following steps may be adopted:
initializing loop tracking parameters of a reverse code synchronization circuit to obtain loop tracking initialization parameters; acquiring a local advanced spreading code and a local delayed spreading code generated by a local reverse code NCO in a reverse code synchronization circuit according to the initial phase value and the initial code frequency value, and performing integral zero clearing on the advanced spreading code and the delayed spreading code and a multiplication result of stripped data respectively to obtain a correlation accumulation result; determining a code phase error of the local code and the received signal based on the correlation accumulation result; processing the code phase error and the loop tracking initialization parameter by using a loop filter to update a loop tracking parameter; judging whether the iteration of the reverse order data is finished, if not, returning to the step of acquiring the local advanced spreading code and the delayed spreading code generated by the local reverse code NCO in the reverse code synchronous circuit according to the initial phase value and the initial code frequency value; if yes, the synchronization process is completed.
The embodiment provides an asynchronous burst signal timing synchronization method based on reverse extrapolation, and aims to solve the problem that the existing code synchronization method suitable for short-time burst spread spectrum signals is large in calculation amount or is not suitable for a scene with large code Doppler frequency offset.
Specifically, the method comprises the following steps: firstly, locally storing sampled data; capturing sampling data by using a local code to realize coarse synchronization of received data; then carrying out carrier synchronization and carrying out carrier stripping; sending the data after carrier stripping into a code synchronization module, realizing early-late code generation, correlation operation, integration and zero clearing, phase discrimination and filtering through a local code NCO, and driving the local code NCO to realize closed-loop tracking according to a filtering result; if code locking is not achieved in the last integration period of the tracked local data, performing reverse order processing on the received signal and the local code, compensating an initial phase introduced by reverse order operation, and updating a phase discrimination error of the last integration period in loop filtering parameters; after loop locking is realized through multiple iterative tracking of forward and reverse data, the reverse sequence operation of a received signal and a local code is repeatedly carried out, the initial phase introduced by the reverse sequence operation is compensated, the phase discrimination error in the previous integral period in loop filtering and the loop filtering output result in the previous integral period are set to be zero, and the initial frequency of the local code NCO is updated; and further, the code tracking is continued, and the fine synchronization of all the code phases of the received signals is realized.
Further, the coarse synchronization of the received data should satisfy: and ensuring that the code phase error of the received signal and the local spreading code is within a half chip period.
Further, the loop filter comprises a first order loop filter and a second order loop filter;
further, the reverse order processing should satisfy: and taking the last sampling point in the last integration period before the reverse order operation as the 1 st sampling point after the reverse order, and sequentially exchanging one by one until the 1 st sampling point in the original sampling data.
Further, the updating of the phase discrimination error of the previous integration period in the loop filter parameter means that the phase discrimination error of the previous integration period is inverted and updated.
Further, the initial frequency of the local code NCO is updated by adding the initial frequency of the local code NCO to the output value of the loop filter.
Optionally, after the loop is locked, the reverse order operation and the subsequent fine synchronization operation of the received signal and the local code can be performed at once, and at this time, fine synchronization of all received signal code phases can be realized through simultaneous forward and reverse tracking by adding the cost of one loop filter; or the tracking can continue to the last integration period of the received signal after locking, and then data reverse order and fine synchronization operation are carried out, and code synchronization is realized under the condition of equivalent hardware complexity to that of the traditional synchronization method.
In the embodiment, under a burst/burst communication system, useful information is borne by using the synchronous spread spectrum code, the length of transmitted data is reduced under the condition of transmitting the same effective information, and the anti-interception capability of the system is enhanced. Compared with the prior art, the method can process the influence of code Doppler introduced by high dynamic of the transmitting/receiving end on the reverse code loop. And the method can also be used for the code synchronization problem when the received data is too short and the data length is not enough to support the code ring-in lock. The method belongs to the expansion and optimization of the traditional closed-loop tracking means of the loop, solves the problems that the existing closed-loop method cannot realize complete burst signal code synchronization and even cannot lock, and simultaneously keeps the characteristic of low computation complexity of the closed-loop tracking method of the loop.
For the convenience of understanding, the present embodiment provides a specific application example of the asynchronous burst signal timing synchronization method based on reverse extrapolation, which is specifically as follows:
referring to fig. 3, the invention is composed of two parts of traditional code ring synchronization and reverse time axis code synchronization, wherein the component of the reverse time axis code synchronization module is added with three submodules of data reverse order, code initial phase calculation and code initial frequency calculation relative to the traditional code synchronization module, the local reverse code NCO submodule in the reverse time axis code synchronization module is consistent with the local code NCO module in the traditional code ring synchronization in implementation mode, and compared with the traditional code NCO, the local code NCO submodule in the invention also needs to compensate the phase jump caused by reverse data according to the input data, and has a forward code and a reverse code local codes, and after reverse operation, the NCO submodule alternately uses the two local codes; the loop filter submodule in the traditional code synchronization module and the loop filter submodule in the inverse time axis code synchronization module have one more phase discrimination error negation function. In addition, the implementation modes of submodules such as the integral zero clearing, the code discriminator and the like are consistent with the implementation modes of corresponding submodules in the traditional code ring synchronous part.
Specifically, the data reverse order module carries out reverse order processing on the received signals, directly replaces the received signals with reverse order data when a loop is not locked, and sends the data after the reverse order to the traditional code synchronization module for tracking processing; when the loop is locked, the reverse order data is directly sent to the reverse time axis code synchronization module to carry out fine synchronization on the reverse order data.
Specifically, the function of negating the phase discrimination error of the loop filtering submodule in the conventional code synchronization module means that the phase discrimination error in the previous integration period is negated at the initial time after the data reversal sequence when the loop is not locked, and the negated phase discrimination error is used as an intermediate parameter in the loop filter for filtering.
Specifically, the code initial phase calculation module calculates the initial phase of the local code at the time of starting the reverse sequence according to the code phase and the sampling period of the local code, the code initial frequency and the code frequency error. When the loop is not locked, the initial code phase is sent to a local code NCO submodule in a traditional code synchronization module; and sending the initial phase of the loop locking time code to a local code NCO submodule in the reverse time axis code synchronization module.
Optionally, the inverse time axis code synchronization module may simplify implementation, retain data inverse sequence, code initial phase calculation and code initial frequency calculation sub-modules, and reuse an integral zero clearing, code discriminator, loop filtering and local code NCO sub-module in the conventional code synchronization module. The cost is that the tracking is continued to the last integration period of the received signal after locking, and then the data reverse order and fine synchronization operation are carried out.
Referring to fig. 4, the steps of the present invention are as follows.
Step 3-1, loop tracking initialization parameters: and setting the phase detection error phErr0 to zero in the last integration period, setting the output result fNCo0 of the loop filter to zero, and setting the initial code frequency fchip.
And 3-2, generating local leading and lagging spread spectrum codes by the local code NCO, multiplying the local leading and lagging spread spectrum codes by the I, Q branch data obtained in the step 2 respectively, and sending the multiplication result to an integral zero clearing module to obtain four-way correlation accumulation results IES, ILS, QES and QLS.
And 3-3, sending the correlation accumulation result in the step 3-2 to a code discriminator to obtain a code phase error phErr1 of the local code and the received signal.
And 3-4, sending the code phase error phErr1, the phase detection error phErr0 in the last integration period and the loop filter output result fNCo0 in the last integration period in the step 3-3 into the loop filter, and then updating the phase detection error phErr0= phErr1 in the last integration period and the loop filter output result fNCo0= fNCo1 in the last integration period.
And 3-5, repeating the steps 3-2 to 3-4, continuously iterating the loop until the loop reaches a locking state or data is finished, recording the loop locking time or the data finishing time as T time, recording the output result fNCo0 of the loop filter at the locking time, detecting a phase error phErr0, recording the accumulated code phase value of the local code NCO as phCode, receiving the data index indData, and simultaneously continuing loop tracking to finish fine synchronization of data after the locking time in the received data.
And 4, receiving data in reverse order arrangement: and carrying out reverse sequence arrangement on the received data from the last sampling point in the T-time integration period to the initial receiving time, and recording the reverse sequence data as dIinv and dQinv.
phInit=-phCode
step 6, initializing reverse-order loop tracking parameters: setting the phase discrimination error phErr0 in the last integration period to zero, setting the output result fNCo0 of the loop filter in the last integration period to zero, and taking the initial phase phInit in the step 5 as the initial phase of the local reverse code NCO and updating the initial code frequency fchip 1 =fNCo0+fchip 0 In the formula, fchip 1 For the updated initial code frequency, fNCo0 is the loop filter output result, fchip 0 Is the initial code frequency before updating.
Step 7, reverse data fine synchronization: and (5) sending the reverse order data in the step (4), the reverse data initial phase in the step (5) and other tracking parameters calculated in the step (6) into a reverse time shaft code synchronization module to perform precise synchronization of the reverse order data. The specific implementation of code loop tracking can be subdivided into the following sub-steps.
Step 7-1, loop tracking initialization parameters: and (3) setting the phase discrimination error phErr0 to zero in the last integration period, setting the output result fNCo0 of the loop filter to zero, and setting the initial code frequency to be the initial code frequency fchip obtained in the step (6).
And 7-2, generating local leading and lagging spread spectrum codes by the local reverse code NCO, multiplying the local leading and lagging spread spectrum codes by the I, Q branch data obtained in the step 4 respectively, and sending the multiplication result to an integral zero clearing module to obtain four-way correlation accumulation results IES, ILS, QES and QLS.
And 7-3, sending the correlation accumulation result in the step 7-2 to a code discriminator to obtain a code phase error phErr1 of the local code and the received signal.
And 7-4, sending the code phase error phErr1, the phase detection error phErr0 in the last integration period and the loop filter output result fNCo0 in the last integration period in the step 7-3 into the loop filter, and then updating the phase detection error phErr0= phErr1 in the last integration period and the loop filter output result fNCo0= fNCo1 in the last integration period.
And 7-5, repeating the steps 7-2 to 7-4, and continuously iterating the loop until the last integration period is reached to finish the fine synchronization of all the received data.
Optionally, when the length of the received data is not enough to support the loop filter to enter the locked state, the reverse order operation described in step 4 may be performed on the received data and the spreading code for multiple times, and the tracking processes of steps 3-2 to 3-5 are performed, and at each time of reverse order, the initial code phase after the data is reverse order is calculated according to step 5, but the update rule of the loop tracking parameter at the time of reverse order initial tracking is as follows: the phase discrimination error in the last integration period is inverted, namely phErr0= -phErr 0; the output result of the loop filter in the last integration period, fNCo0, and the initial code frequency, fchip, are unchanged; and taking the initial phase phInit in the step 5 as the initial phase of the NCO. And (4) when the reverse tracking process is continued until the spread spectrum code is locked, executing the step 4 to the step 7 to realize the code synchronization of all the received data.
Referring to FIG. 5, a schematic of the sampling versus integration period is shown, where M is (n-1) 、M (n) And M (n+1) Respectively representing the number of sampling points, t, within an integration period n-1, an integration period n and an integration period n +1 1 (n) Representing the time interval between the end of the signal of the integration period n and the last sample point within the integration period n. Assuming that the loop is locked during the integration period n, the 1 st sampling point of the reverse order data should be the Mth sampling point within the integration period n (n) A 1 st sampling point of the reverse order data is an Mth sampling point in an integration period n (n) And the sampling points and the like are repeated until the 1 st sampling point of the 1 st integration period is used as the 1 st sampling point of the inverted data. The product of the time interval between the end of the signal in integration period n and the last sample in integration period n and the code rate, i.e. t 1 (n) Fchip is the initial phase phInit of the reverse order data in step 5.
Specific example 1:
a, B two nodes are considered to communicate by adopting a spread spectrum system signal, the system carrier frequency is 2GHz, the spread spectrum multiple is 1023 times, the code rate fchip =10.23MHz, and the sampling frequency fs =24 MHz. The radial velocity of the a node and the B node is v =3000m/s, the acceleration is 0, and the code doppler is 102.3Hz under the above conditions. Taking the example that the node B sends the spread spectrum data with the length of 50ms, the node A utilizes the method of the invention to carry out code synchronization after receiving and storing the sampling data. In the simulation, the phase error of the acquired code is set to 0.4 chip, the loop bandwidth is set to 90Hz, the initial code frequency is set to fchip =10.23MHz, and the integrated code length is L = 1023.
Referring to fig. 6, a plot of the integrated amplitude of the instantaneous, early and late codes for forward tracking at 50ms duration is shown. Fig. 6 illustrates that under the above conditions, the loop lock entry time is about 40ms, the integrated amplitude reaches around the maximum value 2400 after lock entry, and the integration curves of the early code and the late code almost coincide.
In this embodiment, after the forward tracking completes tracking of all the received data, the reverse order processing, initial phase calculation and subsequent fine synchronization operation are performed. After the last integration period of forward tracking is finished, the loop filter outputs fNCo0=101.54, and the code phase of the last sampling point is phCode = -0.13723. Setting the initial code frequency of the reverse code NCO of the local code in the time shaft code synchronization module as fchip according to the method in the step 6 1 =fNCo0+fchip 0 =10230101.54 Hz; according to the method in the step 5, the initial code phase of the local code reverse code NCO in the reverse time axis code synchronization module is set as: phInit = 0.13723. The reverse time axis code synchronization module completes the fine synchronization of all the received signal spread spectrum codes.
Referring to fig. 7, a plot of the integrated amplitude of the instantaneous, early and late codes during back tracking for a signal duration of 50ms is shown. Fig. 7 illustrates that after the loop is locked, the inverse fine tracking phase achieves tracking, i.e., lock-in, the integrated amplitudes of all data are around the maximum 2400, and the integration curves of the early code and the late code almost coincide.
Specific example 2:
similarly to embodiment 1, A, B is considered to communicate two nodes by using spread spectrum system signals. The system carrier frequency is 2GHz, the spread spectrum multiple is 1023 times, the code rate fchip =10.23MHz, and the sampling frequency fs =24 MHz. The radial velocity of node a and node B is v =3000m/s, the acceleration is 0 and the code doppler is 102.3Hz under the above conditions. Different from the embodiment 1, considering that the node B transmits spread spectrum data with a length of 25ms, the node a performs code synchronization by using the method of the present invention after receiving and storing the sample data. In the simulation, the phase error of the acquired code is set to 0.4 chip, the loop bandwidth is set to 90Hz, the initial code frequency is set to fchip =10.23MHz, and the integrated code length is L = 1023.
Referring to fig. 8, a plot of the integrated amplitude of the instantaneous, early and late codes for forward tracking is shown for a 25ms signal duration. Fig. 8 illustrates that under the condition of embodiment 2, the loop fails to achieve the lock, i.e. the integral amplitude of the time code does not reach the maximum value 2400, and the difference between the integral curves of the early code and the late code is large.
The present embodiment performs reverse processing on the received data and the local code after the last integration period is tracked in the forward direction. Meanwhile, the reverse order received signal is sent to a traditional code synchronization module for tracking; negating and updating a phase discrimination error phErr0 in the last integration period in the traditional code synchronization module to obtain 0.015; and 5, calculating to obtain an initial phase phInit =0.1148 according to a calculation formula of the initial phase in the step 5, and sending the initial phase to a local code NCO submodule to perform corresponding code phase adjustment, so as to continue loop tracking.
Referring to fig. 9, a plot of the integrated amplitude of the instantaneous, early and late codes for reverse continuous tracking at 25ms duration of the signal is shown. Fig. 9 illustrates that the loop is locked when back tracking is about 15ms, the integral curve after locking is around 2400, and the integral curves of the early code and the late code almost coincide.
Comparing the simulation results of the embodiment 1 and the embodiment 2, the method of the invention can effectively process the problem that the unidirectional tracking can not realize locking due to too short data, and the synchronization time is equivalent to the time required by unidirectional synchronous locking while the loop locking is realized by a forward and reverse continuous synchronization mode.
Referring to fig. 10, fig. 10 is a block diagram illustrating a structure of an asynchronous burst signal timing synchronization apparatus based on reverse extrapolation according to the present invention.
As shown in fig. 10, the asynchronous burst signal timing synchronization apparatus based on reverse extrapolation according to the embodiment of the present invention includes:
a stripping module 10, configured to perform carrier synchronization on a received signal after the received signal is captured, and strip a carrier of the received signal according to a carrier synchronization result to obtain stripped data;
a loop tracking module 20, configured to perform loop tracking on the stripped data until loop locking or data end, and record a loop locking time or a data end time as a time T;
the arranging module 30 is configured to perform reverse order arrangement on the stripped data from the last sampling point to the first sampling point in the T-time integration period to obtain reverse order data;
an updating module 40, configured to determine an initial phase value of the reverse order data based on an accumulated phase value during loop locking, and update an initial code frequency value according to the initial phase value;
and a synchronization module 50, configured to perform loop iteration on the reverse order data by using the initial phase value and the initial code frequency value until the reverse order data completes a synchronization process.
Other embodiments or specific implementation manners of the asynchronous burst signal timing synchronization apparatus based on reverse extrapolation may refer to the above method embodiments, and are not described herein again.
Furthermore, an embodiment of the present invention further provides a storage medium, on which an inverse extrapolation-based asynchronous burst signal timing synchronization program is stored, which when executed by a processor implements the steps of the inverse extrapolation-based asynchronous burst signal timing synchronization method as described above. Therefore, a detailed description thereof will be omitted. In addition, the beneficial effects of the same method are not described in detail. For technical details not disclosed in embodiments of the computer-readable storage medium referred to in the present application, reference is made to the description of embodiments of the method of the present application. It is determined that the program instructions may be deployed to be executed on one computing device or on multiple computing devices located at one site or distributed across multiple sites and interconnected by a communication network, as examples.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.
It should be noted that the above-described embodiments of the apparatus are merely schematic, where the units described as separate parts may or may not be physically separate, and the parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. In addition, in the drawings of the embodiment of the apparatus provided by the present invention, the connection relationship between the modules indicates that there is a communication connection therebetween, and may be specifically implemented as one or more communication buses or signal lines. One of ordinary skill in the art can understand and implement it without inventive effort.
Through the above description of the embodiments, those skilled in the art will clearly understand that the present invention may be implemented by software plus necessary general hardware, and may also be implemented by special hardware including special integrated circuits, special CPUs, special memories, special components and the like. Generally, functions performed by computer programs can be easily implemented by corresponding hardware, and specific hardware structures for implementing the same functions may be various, such as analog circuits, digital circuits, or dedicated circuits. However, the software program implementation is a better implementation mode for the present invention in more cases. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, where the computer software product is stored in a readable storage medium, such as a floppy disk, a usb disk, a removable hard disk, a Read-only memory (ROM), a random-access memory (RAM), a magnetic disk or an optical disk of a computer, and includes instructions for enabling a computer device (which may be a personal computer, a server, or a network device) to execute the methods according to the embodiments of the present invention.
Claims (10)
1. An asynchronous burst signal timing synchronization method based on reverse extrapolation, the method comprising the steps of:
after the received signal is captured, carrying out carrier synchronization on the received signal, and stripping the carrier of the received signal according to the carrier synchronization result to obtain stripped data;
performing loop tracking on the stripped data until loop locking or data ending, and recording the loop locking time or the data ending time as T time;
carrying out reverse sequence arrangement on the stripped data from the last sampling point to the first sampling point in the T-time integration period to obtain reverse sequence data;
determining an initial phase value of the reverse order data based on an accumulated phase value during loop locking, and updating an initial code frequency value according to the initial phase value;
and performing loop iteration on the reverse-order data by using the initial phase value and the initial code frequency value until the reverse-order data completes the synchronization process.
2. The method for asynchronous burst signal timing synchronization based on reverse extrapolation as claimed in claim 1, wherein the receiving signal capturing step specifically comprises: a received signal is acquired by a receiver such that a code phase error of the received signal with a local spreading code is within a half chip period.
3. The method for asynchronous burst signal timing synchronization based on reverse extrapolation as claimed in claim 1, wherein said loop tracking of stripped data until loop locking or end of data step comprises:
initializing loop tracking parameters of a traditional code synchronization circuit to obtain loop tracking initialization parameters;
acquiring a local advanced spreading code and a local delayed spreading code generated by a local code NCO in a traditional code synchronization circuit, and respectively carrying out integral zero clearing on the stripped data and the multiplication result of the advanced spreading code and the delayed spreading code so as to obtain a correlation accumulation result;
determining a code phase error of the local code and the received signal based on the correlation accumulation result;
processing the loop tracking initialization parameter and the code phase error by using a loop filter to update a loop tracking parameter;
if the loop does not reach the locking state, judging whether the received data of the next integration period exist, if so, returning to execute the step of acquiring the local advanced spreading code and the delayed spreading code generated by the local code NCO; if not, recording the loop tracking parameters and the accumulated phase value at the current moment, and finishing the loop tracking;
and if the loop reaches the locking state, recording the loop tracking parameters and the accumulated phase value at the locking moment to finish loop tracking.
4. The method of inverse extrapolation-based asynchronous burst signal timing synchronization of claim 3, wherein the loop tracking initialization parameter includes zeroing out the phase detection error and zeroing out the loop filter output result for the last integration period.
5. The inverse extrapolation-based asynchronous burst signal timing synchronization method as claimed in claim 1, wherein the accumulated phase value based on loop-locked timing is determined by the expression of the initial phase value of the inverse data:
phInit=-phCode；
in the formula, phInit is an initial phase value of the reverse order data, and phCode is an accumulated phase value when the loop is locked.
6. A method for asynchronous burst signal timing synchronization based on inverse extrapolation as in claim 3 wherein the loop tracking initialization parameters further comprise initialization of an initial code frequency; the step of updating the initial code frequency value according to the initial phase value specifically includes:
taking the initial phase value of the reverse order data as the initial phase of a local reverse code NCO, and updating the frequency of the initial code by utilizing the output result of the loop filter; wherein, the expression of the updated initial code frequency is:
fchip 1 =fNCo0+fchip 0 ；
in the formula, fchip 1 For the updated initial code frequency, fNCo0 is the loop filter output result, fchip 0 Is the initial code frequency before updating.
7. The asynchronous burst signal timing synchronization method based on reverse extrapolation as claimed in claim 1, wherein said performing loop iteration on the reverse-ordered data using the initial phase value and the initial code frequency value until the reverse-ordered data completes the synchronization process step specifically comprises:
initializing loop tracking parameters of a reverse code synchronization circuit to obtain loop tracking initialization parameters;
acquiring a local advanced spreading code and a local delayed spreading code generated by a local reverse code NCO in a reverse code synchronization circuit according to the initial phase value and the initial code frequency value, and performing integral zero clearing on the advanced spreading code and the delayed spreading code and a multiplication result of stripped data respectively to obtain a correlation accumulation result;
determining a code phase error of the local code and the received signal based on the correlation accumulation result;
processing the code phase error and the loop tracking initialization parameter by using a loop filter to update a loop tracking parameter;
judging whether the iteration of the reverse order data is finished, if not, returning to the step of acquiring the local advanced spreading code and the delayed spreading code generated by the local reverse code NCO in the reverse code synchronous circuit according to the initial phase value and the initial code frequency value; if yes, the synchronization process is completed.
8. An inverse extrapolation-based asynchronous burst signal timing synchronization apparatus, comprising:
the stripping module is used for carrying out carrier synchronization on the received signals after the received signals are captured, and stripping the carriers of the received signals according to the carrier synchronization result to obtain stripping data;
the loop tracking module is used for performing loop tracking on the stripped data until loop locking or data ending and recording the loop locking time or the data ending time as T time;
the arrangement module is used for carrying out reverse order arrangement on the stripped data from the last sampling point to the first sampling point in the T-time integration period to obtain reverse order data;
an updating module, configured to determine an initial phase value of the reverse order data based on an accumulated phase value during loop locking, and update an initial code frequency value according to the initial phase value;
and the synchronization module is used for performing loop iteration on the inverted data by using the initial phase value and the initial code frequency value until the inverted data completes the synchronization process.
9. An inverse extrapolation-based asynchronous burst signal timing synchronization apparatus, comprising: memory, a processor and a reverse extrapolation based asynchronous burst signal timing synchronization method program stored on the memory and executable on the processor, the reverse extrapolation based asynchronous burst signal timing synchronization method program when executed by the processor implementing the steps of the reverse extrapolation based asynchronous burst signal timing synchronization method according to any one of claims 1 to 7.
10. A storage medium having stored thereon a reverse extrapolation based asynchronous burst signal timing synchronization method program, which when executed by a processor implements the steps of the reverse extrapolation based asynchronous burst signal timing synchronization method according to any one of claims 1 to 7.
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