CN105187348A - Any-rate CPFSK (Continuous Phase Frequency Shift Key) signal timing synchronization method - Google Patents

Any-rate CPFSK (Continuous Phase Frequency Shift Key) signal timing synchronization method Download PDF

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CN105187348A
CN105187348A CN201510292347.2A CN201510292347A CN105187348A CN 105187348 A CN105187348 A CN 105187348A CN 201510292347 A CN201510292347 A CN 201510292347A CN 105187348 A CN105187348 A CN 105187348A
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signal
cpfsk
nco
unit
symbol
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CN105187348B (en
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袁田
马松
仇三山
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Beijing mechanical and electrical engineering general design department
CETC 10 Research Institute
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
    • H04L27/14—Demodulator circuits; Receiver circuits
    • H04L27/144—Demodulator circuits; Receiver circuits with demodulation using spectral properties of the received signal, e.g. by using frequency selective- or frequency sensitive elements
    • H04L27/152—Demodulator circuits; Receiver circuits with demodulation using spectral properties of the received signal, e.g. by using frequency selective- or frequency sensitive elements using controlled oscillators, e.g. PLL arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
    • H04L7/0276—Self-sustaining, e.g. by tuned delay line and a feedback path to a logical gate
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0332—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with an integrator-detector

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

The invention discloses an any-rate CPFSK (Continuous Phase Frequency Shift Key) signal timing synchronization method which is implemented according to the following technical scheme: an MSD unit demodulates baseband signals which are subjected to resampling processing, and a feedback signal unit carries out processing on a demodulation result so as to acquire feedback signals; a correlation operation unit carries out a correlation operation on the feedback signals and a leading branch, a real-time branch and a lagging branch of CPFSK signals, and a correlation result is subjected to coherent integration and then sent to a code ring discriminator so as to acquire phase discrimination information; a loop filter filters the phase discrimination information, and a filtering result is sent to an NCO; and a resampling unit adjusts an integration interval under control of output enable signals of the NCO, and the phase of the CPFSK signals is changed, thereby achieving a purpose of timing synchronization. According to the invention, advantages of MSD demodulation are utilized, a likelihood function envelope is detected to acquire a timing error, tracking is carried out on code Doppler by using a delay locked loop, and accurate CPFSK signal timing synchronization can be realized under a low signal to noise ratio.

Description

Arbitrary velocity CPFSK signal timing synchronous method
Technical field
The present invention relates to a kind of Timing Synchronization technology of wireless communication field, particularly relate to a kind of method based on arbitrary velocity Continuous phase frequency shift keying (ContinuousPhraseFrequencyShiftKey, CPFSK) the modulation signal Timing Synchronization of multiple-symbol detection (MSD) decision-feedback.
Background technology
Continuous phase frequency shift keying (CPFSK) belongs to the special case of Continuous Phase Modulation (CPM).Different from traditional modulation, the moment that CPM modulation signal replaces at symbol does not have SPA sudden phase anomalies, at utmost can reduce spectrum width, simultaneously, CPM or constant enveloped modulation, insensitive to the nonlinear effect of power amplifier, significantly can save transmitting power.
Traditional CPM signal adopts the mode of difference frequency discrimination to carry out demodulation usually, although this mode structure is simple, has stronger antijamming capability, also easily pass through hardware implementing to the distortion of the amplitude caused because of multipath fading and phase place aspect.But this difference frequency discrimination method is owing to existing larger " threshold effect ", only after input signal-to-noise ratio reaches certain value, detector could normal work.The Timing Synchronization of CPM signal is also the difficult point realizing CPM system, due to the Phase Continuation that signal itself has, does not have obvious amplitude transition between symbol and symbol, and Timing Synchronization extracts relative difficulty.
Timing Synchronization is also bit synchronization, sign synchronization, it is the element of communication system, namely receiving terminal produce one with send bit or the identical clock signal of character rate, for carrying out correct sampling judgement to the baseband signal after demodulation, the impact of the factor such as stress release treatment and interference.
The Performance Evaluating Indexes of Timing Synchronization mainly contains: static phase, shake, dislocation rate, settling time, retention time, synchronous thresholding signal to noise ratio etc.Wherein static phase refers to the deviation between the average phase of synchronizing signal and the phase place of optimal sampling point, is mainly used in describing synchronous precision; Shake refers to that the synchronizing signal caused due to the change of noise departs from its entopic phenomenon in time, for describing synchronous stability; Dislocation rate refers to that the synchronizing pulse train caused due to reasons such as decline, interference or send-receive clock errors departs from the frequency of original sequence phenomenon appearance, is also a measurement index of stability; Settling time is from the Received signal strength containing bit synchronization information enters demodulator, the time required till the synchronous extraction circuit that puts in place exports normal bit synchronization signal, describes the speed that synchronizing signal is caught; Retention time is from the Received signal strength containing bit synchronization information disappears, the time till the normal bit synchronization signal that the synchronous extraction circuit that puts in place exports interrupts, describes the ability maintained synchronizing signal; Synchronous thresholding signal to noise ratio refers to that, under the prerequisite ensureing certain bit synchronization quality, receive the minimum signal to noise ratio that input allows, this index embodies the adaptive capacity of bit synchronization to deep fade.
Along with improving constantly of CPFSK modulated data transmitting speed and operating distance, in order to promote demodulation performance, WilliamP.Osbome etc. propose MSD technology for the demodulation of CPFSK signal.When receiving a symbol, do not adjudicate immediately, but in multiple symbol lengths, the signal waveform received and the local waveform stored are carried out related operation, adjudicate symbol with this.In target range, MSD technology and Turbo product code (TPC) technology combine by advanced remote measurement in the works in the U.S., strengthen the performance of telemetry system.In theory, the telemetry system of these two technology is adopted to be 10 in the error rate -7condition under, compare the channel gain that original system can obtain nearly 9dB.Adopt the system of MSD technology can obtain gain, can carry out premised on accurate Timing Synchronization.The time synchronization method of environment to CPFSK signal of low signal-to-noise ratio proposes new requirement.
Existing method adopts single symbol period lead-lag likelihood detection algorithm to carry out the extraction of phase demodulation information, carries out clock regeneration by loop filter circuit, and controls lead-lag likelihood detection circuit by regeneration time clock, reaches the object of sign synchronization.But owing to utilizing this locality, ' 1 ' and ' 0 ' likelihood detection sequence detect respectively to received signal, and the phase demodulation curve obtained under low signal-to-noise ratio is not ideal enough, and net synchronization capability can not meet the requirement of MSD demodulation.
Summary of the invention
In order to solve the problems of the technologies described above, the present invention is directed to arbitrary velocity Continuous phase frequency shift keying CPFSK modulation signal, utilize the advantage of MSD demodulation, there is provided a kind of based on MSD decision-feedback, phase error information is obtained by detecting likelihood function envelope, delay lock ring structure is utilized to follow the tracks of code Doppler, the time synchronization method that still can normally work when signal to noise ratio is lower.
Above-mentioned purpose of the present invention can be reached by following measures, and a kind of arbitrary velocity CPFSK signal timing synchronous method, comprises the steps:
1. arbitrarily than down-sampled: the pulse signal within the scope of the whole sample clock frequency produced with the digital controlled oscillator NCO improved is for enable signal, resampling unit is adopted to carry out arbitrarily than down-sampled arbitrary velocity Continuous phase frequency shift keying CPFSK baseband signal, the sampling rate of CPFSK baseband signal is reduced to the D of character rate doubly, and D is integer;
2.MSD decision-feedback: utilize receiving terminal existing multiple-symbol detection MSD unit to adjudicate the CPFSK signal after down-sampled process, by feedback signal unit using the conjugated signal of CPFSK modulation signal corresponding to court verdict as feedback signal, in whole process, first D CPFSK baseband signal data is mapped as a symbol, then is D feedback signal data this sign map;
3. and line correlation: time delay module carries out delay process to the CPFSK signal after down-sampled process, obtain advanced, instant and delayed three branch roads respectively, under effective enable signal controls, three road signals carry out the parallel related operation in symbol period respectively with feedback signal, coherent integration unit carries out the correlation intergal of a period of time respectively to three road correlation result.
4. error-detecting: three road coherent integration results are sent into code ring discriminator and detected likelihood function envelope, obtain the phase error information of CPFSK signal.
5. based on delay locked loop structural adjustment signal phase: carry out filtering by loop filter to phase error information, filter result sends into the NCO improved, exported by loop filter and fix accumulation amount and be added the control word obtaining NCO, the frequency of co-controlling NCO output signal; Then traditional numeric-control oscillator NCO is improved, when the control word of NCO is greater than a half of system sampling clock frequency, to the pulse signal negate that traditional NCO obtains, obtain the pulse signal that frequency is greater than 1/2nd sampling clock frequencies; The pulse signal that NCO exports is effective enable signal of other unit in and Timing Synchronization loop enable as the integrate-dump of resampling unit simultaneously, adjusts, control Timing Synchronization loop and follow the tracks of code Doppler the phase place of CPFSK signal.
The present invention has following beneficial effect compared to prior art:
The present invention is directed to the CPFSK signal of arbitrary velocity, MSD technology is first utilized to adjudicate it, then feedback signal is obtained according to court verdict, storage gain cumulative after utilizing feedback signal relevant to corresponding modulation signal, phase error information is obtained by detecting likelihood function envelope, adopt delay lock ring structure to follow the tracks of code Doppler, still can complete accurate Timing Synchronization when signal to noise ratio is lower.
The present invention improves traditional NCO structure, enables to produce the pulse signal within the scope of whole sample clock frequency, and resampling unit is with this pulse signal for enable signal, and what can realize CPFSK signal is any than down-sampled.The control word of NCO is exported by loop filter and fixes accumulation amount and be added and obtain, fixing accumulated value is the integral multiple of character rate, the pulse signal that NCO exports is effective enable signal of other unit in and Timing Synchronization loop enable as the integrate-dump of resampling unit simultaneously, be conducive to Timing Synchronization loop to process according to CPFSK symbol period, improve Timing Synchronization precision.
The present invention utilizes the court verdict of the existing MSD unit of receiving terminal to obtain feedback signal, without the need to paying extra hardware resource cost, obtaining the phase information of CPFSK signal by detecting likelihood function envelope, assisting without the need to data, do not increase guiding expense, implementation complexity is low.
Accompanying drawing explanation
Fig. 1 is arbitrary velocity CPFSK signal timing synchronization structure circuit theory schematic diagram of the present invention.
Fig. 2 is the principle schematic of the step one in Fig. 1.
Fig. 3 is the principle schematic of the step 2 in Fig. 1.
Fig. 4 is the principle schematic of the step 3 in Fig. 1.
Fig. 5 is the principle schematic of the step 4 in Fig. 1.
Fig. 6 is the principle schematic of the step 5 in Fig. 1.
Fig. 7 is that the NCO in Fig. 1 improves circuit theory schematic diagram.
In figure: 1 resampling unit, 2MSD unit, 3 feedback signal unit, 4 related operation unit, 5 coherent integration unit, 6 yards of ring discriminators, 7 loop filters, 8 digital controlled oscillator NCO.
Embodiment
Below in conjunction with drawings and Examples, invention is further illustrated.
Consult Fig. 1.Arbitrary velocity CPFSK signal timing synchronization structure based on MSD decision-feedback comprises: resampling unit 1, MSD unit 2, feedback signal unit 3, related operation unit 4, coherent integration unit 5, code ring discriminator 6, loop filter 7 and digital controlled oscillator NCO8, wherein, the enable signal that resampling unit 1 exports according to NCO carries out, arbitrarily than down-sampled, the sampling rate of CPFSK baseband signal being reduced to the integral multiple of character rate to the CPFSK baseband signal received; Signal after resampling sends into multiple-symbol detection MSD unit 2, and utilize MSD technology to obtain court verdict, feedback signal unit 3 pairs of court verdicts process, and obtain feedback signal; Related operation unit 4 pairs of feedback signals carry out related operation with advanced, instant and delayed three tributary signals of CPFSK signal respectively; Correlated results sends into code ring discriminator 6 after coherent integration unit 5, obtains phase demodulation information; Loop filter 7 pairs of phase demodulation information carry out filtering, and filter result is sent into NCO8; NCO8 exports with loop filter and fixes accumulation amount sum for control word, and resampling unit (1), under the control of NCO (8) output enable signal, adjusts integrating range, changes the phase place of CPFSK signal, realizes Timing Synchronization.
According to the present invention, based on the arbitrary velocity CPFSK signal timing synchronous method of MSD decision-feedback, concrete steps comprise:
Consult Fig. 2.Arbitrarily than down-sampled: resampling unit is using CPFSK baseband signal as input, first accumulator is utilized to add up to input, then carry out sampling when enable signal is effective to accumulation result to be outputed signal, accumulator is reset simultaneously, then circulate this process, completes the down-sampled operation to input signal.This step is reduced to the D of character rate doubly the sampling rate of CPFSK baseband signal.
Consult Fig. 3.MSD decision-feedback: the set A BCDE of corresponding D the data of the CPFSK signal obtained after resampling unit is down-sampled ... (capitalization represents the set of D the data that CPFSK symbol is corresponding respectively) order enters MSD unit, under the control of the enable signal that MSD unit exports at NCO, according to symbol period, input signal is adjudicated, output symbol sequence abcde ... (lowercase represents a symbol respectively), under the control of the enable signal that feedback signal unit exports at NCO, each symbol is processed, obtains feedback signal A'B'C'D'E' ...Feedback signal unit wherein using the conjugated signal of CPFSK modulation signal corresponding to court verdict as feedback signal, CPFSK signal conjugation each other corresponding to ' 0 ' and ' 1 ' due to symbol, feedback signal can be obtained by following two kinds of implementations:
A. feedback signal unit first carries out negate to the symbol received: symbol, and ' 0 ' becomes, and ' 1 ', symbol ' 1 ' becomes ' 0 '; Then, CPFSK modulation is carried out to the symbol after negate, obtains feedback signal;
B. feedback signal directly carries out CPFSK modulation to the symbol received, and then gets conjugation to modulation signal, obtains feedback signal.
MSD unit after each N number of symbol, is just adjudicated current sign, so except the hardware time delay that MSD unit and feedback signal unit bring, have the time delay of N number of symbol period between feedback signal and corresponding CPFSK signal before and after continuous observation.Because initial phase is different, feedback signal and corresponding CPFSK signal not conjugation each other, but still the rule meeting that maximum appears in correlation result when phase alignment, can by detection likelihood function envelope acquisition phase error information.
Consult Fig. 4.And line correlation: parallel correlation step comprises time delay module, complex multiplier, accumulator and correlation intergal unit, complex multiplier wherein and accumulator composition digital correlator.First, time delay module carries out delay operation to CPFSK signal, obtain advanced, instant and delayed three branch roads, the phase alignment of the feedback signal that the phase place of the instant branch road making symbol corresponding is corresponding with this symbol, phase place d the symbol period more advanced than the phase place of instant branch road of advanced branch road, the phase place of delayed branch road falls behind d symbol period, d representative digit correlator spacing than the phase place of instant branch road.Then, three digital correlators carry out complex multiplication operations to three road CPFSK signals and feedback signal respectively.Then, accumulator, under enable signal controls, adds up to complex multiplier output signal in each symbol period.Finally, coherent integration unit carries out length to correlated results is N corcoherent integration.Coherent integration can high frequency signal components in erasure signal and noise, and improve signal to noise ratio, gain is directly proportional to coherent integration time.
Consult Fig. 5.Error-detecting: three road coherent integration results are admitted to a yard ring discriminator, obtain the phase error information of CPFSK signal.Optional discriminator algorithm comprise incoherently subtract delayed amplitude method in advance, incoherently subtract after-power method in advance, patibhaga-nimitta does long-pending power method and relevant dot product power method etc.Often kind of method all can be normalized.Normalization can remove amplitude sensitive, improves the performance of loop under signal to noise ratio change condition fast, contributes to making loop tracks and thresholding performance not rely on AGC performance.The normalized incoherent code ring discriminator subtracting after-power method is in advance adopted to comprise power computation module, non-coherent integration unit and error detection unit, wherein, the coherent integration results of power computation module to advanced branch road and delayed branch road asks power, and it is N that non-coherent integration unit carries out length to the performance number of coherent integration results ncnon-coherent integration, error detection unit utilize non-coherent integration results obtain phase error information:
δ = 1 2 Σ n = 1 N n c E ( n ) 2 - Σ n = 1 N n c L ( n ) 2 Σ n = 1 N n c E ( n ) 2 + Σ n = 1 N n c L ( n ) 2 (symbol)
E (n) and L (n) represent the coherent integration results of advanced branch road and delayed branch road respectively, and the normalized phase error obtained by error-detecting represents and is:
The initial phase of the identified result of current sign and the front and back symbol of current sign and each symbol has direct relation, and the phase demodulation curve that distinct symbols obtains is different.Non-coherent integration module carries out addition accumulation to the performance number of coherent integration results, can be smoothing to the identified result of multiple symbol, also can offset the shake that noise brings simultaneously, improves signal to noise ratio.Become multiple to zoom in or out correlated results and can not affect signal to noise ratio and phase error information, numerical value occurs in link after non-coherent integration and overflows, coefficient 1/N can be multiplied by non-coherent integration results cor 2n nc.
Consult Fig. 6.Based on delay locked loop structural adjustment signal phase: this step comprises the NCO of loop filter and improvement, first, loop filter carries out filtering to phase error signal, then, filter output signal is added with fixing accumulated value, obtain the control word of NCO, finally, the NCO improved adds up to control word, the pulse signal of characteristic frequency can be obtained, this pulse signal is effective enable signal of other unit in and Timing Synchronization loop enable as the integrate-dump of resampling unit simultaneously, controls Timing Synchronization loop and carries out accurate tracking to code Doppler.The fixing accumulated value σ of NCO is character rate R bd doubly, i.e. σ=DR b.
Loop filter can reduce the shake of phase error signal; reduce the impact of high-frequency noise, for phase-locked loop provides the memory of a short-term, in system due to instantaneous noise during losing lock; guarantee the rapid recapture signal of loop, the tracking of the code Doppler to dynamic change can be realized.Exponent number and noise bandwidth determine the dynamic response of loop filter to signal.The present invention is directed to different applied environments, loop filter can select single order ring, second order loop or third order PLL, in the system having FLL, can select the phase locked loop filter of being assisted by FLL.After selected filter order, can be required that the highest user's dynamic stress of the most weak signal of intensity and the required support accepted selects an appropriate noise bandwidth according to receiver.Noise bandwidth is larger, and the convergence rate of loop is faster; Otherwise the tracking of loop to signal is more accurate.On the other hand, noise bandwidth is larger, and the loop update cycle just must be shorter, when character rate is certain, must select the shorter time of integration, otherwise loop can be made to become unstable.
Consult Fig. 7.Traditional NCO is realized by phase accumulator, and export pulse in the moment that accumulated phase overturns from negative angle to positive-angle, system sampling clock frequency is f stime, it is [0, f that traditional NCO can produce frequency range s/ 2] pulse signal.The frequency f of tradition NCO output signal owith frequency word f ipass be:
f o = f i f i ∈ [ 0 , f s / 2 ] f s - f i , f i ∈ ( f s / 2 , f s ]
The frequency of the enable signal that resampling unit needs likely is greater than the half of system sampling clock frequency.In order to be met the enable signal of requirement, the structure of the present invention to traditional NCO is improved.
MOD module in the NCO improved represents asks accumulation result divided by system sampling clock frequency f sremainder; AND and NOT represent respectively ask and and inversion operation; As control word f i∈ [0, f s/ 2], time, the frequency of signal A is f i, the frequency of signal B is (f s-f i), select module output signal A; As control word f i∈ (f s/ 2, f s] time, the frequency of signal A is (f s-f i), the frequency of signal B is f i, select module output signal B.
Being described in detail the embodiment of the present invention above, applying embodiment herein to invention has been elaboration, the explanation of above embodiment just understands method and apparatus of the present invention for helping; Meanwhile, for one of ordinary skill in the art, according to thought of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.

Claims (10)

1. an arbitrary velocity CPFSK signal timing synchronous method, comprises the steps:
1) arbitrarily than down-sampled: the pulse signal within the scope of the whole sample clock frequency produced with the digital controlled oscillator NCO improved is for enable signal, resampling unit is adopted to carry out arbitrarily than down-sampled arbitrary velocity Continuous phase frequency shift keying CPFSK baseband signal, the sampling rate of CPFSK baseband signal is reduced to the D of character rate doubly, and D is integer;
2) MSD decision-feedback: utilize receiving terminal existing multiple-symbol detection MSD unit to adjudicate the CPFSK signal after down-sampled process, by feedback signal unit using the conjugated signal of CPFSK modulation signal corresponding to court verdict as feedback signal, in whole process, first D CPFSK baseband signal data is mapped as a symbol, then is D feedback signal data this sign map;
3) and line correlation: time delay module carries out delay process to the CPFSK signal after down-sampled process, obtain advanced, instant and delayed three branch roads respectively, under effective enable signal controls, three road signals carry out the parallel related operation in symbol period respectively with feedback signal, coherent integration unit carries out the correlation intergal of a period of time respectively to three road correlation result;
4) error-detecting: three road coherent integration results are sent into code ring discriminator and detected likelihood function envelope, obtain the phase error information of CPFSK signal;
5) based on delay locked loop structural adjustment signal phase: carry out filtering by loop filter to phase error information, filter result sends into the NCO improved, exported by loop filter and fix accumulation amount and be added the control word obtaining NCO, the frequency of co-controlling NCO output signal; Then traditional numeric-control oscillator NCO is improved, when the control word of NCO is greater than a half of system sampling clock frequency, to the pulse signal negate that traditional NCO obtains, obtain the pulse signal that frequency is greater than 1/2nd sampling clock frequencies; The pulse signal that NCO exports is effective enable signal of other unit in and Timing Synchronization loop enable as the integrate-dump of resampling unit simultaneously, adjusts, control Timing Synchronization loop and follow the tracks of code Doppler the phase place of CPFSK signal.
2. arbitrary velocity CPFSK signal timing synchronous method as claimed in claim 1, it is characterized in that: resampling unit is using CPFSK baseband signal as input, first accumulator is utilized to add up to input, then carry out sampling when enable signal is effective to accumulation result to be outputed signal, accumulator is reset simultaneously, then circulate this process, completes the down-sampled operation to input signal.
3. arbitrary velocity CPFSK signal timing synchronous method as claimed in claim 1, is characterized in that: feedback signal is obtained by following two kinds of implementations:
A. feedback signal unit first carries out negate to the symbol received: symbol, and ' 0 ' becomes, and ' 1 ', symbol ' 1 ' becomes ' 0 '; Then, CPFSK modulation is carried out to the symbol after negate, obtains feedback signal;
B. feedback signal directly carries out CPFSK modulation to the symbol received, and then gets conjugation to modulation signal and obtains feedback signal.
4. arbitrary velocity CPFSK signal timing synchronous method as claimed in claim 1, it is characterized in that: MSD unit is before and after continuous observation after each N number of symbol, just current sign is adjudicated, except the hardware time delay that MSD unit and feedback signal unit bring, between feedback signal and corresponding CPFSK signal, there is the time delay of N number of symbol period.
5. arbitrary velocity CPFSK signal timing synchronous method as claimed in claim 1, it is characterized in that: parallel correlation step comprises time delay module, complex multiplier, accumulator and correlation intergal unit, wherein, complex multiplier and accumulator composition digital correlator, time delay module carries out delay operation to CPFSK signal, obtain advanced, immediately with delayed three branch roads, the phase alignment of the feedback signal that the phase place of the instant branch road making symbol corresponding is corresponding with this symbol, phase place d the symbol period more advanced than the phase place of instant branch road of advanced branch road, the phase place of delayed branch road falls behind d symbol period than the phase place of instant branch road, d representative digit correlator spacing.
6. arbitrary velocity CPFSK signal timing synchronous method as claimed in claim 5, is characterized in that: three digital correlators carry out complex multiplication operations to three road CPFSK signals and feedback signal respectively; Then, accumulator, under enable signal controls, adds up to complex multiplier output signal in each symbol period; Finally, coherent integration unit carries out length to correlated results is N corcoherent integration, coherent integration can high frequency signal components in erasure signal and noise, and improve signal to noise ratio, gain is directly proportional to coherent integration time.
7. arbitrary velocity CPFSK signal timing synchronous method as claimed in claim 1, it is characterized in that: code ring discriminator comprises power computation module, non-coherent integration unit and error detection unit, wherein, the coherent integration results of power computation module to advanced branch road and delayed branch road asks power, and it is N that non-coherent integration unit carries out length to the performance number of coherent integration results ncnon-coherent integration, error detection unit utilize non-coherent integration results obtain phase error information.
8. arbitrary velocity CPFSK signal timing synchronous method as claimed in claim 1, it is characterized in that: loop filter carries out filtering to phase error signal, the filtering signal of output is added with fixing accumulated value the control word obtaining NCO; The fixing accumulated value σ of NCO is character rate R bd doubly, i.e. σ=DR b.
9. arbitrary velocity CPFSK signal timing synchronous method as claimed in claim 1, it is characterized in that: traditional numeric-control oscillator NCO is improved, when control word is greater than a half of sampling rate, to the pulse signal negate that traditional NCO obtains, obtain the pulse signal that frequency is greater than 1/2nd sampling speed; In the NCO improved, as control word f i∈ [0, f s/ 2], time, the frequency of signal A is f i, the frequency of signal B is (f s-f i), select module output signal A; As control word f i∈ (f s/ 2, f s] time, the frequency of signal A is (f s-f i), the frequency of signal B is f i, select module output signal B.
10. arbitrary velocity CPFSK signal timing synchronous method as claimed in claim 1, it is characterized in that: in the system having FLL, select the phase locked loop filter of being assisted by FLL, after selected filter order, be required that the highest user's dynamic stress of the most weak signal of intensity and the required support accepted selects noise bandwidth according to receiver.
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CN108833321A (en) * 2018-06-26 2018-11-16 中国人民解放军国防科技大学 Code CPM signal code block synchronization method based on differential phase waveform matching
CN108833321B (en) * 2018-06-26 2021-01-15 中国人民解放军国防科技大学 Code CPM signal code block synchronization method based on differential phase waveform matching
CN110401611B (en) * 2019-06-29 2021-12-07 西南电子技术研究所（中国电子科技集团公司第十研究所） Method for rapidly detecting CPFSK signal
CN110401611A (en) * 2019-06-29 2019-11-01 西南电子技术研究所（中国电子科技集团公司第十研究所） The quickly method of detection CPFSK signal
CN113158157A (en) * 2021-04-01 2021-07-23 东南大学 Method for extracting equipment fingerprint information in wired network card signal
CN113315532A (en) * 2021-05-28 2021-08-27 成都谐盈科技有限公司 Self-adaptive receiving device and method for telemetering signals with any rate
CN114124341A (en) * 2022-01-21 2022-03-01 北京融为科技有限公司 Synchronization method suitable for high-bit-rate frequency modulation signal
CN114124341B (en) * 2022-01-21 2022-05-20 北京融为科技有限公司 Synchronization method suitable for high-bit-rate frequency modulation signal
CN115051782A (en) * 2022-08-16 2022-09-13 北京航空航天大学 Timing synchronization method of continuous phase modulation system
CN116015590A (en) * 2022-12-30 2023-04-25 上海星思半导体有限责任公司 Signal phase alignment method, device and related equipment
CN115834311A (en) * 2023-02-21 2023-03-21 天津讯联科技有限公司 General CPFSK pre-filtering direct modulation device and modulation method thereof
CN115834311B (en) * 2023-02-21 2023-04-28 天津讯联科技有限公司 General CPFSK pre-filtering direct modulation device and modulation method thereof
CN117762190A (en) * 2023-12-21 2024-03-26 成都玖锦科技有限公司 Signal phase alignment method in digital domain

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