CN114883443A - Poly-Si plating removal method and application in TopCon battery preparation - Google Patents
Poly-Si plating removal method and application in TopCon battery preparation Download PDFInfo
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
- H01L31/02168—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells the coatings being antireflective or having enhancing optical properties for the solar cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
- H01L31/1868—Passivation
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- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
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- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention discloses a poly-Si plating removal method and application thereof in TopCon battery preparation, and belongs to the technical field of solar batteries. The method comprises the following steps: cleaning and texturing, diffusing boron on the front surface, retaining BSG on the front surface, removing BSG on the periphery and polishing the back, growing a tunneling oxide layer and a polysilicon layer, phosphorous on the back surface, removing PSG on the front surface and the periphery and retaining a BSG layer, removing poly-si by a dry method, cleaning and washing PSG and BSG, ninthly, aluminum oxide on the front surface, passivating layers on the front surface and the back surface, and ⑪ screen printing. The dry etching process used by the invention can completely etch the deposited polycrystalline silicon winding plating layer whether being an intrinsic layer or a doping layer, has unique advantages compared with wet cleaning, has relatively low requirement on workshop cleanliness, avoids the additional cost of sewage treatment, has lower cost, and saves process time and production cost.
Description
Technical Field
The invention belongs to the technical field of solar cells, and particularly relates to a poly-Si plating removal method and application thereof in TopCon cell preparation.
Background
The technology of a Tunnel Oxide Passivated Contact (TopCon) battery is based on an N-type silicon substrate, the front surface adopts a laminated film passivation process, and the back surface adopts a Tunnel Oxide Passivated Contact structure based on ultrathin silicon Oxide and doped polysilicon (poly-Si), so that the selective passing performance of current carriers is effectively realized, the recombination rate of minority current carriers can be greatly reduced, and the high recombination problem caused by the Contact position of an electrode is avoided. TopCon cells thus have high open circuit voltages and fill factors.
However, a major problem encountered in the industrial production process of the high-efficiency cell with such a structure is that during the process of depositing polysilicon by using LPCVD or PECVD, the wrap-around plating cannot be avoided, and the removal of the poly-Si wrap-around plating on the front surface (emitter) caused during the growth of the poly-Si layer on the back surface needs to completely remove the polysilicon wrap-around plating layer on the textured side and isolate the edges to avoid edge leakage in the solar cell, because the wrap-around plated poly-Si layer is not uniform on the whole front surface, i.e., thin in the middle and thick at the edges. Incomplete cleaning of the polysilicon overplate results in cell electrical performance and yield problems such as poor appearance, poor passivation, parasitic absorption, reduced current density, high resistance causing FF reduction, increased dark current density of the cell resulting in leakage, and therefore complete removal of the polysilicon overplate is necessary.
In the industry, most enterprises remove the plating by a wet process, and the alkaline solution and the alkaline mixed solution of the additive and the acidic mixed solution of hydrofluoric acid and nitric acid are mixed; after the acid corrosive liquid is removed from the winding coating, the square resistance of the emitter on the front side of the battery is increased greatly, the PN junction depth and the boron-doped surface concentration are both obviously reduced, the control requirement on the preparation process of the battery metalized electrode is higher, and otherwise, the problem of poor electrode burning-through is easily caused; due to the instability of the acidic corrosive liquid, most enterprises select alkali corrosion to remove the plating, the improvement range of the sheet resistance of the resistor after the alkali corrosion is relatively small, the depth of a PN junction is reduced, the surface concentration change of a boron doped layer is relatively unobvious, the adjustment window of the preparation process of the battery metallized electrode is wide, and the production stability is easy to control; however, in the alkaline etching, a silicon wafer is soaked in an etching solution, and meanwhile, a polysilicon passivation layer is also corroded, over-polishing is easily caused, a phosphorus diffusion doping process is required to match, the process complexity is increased, the service life of the solution is short, the etching solution needs to be frequently replaced, the problem of low repeatability among batches is caused, and the equipment utilization rate is reduced, so that poly-Si at the center of the front surface is easy to remove in the cleaning (removing) process by using the mixed solution, and a poly-Si layer grown at the edge position is thick and is not easy to remove, so that poly-Si removal is an important reason for limiting industrial development. Meanwhile, the wet cleaning mode has the defects of higher facility overall COO, higher requirement on workshop cleanliness, increased sewage treatment cost, higher equipment failure rate and the like, and a new cleaning mode is urgently needed to be developed in large-scale battery manufacturing.
Disclosure of Invention
The invention provides a poly-Si plating removal method and application in TopCon battery preparation for solving the technical problems in the background technology.
The invention adopts the following technical scheme: a poly-Si plating removal method comprises the following steps:
firstly, feeding the silicon wafer into a furnace body, and heating the furnace body to a preset temperature; the furnace body is provided with at least two air vent pipelines; the silicon wafer comprises: the etching device comprises a substrate, an etching stop layer arranged on the front surface of the substrate and a reaction layer arranged on the back surface of the substrate;
secondly, introducing etching gas into the furnace body through the air pipe, wherein the etching gas at least contains fluorine ions; when fluorine ions act on the front surface of the substrate, the etching stop layer is set to resist the fluorine ions;
when the fluorine ions act on the back surface of the substrate, when the reaction layer is etched, the fluorine ions stop reacting on the back surface of the substrate, and a semi-finished silicon wafer is obtained.
In a further embodiment, the substrate is an N-type silicon wafer; the etching stop layer is a BSG layer; the reaction layer is a polysilicon winding coating.
In a further embodiment, the etching gas comprises at least CF 4 、SF 6 、NF 3 And CHF 3 One of them.
In a further embodiment, the etching gas further comprisesO 3 、O 2 、N 2 And one or more of O.
In a further embodiment, the predetermined temperature is in a range of 250-650 ℃.
In a further embodiment, the tubing pressure of the ventilation tubing is controlled at 1600-.
In a further embodiment, if the ventilation pipeline is divided into two paths, the two paths are respectively arranged in the furnace mouth and the furnace; if the ventilation pipeline is three paths, the ventilation pipeline is respectively arranged at a furnace mouth, a furnace and a furnace tail, and the control flow of each path is independently adjusted through an MFC.
By adopting the technical scheme, the characteristic of the difference of the reaction rates of fluorine atoms and silicon dioxide is utilized, the extremely high reaction selectivity difference of fluorine ions and polysilicon and a PSG layer (the layer is formed in phosphorus diffusion) is utilized, and the reaction rate of the fluorine ions and the polysilicon is 10-1000 times that of silicon oxide; the BSG layer (which is formed in the boron diffusion step) can be used as a perfectly stable etch stop for fluorine ion etching, using an etching gas of CF 4 、SF 6 、NF 3 And CHF 3 Or etching gas mixed with auxiliary gas O 3 、O 2 、N 2 And removing the silicon wafer with poly-si by using the combination of O and the like as dry etching gas.
The process only depends on the activation energy of fluorine ions directly on the surface of the silicon wafer, and the activation energy of the fluorine ions can be improved by increasing the reaction temperature, increasing the flow of fluoride and increasing the radio frequency power, which is beneficial to the reaction of the fluorine ions and the polycrystalline silicon deposited on the silicon substrate around a coating layer.
The polycrystalline silicon surrounding coating comprises small single crystal grains separated by thin grain boundaries consisting of extremely thin amorphous layers, and fluorine ions formed after plasma excitation preferentially etch places with unstable chemical properties such as surface defects, grain boundaries and the like. So that the etching results in an increase in the grain boundary opening and a greater surface area of the polysilicon is exposed to fluorine ions.
According to the matching of different processes, the etching rate of the polycrystalline silicon around the coating can reach 1-3um/min, and the reaction rate is further increased under higher fluoride flow and concentration; in contrast, the etching rate of the alkaline etching solution is in the range of 0.2-0.3um/min and the etching rate of the acidic etching solution is in the range of 0.1-0.2um/min, so that the dry etching and plating method can be seen to greatly shorten the process time and save the production cost, the BSG layer provides a wide process window for fluorine ion etching of the polysilicon and ensures that the polysilicon is thoroughly cleaned of the plating layer, and the corrosion condition of the BSG layer is not observed even if the fluorine ion concentration is increased.
In a further embodiment, the silicon wafer is prepared as follows:
101, selecting an N-type silicon wafer as a substrate material, and cleaning and texturing to enable the silicon wafer to generate a pyramid-shaped surface structure, wherein the reflectivity is controlled within 11%;
step 102, using a doping source as BCl 3 Performing high-temperature boron diffusion to form a PN junction on the front surface of the silicon wafer, and continuously introducing oxygen in the high-temperature preparation process to generate a BSG layer;
103, dripping a dripping device of the mixed solution of nitric acid and hydrofluoric acid on the front surface of the silicon wafer, reserving the BSG layer on the front surface, removing the BSG layer on the outer wall of the silicon wafer, and polishing the back surface;
104, growing a tunneling oxide layer and a polycrystalline silicon winding coating on the back surface of the silicon wafer by an LPCVD (low pressure chemical vapor deposition) method;
105, performing phosphorus diffusion on the back of the silicon wafer by using a high-temperature diffusion method to generate a PSG layer;
and 106, removing the PSG layers generated on the front surface and the outer wall of the silicon wafer by using a hydrofluoric acid solution, and simultaneously keeping the BSG layer obtained in the step 103. Preferably, hydrofluoric acid in hydrofluoric acid solution: the volume ratio of water is controlled to be 1:3-1:10, and the contact time is adjusted according to the length of the tank body on site and the requirement on the rotating speed of the roller. The preservation of the BSG layer provides a wide process window for the subsequent dry stripping plating process because the BSG layer acts as an excellent barrier against fluorine ions during the fluorine ion stripping plating process and is an etch stop layer.
In a further embodiment, the thickness of the tunneling oxide layer is 1-2 nm, and the thickness of the polysilicon cladding layer is 90-130 nm;
the application of the poly-Si plating removal method in the preparation of the TopCon battery comprises the following steps:
step 1, removing a PSG layer and a BSG layer on the semi-finished silicon wafer product by wet etching;
step 2, growing an aluminum oxide film layer on the front surface of the semi-finished silicon wafer product in an atomic deposition mode;
step 3, growing passivation layers on the front side and the back side of the semi-finished silicon wafer product by a vapor deposition method;
and 4, screen printing.
In a further embodiment, the passivation layer is any one or more of silicon nitride, silicon oxynitride, or silicon oxide.
The invention has the beneficial effects that: the BSG layer is used as a mask layer, so that the poly-si winding plating layer is arranged on the BSG layer, and the poly-si on the winding plating and the isolation edge is removed in a dry method mode of PECVD by utilizing the characteristic of reaction rate difference of fluorine atoms and silicon dioxide, thereby effectively solving the problem of removing the poly-si winding plating. The method has the advantages that high parallel resistance is generated in the TopCon battery, a single-sided etching process is realized, the doped polycrystalline silicon passivation layer is hardly influenced, the process stability of the method is good, the operation is easy, and the method is favorable for industrial production.
The dry etching process can completely etch the deposited polycrystalline silicon winding coating layer whether being an intrinsic layer or a doped layer, has unique advantages compared with wet cleaning, has relatively low requirement on cleanliness of a workshop, avoids the additional cost of sewage treatment, has lower cost, and saves the process time and the production cost.
Drawings
FIG. 1 is a flow chart of the poly-Si plating removal method of the present invention.
FIG. 2 is a process diagram of the poly-Si plating removal method of the present invention in the preparation of a TopCon battery.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described and illustrated below with reference to the embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments provided in the present application without any creative effort belong to the protection scope of the present application.
The dry etching cleaning method has the advantages of being capable of being accurately controlled, thorough in cleaning, free of introducing new impurities, free of causing secondary pollution and the like, meanwhile, compared with the wet cleaning method, the dry etching cleaning method has unique advantages, relatively low requirement on cleanliness of a workshop, and avoiding of extra cost of sewage treatment, the process is mature, equipment is stable, the dry etching cleaning method is widely applied to semiconductors, the dry etching cleaning method is developed more and more rapidly in the photovoltaic industry, and relevant researches are also endless.
Example 1
A poly-Si plating removal method comprises the following steps:
(1) cleaning a silicon wafer and manufacturing a textured surface, wherein a mixed solution of hydrogen peroxide, deionized water, an additive and sodium hydroxide is used as a solution, the mass concentration of alkali texturing sodium hydroxide is 2.5%, the temperature is controlled at 82 ℃, and a pyramid textured surface with the reflectivity of 10% is manufactured;
(2) inserting the cleaned and textured silicon wafers into a quartz boat back to back and sending the quartz boat into a tubular low-pressure diffusion furnace, and using BCl at the temperature of 920- 3 Performing high-temperature boron diffusion on the front surface of the doping source, and controlling the diffusion sheet resistance to be 110 omega/□; further preferably 1000 ℃.
(3) Etching the periphery of the silicon wafer and polishing the back surface by using a mixed solution of nitric acid and hydrofluoric acid, dripping water on the front surface of the silicon wafer by using a water dripping device, and keeping a BSG layer on the front surface of the silicon wafer; the preservation of the BSG layer provides a wide process window for the subsequent dry stripping plating process because the BSG layer acts as an excellent barrier against fluorine ions during the fluorine ion stripping plating process and is an etch stop layer.
(4) Putting the silicon wafer with the polished back into LPCVD equipment, and growing a tunneling oxide layer with the thickness of about 1.2nm and a polycrystalline silicon winding coating with the thickness of 120nm on the back of the silicon wafer;
(5) inserting the silicon wafer into a quartz boat and sending the quartz boat into a tubular low-pressure diffusion furnace, and performing high-temperature phosphorus diffusion on the back polycrystalline silicon winding coating at the temperature of 750 plus 880 ℃ to control the diffusion sheet resistance to be 50 omega/□; further preferably 800 ℃.
(6) Removing PSG around the front surface and the periphery by using hydrofluoric acid solution, wherein the etching groove contains hydrofluoric acid: the volume ratio of water is 1:8, and the rotating speed of the roller is 2.7 m/min. The purpose is to preserve the BSG layer on the front side of the wafer.
The silicon wafer prepared according to the steps (1) to (6) has the following structure: from last to including down in proper order: BSG layer, substrate, tunneling oxide layer, polysilicon cladding layer and PSG layer.
And carrying out poly-Si winding plating dry removal on the silicon wafer, wherein the method comprises the following steps:
(7) by dry method of PECVD, using etching gas as CF 4 The temperature of the etching step is controlled at 650 ℃, CF 4 Introducing gas from the furnace mouth/furnace tail, controlling the flow rate of each path to be 600sccm, 600sccm and 200sccm, compensating N 2 Introducing the gas from a furnace mouth, controlling the tube pressure at 1600sccm, controlling the radio frequency power at 15000w, and controlling the etching process time at 30 s; during etching, the BSG layer provides a wide process window for fluorine ion etching of the polysilicon winding plating, the winding plating layer is guaranteed to be thoroughly cleaned, and even if the concentration of fluorine ions is increased, the corrosion condition of the BSG layer is not observed. The characteristic of the difference of the reaction rate of fluorine atoms and silicon dioxide is utilized, the extremely high reaction selectivity difference of fluorine ions and polysilicon and a PSG layer (the layer is formed in phosphorus diffusion) is utilized, and the reaction rate of the fluorine ions and the polysilicon is 10-1000 times that of silicon oxide; the BSG layer (which is formed in the boron diffusion step) can be used as a perfectly stable etch stop for the fluorine ion etch, using an etch gas of CF 4 、SF 6 、NF 3 、CHF 3 Or etching gas mixed with auxiliary gas O 3 、O 2 、N 2 And removing the silicon wafer with poly-si by using the combination of O and the like as dry etching gas.
The application of a poly-Si plating removal method in the preparation of a TopCon battery comprises the following application steps:
(8) cleaning the semi-finished silicon wafer, and cleaning the PSG layer on the back side and the BSG layer on the front side of the semi-finished silicon wafer;
(9) growing a layer of 3-8nm aluminum oxide film on the front surface by adopting an ALD (atomic deposition) mode, preparing a passivation layer on the front/back surfaces of a silicon wafer in a PECVD (plasma enhanced chemical vapor deposition) mode, and controlling the thickness of the passivation layer to be 75-85 nm;
(10) and (3) performing paste printing on the front side and the back side of the battery in a screen printing mode, and sintering and metalizing to finish the preparation of the battery.
Example 2
A poly-Si plating removal method comprises the following steps:
(1) cleaning a silicon wafer and manufacturing a textured surface, wherein a mixed solution of hydrogen peroxide, deionized water, an additive and sodium hydroxide is used as a solution, the mass concentration of alkali texturing sodium hydroxide is 2.5%, the temperature is controlled at 82 ℃, and a pyramid textured surface with the reflectivity of 10% is manufactured;
(2) inserting the cleaned and textured silicon wafers into a quartz boat back to back and sending the quartz boat into a tubular low-pressure diffusion furnace, and using BCl at the temperature of 920- 3 Performing high-temperature boron diffusion on the front surface of the doping source, and controlling the diffusion sheet resistance to be 110 omega/□;
(3) etching the periphery of the silicon wafer and polishing the back surface by using a mixed solution of nitric acid and hydrofluoric acid, dripping water on the front surface of the silicon wafer by using a dripping device, and keeping a BSG layer on the front surface;
(4) putting the silicon wafer with the polished back into LPCVD equipment, and growing a tunneling oxide layer with the thickness of about 1.2nm and a polycrystalline silicon winding coating with the thickness of 120nm on the back;
(5) inserting the silicon wafer into a quartz boat and sending the quartz boat into a tubular low-pressure diffusion furnace, and performing high-temperature phosphorus diffusion on the back polycrystalline silicon winding coating at the temperature of 750 plus 880 ℃ to control the diffusion sheet resistance to be 50 omega/□;
(6) removing PSG around the front surface and the periphery by using hydrofluoric acid solution, etching the groove to obtain hydrofluoric acid: the volume ratio of water is 1:8, and the rotating speed of the roller is 2.7 m/min.
And carrying out poly-Si winding plating dry removal on the silicon wafer, wherein the method comprises the following steps:
(7) by dry method of PECVD, using etching gas as CF 4 The temperature of the etching step is controlled at 250 ℃, CF 4 Introducing air from the furnace mouth/the furnace and the furnace tail, and controlling the flow rate of each path to be 900sccm and 900sccmsccm, 300sccm, offset N 2 And introducing the gas from a furnace mouth, controlling the pipe pressure at 3500sccm, controlling the radio frequency power at 4000w, and controlling the etching process time at 35 s.
The application of a poly-Si plating removal method in the preparation of a TopCon battery comprises the following application steps:
(8) cleaning the silicon wafer, and cleaning the PSG layer on the back side and the BSG layer on the front side of the silicon wafer;
(9) growing a 3-8nm aluminum oxide film layer on the front side by adopting an ALD (atomic layer deposition) mode, preparing a passivation layer on the front side/the back side of the silicon wafer in a PECVD (plasma enhanced chemical vapor deposition) mode, and controlling the thickness of the passivation layer to be 75-85 nm;
(10) and (3) performing paste printing on the front side and the back side of the battery in a screen printing mode, and sintering and metalizing to finish the preparation of the battery.
Example 3
A poly-Si plating removal method comprises the following steps:
(1) cleaning a silicon wafer and manufacturing a textured surface, wherein a mixed solution of hydrogen peroxide, deionized water, an additive and sodium hydroxide is used as a solution, the mass concentration of alkali texturing sodium hydroxide is 2.5%, the temperature is controlled at 82 ℃, and a pyramid textured surface with the reflectivity of 10% is manufactured;
(2) inserting the cleaned and textured silicon wafers into a quartz boat back to back and sending the quartz boat into a tubular low-pressure diffusion furnace, and using BCl at the temperature of 920- 3 Performing high-temperature boron diffusion on the front surface of the doping source, and controlling the diffusion sheet resistance to be 110 omega/□;
(3) etching the periphery of the silicon wafer and polishing the back surface by using a mixed solution of nitric acid and hydrofluoric acid, dripping water on the front surface of the silicon wafer by using a dripping device, and keeping a BSG layer on the front surface;
(4) putting the silicon wafer with the polished back into LPCVD equipment, and growing a tunneling oxide layer with the thickness of about 1.2nm and a polycrystalline silicon winding coating with the thickness of 120nm on the back;
(5) inserting the silicon wafer into a quartz boat and sending the quartz boat into a tubular low-pressure diffusion furnace, and performing high-temperature phosphorus diffusion on the back polycrystalline silicon winding coating at the temperature of 750 plus 880 ℃ to control the diffusion sheet resistance to be 50 omega/□;
(6) removing PSG around the front surface and the periphery by using hydrofluoric acid solution, etching the groove to obtain hydrofluoric acid: the volume ratio of water is 1:8, and the rotating speed of the roller is 2.7 m/min.
And carrying out poly-Si winding plating dry removal on the silicon wafer, wherein the method comprises the following steps:
(7) by dry method of PECVD, using etching gas as CF 4 The temperature of the etching step is controlled at 450 ℃, CF 4 Introducing gas from the furnace mouth/furnace tail, controlling the flow rate of each path to be 900sccm, 900sccm and 300sccm, and compensating N 2 And O 2 The flow of oxygen is controlled at 200sccm from the furnace mouth, the tube pressure is controlled at 3500sccm, the radio frequency power is controlled at 11000w, and the etching process time is 30 s.
The application of a poly-Si plating removal method in the preparation of a TopCon battery comprises the following application steps:
(8) cleaning the silicon wafer, and cleaning the PSG layer on the back side and the BSG layer on the front side of the silicon wafer;
(9) growing a 3-8nm aluminum oxide film layer on the front side by adopting an ALD (atomic layer deposition) mode, preparing a passivation layer on the front side/the back side of the silicon wafer in a PECVD (plasma enhanced chemical vapor deposition) mode, and controlling the thickness of the passivation layer to be 75-85 nm;
(10) and (3) performing paste printing on the front side and the back side of the battery in a screen printing mode, and sintering and metalizing to finish the preparation of the battery.
Comparative example
(1) Cleaning a silicon wafer and manufacturing a textured surface, wherein a mixed solution of hydrogen peroxide, deionized water, an additive and sodium hydroxide is used as a solution, the mass concentration of alkali texturing sodium hydroxide is 2.5%, the temperature is controlled at 82 ℃, and a pyramid textured surface with the reflectivity of 10% is manufactured;
(2) inserting the cleaned and textured silicon wafers into a quartz boat back to back and sending the quartz boat into a tubular low-pressure diffusion furnace, and using BCl at the temperature of 920- 3 Performing high-temperature boron diffusion on the front surface of the doping source, and controlling the diffusion sheet resistance to be 110 omega/□;
(3) removing BSG layers on the periphery and the front side of the silicon wafer and polishing the back side of the silicon wafer by using a mixed solution of nitric acid and hydrofluoric acid;
(4) putting the silicon wafer with the polished back into LPCVD equipment, and growing a tunneling oxide layer with the thickness of about 1.2nm and a polycrystalline silicon winding coating with the thickness of 120nm on the back;
(5) inserting the silicon wafer into a quartz boat and sending the quartz boat into a tubular low-pressure diffusion furnace, and performing high-temperature phosphorus diffusion on the back polycrystalline silicon winding coating at the temperature of 750 plus 880 ℃ to control the diffusion sheet resistance to be 50 omega/□;
(6) with chain switching slot type's mode, use hydrofluoric acid solution to get rid of around expanding to the front and PSG all around, etching groove hydrofluoric acid: the volume ratio of water is 1:8, and the rotating speed of the roller is 2.7 m/min.
(7) Transferring the silicon wafers discharged by the chain machine into a groove machine, and removing the winding plating poly-si through a pretreatment groove (NaOH + H2O 2), a water groove, an alkali groove (NaOH + ADD), a water groove, a post-cleaning groove (NaOH + H2O 2), a water groove, an acid groove (HCL + HF), a water groove, slow pulling and drying;
(8) growing a 3-8nm aluminum oxide film layer on the front side by adopting an ALD (atomic layer deposition) mode, preparing a passivation layer on the front side/the back side of the silicon wafer in a PECVD (plasma enhanced chemical vapor deposition) mode, and controlling the thickness of the passivation layer to be 75-85 nm;
(9) and (3) performing paste printing on the front side and the back side of the battery in a screen printing mode, and sintering and metalizing to finish the preparation of the battery.
Table 1 shows the electrical property test data
| ITEM | Eta（%） | Voc（V） | Isc（A） | Rs（mΩ） | Rsh（Ω） | FF |
| Comparative example | 24.26 | 0.713 | 13.927 | 1.218 | 1841 | 81.49 |
| Example 1 | 24.35 | 0.714 | 13.941 | 1.192 | 2755 | 81.64 |
| Example 2 | 24.33 | 0.714 | 13.93 | 1.204 | 2649 | 81.59 |
| Example 3 | 24.37 | 0.714 | 13.938 | 1.179 | 2892 | 81.68 |
Table 1 shows that the electrical test data in the embodiment of the present invention has significant advantages over the comparative example.
The conventional wet process immersion type removal of the winding plating layer can also corrode the polysilicon passivation layer while removing the winding plating layer by the corrosive solution due to the instability of the corrosive solution, so that the sheet resistance is improved, the doping surface concentration is reduced, and the over-polishing is easy to generate.
According to the invention, the BSG layer is used as a mask layer, so that the poly-si winding coating is on the BSG layer, and the poly-si on the winding coating and the isolation edge is removed by utilizing the characteristic of reaction rate difference of fluorine atoms and silicon dioxide in a dry method mode of PECVD (plasma enhanced chemical vapor deposition), so that the problem of removing the poly-si winding coating is effectively solved, and the doped polycrystalline silicon passivation layer is hardly influenced.
Claims (10)
1. The poly-Si plating removal method is characterized by comprising the following steps of:
firstly, feeding the silicon wafer into a furnace body, and heating the furnace body to a preset temperature; the furnace body is provided with at least two air vent pipelines; the silicon wafer comprises: the etching device comprises a substrate, an etching stop layer arranged on the front surface of the substrate and a reaction layer arranged on the back surface of the substrate;
secondly, introducing etching gas into the furnace body through the air pipe, wherein the etching gas at least contains fluorine ions; when fluorine ions act on the front surface of the substrate, the etching stop layer is set to resist the fluorine ions;
when the fluorine ions act on the back surface of the substrate, when the reaction layer is etched, the fluorine ions stop reacting on the back surface of the substrate, and a semi-finished silicon wafer is obtained.
2. The method of claim 1, wherein the poly-Si plating removal process,
the substrate is an N-type silicon wafer;
the etching stop layer is a BSG layer;
the reaction layer is a polysilicon winding coating.
3. The method of claim 1, wherein the etching gas comprises at least CF 4 、SF 6 、NF 3 And CHF 3 One of them.
4. The poly-Si plating removal method of claim 1, wherein the etching gas further comprises O 3 、O 2 、N 2 And one or more of O.
5. The method for removing poly-Si by coil plating according to claim 1, wherein the predetermined temperature is in a range of 250 to 650 ℃.
6. The method as claimed in claim 1, wherein the tube pressure of the ventilation tube is controlled at 1600-.
7. The poly-Si plating removal method as claimed in claim 1, wherein the silicon wafer is prepared by the following steps:
101, selecting an N-type silicon wafer as a substrate material, and cleaning and texturing to enable the silicon wafer to generate a pyramid-shaped surface structure, wherein the reflectivity is controlled within 11%;
step 102, using a doping source as BCl 3 Performing high-temperature boron diffusion to form a PN junction on the front surface of the silicon wafer, and continuously introducing oxygen in the high-temperature preparation process to generate a BSG layer;
103, dripping a dripping device of the mixed solution of nitric acid and hydrofluoric acid on the front surface of the silicon wafer, reserving the BSG layer on the front surface, removing the BSG layer on the outer wall of the silicon wafer, and polishing the back surface;
104, growing a tunneling oxide layer and a polycrystalline silicon winding coating on the back surface of the silicon wafer by an LPCVD (low pressure chemical vapor deposition) method;
105, performing phosphorus diffusion on the back of the silicon wafer by using a high-temperature diffusion method to generate a PSG layer;
and 106, removing the PSG layers generated on the front surface and the outer wall of the silicon wafer by using a hydrofluoric acid solution, and simultaneously keeping the BSG layer obtained in the step 103.
8. The method of claim 7, wherein the poly-Si plating removal process,
the thickness of the tunneling oxide layer is 1-2 nm, and the thickness of the polycrystalline silicon winding coating is 90-130 nm.
9. Use of the poly-Si coil removal method of any one of claims 1 to 8 in TopCon cell fabrication, comprising the steps of:
step 1, removing a PSG layer and a BSG layer on the semi-finished silicon wafer product by wet etching;
step 2, growing an aluminum oxide film layer on the front surface of the semi-finished silicon wafer product in an atomic deposition mode;
step 3, growing passivation layers on the front side and the back side of the semi-finished silicon wafer product by a vapor deposition method;
and 4, screen printing.
10. The use of the poly-Si plating removal method of claim 9 in the fabrication of a TopCon cell, wherein the passivation layer is any one or more of silicon nitride, silicon oxynitride, or silicon oxide.
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