CN114335237A - Preparation method of crystalline silicon solar cell and crystalline silicon solar cell - Google Patents
Preparation method of crystalline silicon solar cell and crystalline silicon solar cell Download PDFInfo
- Publication number
- CN114335237A CN114335237A CN202011053547.XA CN202011053547A CN114335237A CN 114335237 A CN114335237 A CN 114335237A CN 202011053547 A CN202011053547 A CN 202011053547A CN 114335237 A CN114335237 A CN 114335237A
- Authority
- CN
- China
- Prior art keywords
- crystalline silicon
- silicon substrate
- layer
- doped
- solar cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/546—Polycrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention provides a crystalline silicon solar cell and a preparation method thereof, belonging to the technical field of photovoltaics. The preparation method of the crystalline silicon solar cell provided by the invention deposits the doped dielectric layer on the front surface of the crystalline silicon substrate, and then carries out the crystallization degree treatment and the polarity enhancement treatment on the conductive polar semiconductor, the higher reaction temperature simultaneously causes the doped impurities in the doped dielectric layer to diffuse to the crystalline silicon substrate, because the temperature of the deposition process is lower than that of the diffusion process, the doped dielectric layer is deposited first, and then impurities are diffused by using the high-temperature process in the subsequent steps, so that the energy consumption of production equipment in the production process is reduced, thereby solving the problem of contradiction between the thickness of the mask layer and the production capacity, adjusting the thickness of the doped dielectric layer to obtain a proper thickness of the mask layer, the method has the advantages of playing a good mask role on the front surface of the crystalline silicon substrate, reducing the formation of defects in the crystalline silicon substrate caused by a high-temperature environment and improving the structural uniformity of the surface appearance of the silicon substrate.
Description
Technical Field
The invention relates to the technical field of photovoltaics, in particular to a crystalline silicon solar cell and a preparation method thereof.
Background
The crystalline silicon solar cell is a solar cell widely applied at present, wherein the compounding of a metal electrode and a crystalline silicon contact part is a key factor influencing the photoelectric conversion efficiency of the crystalline silicon cell.
The passivation metal contact structure of the tunneling layer consists of the ultrathin tunneling layer and the doped polycrystalline silicon layer, so that the composition of a metal electrode contact area can be obviously reduced, and the passivation metal contact structure has good contact performance, thereby improving the efficiency of the solar cell. Therefore, the tunneling layer passivation metal contact structure can be applied to the crystalline silicon solar cell, so that the photoelectric conversion efficiency of the crystalline silicon solar cell is improved.
However, in the preparation process of the crystalline silicon solar cell with the tunnel-through layer passivation metal contact structure, in order to obtain a good silicon oxide mask layer, a longer diffusion process time is needed to increase the production capacity of the cell, so that the production cost of the cell is indirectly increased, the reduction of the production capacity can cause the thickness of the silicon oxide mask layer to be limited, the mask effect cannot be better played, and the surface of the silicon substrate covered by the silicon oxide mask layer is damaged in the process of removing the silicon oxide mask layer through a chemical corrosion process, so that the problem of poor uniformity of the surface morphology structure of the silicon substrate is caused.
Disclosure of Invention
The invention provides a preparation method of a crystalline silicon solar cell and the crystalline silicon solar cell, and aims to solve the problems that in the prior art, in order to meet production capacity, the thickness of a mask layer is limited, and the mask effect cannot be well played.
In a first aspect, a method for preparing a crystalline silicon solar cell is provided, the method comprising:
depositing a doped dielectric layer on the front side of a crystalline silicon substrate at a first preset temperature, wherein the front side of the crystalline silicon substrate is provided with a textured structure;
forming a tunneling layer on the back surface of the crystalline silicon substrate;
depositing a conductive polar semiconductor on the surface of the tunneling layer;
performing crystallization degree treatment and polarity increasing treatment on the conductive polarity semiconductor at a second preset temperature, wherein the second preset temperature is higher than the first preset temperature, and the doped impurities of the doped dielectric layer diffuse into the crystalline silicon substrate at the second preset temperature;
and respectively forming a first electrode structure and a second electrode structure on the two sides of the crystalline silicon substrate to obtain the crystalline silicon solar cell.
Optionally, the first preset temperature is 200 ℃ to 700 ℃.
Optionally, the second preset temperature is 800 ℃ to 1100 ℃.
Optionally, the doped dielectric layer is at least one film layer of silicon oxide, silicon oxynitride and silicon nitride doped with a doping impurity, wherein the doping impurity is a boron atom or a phosphorus atom.
Optionally, the tunneling layer is at least one of a silicon nitride layer and a silicon oxide layer.
Optionally, the depositing a conductive polar semiconductor on the surface of the tunneling layer includes:
and depositing a conductive polar semiconductor on the surface of the tunneling layer by any one of a plasma enhanced chemical vapor deposition mode, an atmospheric pressure chemical vapor deposition mode, a medium pressure chemical vapor deposition mode and a low pressure chemical vapor deposition mode.
Optionally, in a case that the conductivity type of the crystalline silicon substrate is N-type, the conductive polar semiconductor is at least one of a phosphorus-doped amorphous silicon, an amorphous silicon carbide or an N-type transparent conductive film layer;
under the condition that the conductive type of the crystalline silicon substrate is P type, the conductive electrode semiconductor is at least one film layer of boron-doped amorphous silicon, amorphous silicon carbide or a P type transparent conductive film layer.
Optionally, before forming the tunneling layer on the back side of the crystalline silicon substrate, the method further includes:
removing a winding plating layer formed when the doped dielectric layer is deposited on the front side of the back surface of the crystalline silicon substrate;
and carrying out surface topography treatment on the back surface of the crystalline silicon substrate to enable the surface reflectivity of the back surface of the crystalline silicon substrate to be 15% -60%, wherein the surface topography treatment is any one of surface polishing, surface pyramid rounding treatment and surface pyramid enlarging structure.
Optionally, the forming a first electrode structure and a second electrode structure on two sides of the crystalline silicon substrate respectively to obtain a crystalline silicon solar cell includes:
removing the doped dielectric layer;
depositing a passivation layer and a first anti-reflection layer on the P-type side surface of the crystalline silicon substrate in sequence, and preparing a first metal electrode;
and depositing a second anti-reflection layer on the N-type side surface of the crystalline silicon substrate, and preparing a second metal electrode to obtain the crystalline silicon solar cell.
In a second aspect, a crystalline silicon solar cell is provided, and the crystalline silicon solar cell is prepared by the preparation method of the crystalline silicon solar cell in the first aspect.
Compared with the related art, the invention has the following advantages:
in the embodiment of the invention, the doping medium layer is deposited on the front surface of the crystalline silicon substrate, and in the subsequent crystallization degree and polarity enhancement treatment of the conductive polar semiconductor, the higher reaction temperature simultaneously diffuses the doping impurities in the doping medium layer to the crystalline silicon substrate to form a PN junction structure, because the process temperature of the deposition process is lower than the process temperature of the diffusion process, the doping medium layer is deposited first and then the high-temperature process in the subsequent steps is utilized without diffusing the impurities into the crystalline silicon substrate through the diffusion process, the energy consumption of production equipment in the production process is reduced, the problem of contradiction between the thickness of the mask layer and the production capacity is solved while the production capacity is optimized, the doping medium layer can be adjusted to obtain the proper thickness of the film layer, the good masking effect on the front surface of the crystalline silicon substrate is achieved, and the formation of defects in the crystalline silicon substrate caused by the high-temperature environment is reduced, the surface of the silicon substrate is better protected, and the structural uniformity of the surface appearance of the silicon substrate is improved.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
fig. 1 is a flow chart illustrating steps of a method for manufacturing a crystalline silicon solar cell according to an embodiment of the present invention;
fig. 2a is a schematic cross-sectional structure diagram of a cell of a first step process flow of example 1 provided by an embodiment of the present invention;
fig. 2b is a schematic cross-sectional structure diagram of a battery according to an exemplary process flow of step 1 provided in an embodiment of the present invention;
fig. 2c is a schematic cross-sectional structure diagram of a cell according to a third process flow of example 1 provided in an embodiment of the present invention;
fig. 2d is a schematic cross-sectional structure diagram of a battery according to a fourth process flow of example 1 provided in an embodiment of the present invention;
fig. 2e is a schematic cross-sectional structure diagram of a battery according to a fifth process flow of example 1 provided in an embodiment of the present invention;
fig. 2f is a schematic cross-sectional structure diagram of a battery according to a sixth process flow of example 1 provided in an embodiment of the present invention;
fig. 2g is a schematic cross-sectional structure diagram of a battery according to a seventh process flow of example 1 provided in an embodiment of the present invention;
fig. 2h is a schematic cross-sectional structure diagram of a battery according to an eighth process flow of example 1 provided in an embodiment of the present invention;
fig. 2i is a schematic cross-sectional structure diagram of a battery in a ninth process flow of example 1 according to an embodiment of the present invention;
fig. 2j is a schematic cross-sectional structure diagram of an N-type single crystalline silicon solar cell prepared in example 1 according to an embodiment of the present invention;
fig. 3a is a schematic cross-sectional structure diagram of a cell of a first step process flow of example 2 provided by an embodiment of the present invention;
fig. 3b is a schematic cross-sectional structure diagram of a battery according to an exemplary process flow of step 2 provided in an embodiment of the present invention;
fig. 3c is a schematic cross-sectional structure diagram of a cell according to a third process flow of example 2 provided in an embodiment of the present invention;
fig. 3d is a schematic cross-sectional structure diagram of a battery according to a fourth process flow of example 2 provided in an embodiment of the present invention;
fig. 3e is a schematic cross-sectional structure diagram of a battery according to a fifth process flow of example 2 provided in an embodiment of the present invention;
fig. 3f is a schematic cross-sectional structure diagram of a battery according to a sixth process flow of example 2 provided in an embodiment of the present invention;
fig. 3g is a schematic cross-sectional structure diagram of a battery according to a seventh process flow of example 2 provided in an embodiment of the present invention;
fig. 3h is a schematic cross-sectional structure diagram of a battery according to an eighth process flow of example 2 provided in an embodiment of the present invention;
fig. 3i is a schematic cross-sectional structure diagram of a battery of a ninth process flow of example 2 according to an embodiment of the present invention;
fig. 3j is a schematic cross-sectional structure diagram of a P-type single crystalline silicon solar cell prepared in example 2 according to an embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
Fig. 1 is a flow chart illustrating steps of a method for manufacturing a crystalline silicon solar cell according to an embodiment of the present invention, where the method may include:
101, depositing a doped dielectric layer on the front side of a crystalline silicon substrate at a first preset temperature, wherein the front side of the crystalline silicon substrate is provided with a textured structure.
In the embodiment of the invention, the solar cell can be a solar cell with a passivation contact structure, and can be obtained by sequentially preparing each functional layer on the basis of a crystalline silicon substrate. The crystalline silicon substrate may be an N-type crystalline silicon substrate or a P-type crystalline silicon substrate according to a conductive type, which is not particularly limited in the embodiment of the present invention. The crystalline silicon substrate is provided with a textured structure, optionally, the crystalline silicon substrate can be textured in an acid washing, alkali washing, laser texturing and other modes, and one surface of the crystalline silicon substrate with the textured structure can be used as a front surface to deposit a doped dielectric layer.
In the embodiment of the invention, the doped medium layer is a film layer doped with doped impurities, wherein the film layer can be one film layer or a combination of several film layers, and the doped medium can be determined according to the conductivity type of the crystalline silicon substrate, so that the doped medium of the doped medium layer is diffused into the crystalline silicon substrate in the subsequent high-temperature process to form a PN junction structure. The second preset temperature is the deposition process temperature of the doped dielectric layer, is lower than the diffusion process temperature, and is low in energy consumption, so that the thickness of the doped dielectric layer can be properly increased while the production capacity requirement is met, and the mask effect of the doped dielectric layer is enhanced.
Optionally, the first preset temperature is 200 ℃ to 700 ℃.
In this embodiment of the present invention, the first preset temperature may be any temperature from 200 ℃ to 700 ℃, for example, the first preset temperature may be 200 ℃, 250 ℃, 300 ℃, 350 ℃, 400 ℃, 450 ℃, 500 ℃, 550 ℃, 600 ℃, 650 ℃, 700 ℃, and the like, which is not particularly limited in this embodiment of the present invention.
Optionally, the doped dielectric layer is at least one film layer of silicon oxide, silicon oxynitride and silicon nitride doped with a doping impurity, wherein the doping impurity is a boron atom or a phosphorus atom.
In the embodiment of the present invention, the film layer of the doped dielectric layer may be one or a combination of two or more film layers of silicon oxide, silicon oxynitride, silicon nitride, and the like, wherein different doped media may be selected according to different conductivity types of the crystalline silicon substrate, for example, the N-type crystalline silicon substrate may deposit a boron doped dielectric layer, the P-type crystalline silicon substrate may deposit a phosphorus doped dielectric layer, and optionally, the doped dielectric layer may be deposited by any one deposition method of plasma enhanced chemical vapor deposition, atmospheric pressure chemical vapor deposition, medium pressure chemical vapor deposition, and low pressure chemical vapor deposition, and the total thickness of the deposited doped dielectric layer may be any thickness between 10nm and 200 nm.
And 102, forming a tunneling layer on the back surface of the crystalline silicon substrate.
In the embodiment of the invention, the tunneling layer can be formed on the back surface of the crystalline silicon substrate, the tunneling layer can be one film layer or a combined film layer of more than two film layers, optionally, the thickness of the tunneling layer can be any thickness within 1 nm-5 nm, and the fixed charge density of the tunneling layer can be 109～1012cm-2Any value within, which is not particularly limited by the embodiments of the present invention.
Optionally, the tunneling layer is at least one of a silicon nitride layer and a silicon oxide layer.
In the embodiment of the invention, the tunneling layer can be one of a silicon nitride layer and a silicon oxide layer or a combination of the two layers, wherein the tunneling layer can be deposited by plasma enhanced chemical vapor deposition, optionally oxygen plasma oxidation by plasma enhanced chemical vapor deposition, or the oxygen and nitrogen plasma mixed plasma treatment of plasma enhanced chemical vapor deposition, adopts the plasma enhanced chemical vapor deposition, can improve the definition degree between the interface of the crystalline silicon substrate and the tunneling layer, reduce the interface state density of the crystalline silicon substrate, thereby improving the chemical passivation effect of the tunneling layer on the surface of the crystalline silicon substrate, effectively controlling the fixed charge density of the tunneling layer, the adverse effect of a strong electric field formed by the fixed charges on the tunneling of the carrier in the tunneling layer can be further reduced, and the yield of the solar cell is improved. At this time, the gas source of the oxygen plasma may be one or more of oxygen, ozone, nitrous oxide (nitrous oxide), and carbon dioxide, and the gas source of the nitrogen plasma may be nitrogen, depending on the type of the tunneling layer.
Optionally, before the step S102, the method further includes:
and step S11, removing the winding plating layer formed on the back surface of the crystalline silicon substrate when the doped dielectric layer is deposited on the front surface.
In the embodiment of the invention, when the doped dielectric layer is deposited on the front surface of the crystalline silicon substrate, the winding coating layer may be formed on the back surface of the crystalline silicon substrate due to the deposition process, and the winding coating layer may affect the efficiency of the battery and the appearance of the battery, so that the winding coating layer of the doped dielectric layer on the back surface can be removed first, and the yield of the prepared battery is improved. Alternatively, the winding plating layer may be removed by an acid cleaning method, or may be prevented from being generated in the deposition process by other methods, which is not particularly limited in the embodiment of the present invention.
Step S12, performing surface topography treatment on the back surface of the crystalline silicon substrate to enable the surface reflectivity of the back surface of the crystalline silicon substrate to be 15% -60%, wherein the surface topography treatment is any one of surface polishing, surface pyramid rounding treatment and surface pyramid enlarging structure.
In the embodiment of the present invention, before the tunneling layer is formed on the back surface of the crystalline silicon substrate, surface topography processing may be further performed on the back surface of the crystalline silicon substrate, so that the surface reflectivity of the crystalline silicon substrate may be any value within 15% to 60% to improve the effect of the tunneling layer deposition, optionally, the surface topography processing may be any one of surface polishing, surface pyramid rounding, surface pyramid expansion structures, wherein the surface polishing may be acid polishing, alkali polishing, mechanical polishing, and the like, which is not particularly limited in this embodiment of the present invention.
In the embodiment of the invention, the front surface and the back surface of the crystalline silicon substrate are only used for distinguishing the surfaces of different functional layers deposited on the crystalline silicon substrate, and in the specific preparation process, any one surface of the crystalline silicon substrate can be used as the front surface of the crystalline silicon substrate, and the opposite other surface can be used as the back surface of the crystalline silicon substrate.
And 103, depositing a conductive polar semiconductor on the surface of the tunneling layer.
In the embodiment of the invention, after the tunneling layer on the back surface of the silicon substrate is obtained, the conductive polarity semiconductor can be deposited on the surface of the tunneling layer, wherein the conductive polarity of the conductive polarity semiconductor corresponds to the conductive type of the crystalline silicon substrate, so that different conductive polarity semiconductors can be selected according to the conductive type of the crystalline silicon substrate.
Optionally, in a case that the conductivity type of the crystalline silicon substrate is N-type, the conductive polar semiconductor is at least one of phosphorus-doped amorphous silicon, amorphous silicon carbide or an N-type transparent conductive film layer.
Under the condition that the conductive type of the crystalline silicon substrate is P type, the conductive electrode semiconductor is at least one film layer of boron-doped amorphous silicon, amorphous silicon carbide or a P type transparent conductive film layer.
In the embodiment of the invention, when the conductive type of the crystalline silicon substrate is N-type, the conductive polarity of the conductive polarity semiconductor can be N-type, for example, the conductive polarity semiconductor can be one film or a combined film of more than two films of phosphorus-doped amorphous silicon, amorphous silicon carbide or N-type transparent conductive films; when the conductive type of the crystalline silicon substrate is P-type, the conductive polarity of the conductive polarity semiconductor may be P-type, for example, the conductive polarity semiconductor may be one of boron-doped amorphous silicon, amorphous silicon carbide, and a P-type transparent conductive thin film layer or a combined film of two or more films, and optionally, the thickness of the conductive polarity semiconductor may be any thickness between 20nm and 200nm, which is not particularly limited in the embodiment of the present invention.
Optionally, the step 103 includes:
and step S21, depositing a conductive polar semiconductor on the surface of the tunneling layer by any one of plasma enhanced chemical vapor deposition, atmospheric pressure chemical vapor deposition, medium pressure chemical vapor deposition and low pressure chemical vapor deposition.
In the embodiment of the present invention, the deposition method for depositing the conductive polar semiconductor on the surface of the tunneling layer may be any one of plasma enhanced chemical vapor deposition, atmospheric pressure chemical vapor deposition, medium pressure chemical vapor deposition, and low pressure chemical vapor deposition, and specific reference may be made to the foregoing description of the deposition methods of the doped dielectric layer, the tunneling layer, and the like, and details are not repeated herein to avoid repetition.
And 104, performing crystallization degree treatment and polarity increasing treatment on the conductive polar semiconductor at a second preset temperature, wherein the second preset temperature is higher than the first preset temperature, and the doping impurities of the doping medium layer diffuse into the crystalline silicon substrate at the second preset temperature.
In the embodiment of the invention, the crystallization degree treatment and the polarity increasing treatment can be carried out on the conductive polar semiconductor to convert the conductive polar semiconductor with an amorphous structure into a crystalline structure, and the crystallization degree treatment and the polarity increasing treatment need to be carried out at the second preset temperature higher than the first preset temperature, so that in the crystallization degree treatment and the polarity increasing treatment of the conductive polar semiconductor on the back of the crystalline silicon substrate, the doping impurities in the doping medium layer on the front of the crystalline silicon substrate also diffuse into the crystalline silicon substrate to form a PN junction structure, the high-temperature process in the reaction process is utilized more reasonably, the diffusion process does not need to be carried out under the high-temperature condition additionally, the energy consumption is saved, the production capacity is improved, and the production cost of the battery is reduced. Alternatively, the crystallization degree treatment and the polarity increasing treatment may be diffusion treatments for diffusing impurity-doped impurities of the same conductivity into the conductivity semiconductor, such as diffusing phosphorus into phosphorus-doped amorphous silicon, diffusing boron into boron-doped amorphous silicon, and the like, and the amorphous structure may be converted into a crystalline structure during the diffusion treatments.
Optionally, the second preset temperature is 800 ℃ to 1100 ℃.
In this embodiment of the present invention, the second preset temperature may be any temperature between 800 ℃ and 1100 ℃, and optionally, the second preset temperature may be 800 ℃, 900 ℃, 1000 ℃, 1100 ℃, or the like, which is not specifically limited in this embodiment of the present invention.
And 105, respectively forming a first electrode structure and a second electrode structure on the two sides of the crystalline silicon substrate to obtain the crystalline silicon solar cell.
In the embodiment of the present invention, in order to prepare a workable crystalline silicon solar cell, a first electrode structure and a second electrode structure may be further formed on the front surface and the back surface of the crystalline silicon substrate, and a person skilled in the art may select specific structures and preparation manners of the first electrode structure and the second electrode structure according to actual requirements, which is not limited in the embodiment of the present invention.
Optionally, the step 105 comprises:
and step S31, removing the doped dielectric layer.
In the embodiment of the invention, the doped medium layer can be removed after the doped impurities are diffused into the crystalline silicon substrate, and in the removing process, the doped medium layer is obtained by a deposition process, so that the thickness can be increased while the requirement of production capacity is met, a good mask effect is achieved, the adverse effect on the uniformity of the front surface morphology structure of the crystalline substrate in the process of removing the doped medium layer is avoided, and the yield of the cell is improved. Optionally, during the process of depositing the tunneling layer and the conductive polar semiconductor on the back surface of the crystalline silicon substrate, a corresponding winding plating layer may be generated on the front surface, and before removing the doped dielectric layer, the winding plating layer on the front surface may be removed, where the process of removing the winding plating layer on the front surface may correspond to the foregoing description of removing the winding plating layer formed on the back surface during the process of depositing the doped dielectric layer on the front surface, and this is not particularly limited in this embodiment of the present invention.
And S32, sequentially depositing a passivation layer and a first anti-reflection layer on the P-type side surface of the crystalline silicon substrate, and preparing a first metal electrode.
In the embodiment of the invention, the first electrode structure may be an electrode structure formed on a P-type side surface of the crystalline silicon substrate, wherein, when the conductive type of the crystalline silicon substrate is P-type, the first electrode structure may be prepared on the back surface of the crystalline silicon substrate, and at this time, on the back surface of the crystalline silicon substrate, the first electrode structure sequentially comprises a passivation layer, a first anti-reflection layer and a first metal electrode; in the case that the conductivity type of the crystalline silicon substrate is N type, a first electrode structure may be prepared on the front surface of the crystalline silicon substrate, and in this case, on the front surface of the crystalline silicon substrate, the first electrode structure sequentially includes a passivation layer, a first anti-reflection layer, and a first metal electrode. One skilled in the art may select different passivation layers, first anti-reflection layers, and first metal electrodes according to application requirements, process conditions, and the like, and the embodiment of the invention is not limited in this respect.
And S33, depositing a second anti-reflection layer on the N-type side surface of the crystalline silicon substrate, and preparing a second metal electrode to obtain the crystalline silicon solar cell.
In the embodiment of the invention, the second electrode structure may be an electrode structure formed on an N-type side surface of the crystalline silicon substrate, wherein, when the conductivity type of the crystalline silicon substrate is N-type, the second electrode structure may be prepared on the back surface of the crystalline silicon substrate, and at this time, on the back surface of the crystalline silicon substrate, the second electrode structure sequentially includes a second anti-reflection layer and a second metal electrode; in the case that the conductivity type of the crystalline silicon substrate is P-type, a second electrode structure may be prepared on the front surface of the crystalline silicon substrate, and in this case, on the front surface of the crystalline silicon substrate, the second electrode structure sequentially includes a second anti-reflection layer and a second metal electrode. One skilled in the art may select different second anti-reflection layers and second metal electrodes according to application requirements, process conditions, and the like, and the embodiment of the invention is not limited in this respect.
In summary, in the embodiments of the present invention, the doped dielectric layer is deposited on the front surface of the crystalline silicon substrate, and in the subsequent process of increasing the crystallization degree and the polarity of the conductive polar semiconductor, the higher reaction temperature also allows the doped impurities in the doped dielectric layer to diffuse toward the crystalline silicon substrate to form the PN junction structure, and since the process temperature of the deposition process is lower than the process temperature of the diffusion process, the doped dielectric layer is deposited first and then the high temperature process in the subsequent steps is utilized without diffusing the impurities into the crystalline silicon substrate through the diffusion process, so that the energy consumption of the production equipment in the production process is reduced, the problem of contradiction between the thickness of the mask layer and the production capacity is solved while optimizing the production capacity, the doped dielectric layer can be adjusted to obtain a suitable thickness of the film layer, a good masking effect is achieved on the front surface of the crystalline silicon substrate, and the formation of defects in the crystalline silicon substrate caused by the high temperature environment is reduced, the surface of the silicon substrate is better protected, and the structural uniformity of the surface appearance of the silicon substrate is improved.
The preparation method of the crystalline silicon solar cell provided by the embodiment of the invention is described by specific examples as follows:
example 1
Fig. 2a is a schematic cross-sectional structure diagram of a cell in a first step process flow of example 1, which is provided by an embodiment of the present invention, and an N-type monocrystalline silicon wafer is cleaned and textured to obtain an N-type monocrystalline silicon substrate 201 shown in fig. 2 a.
Fig. 2b is a schematic cross-sectional structure diagram of a cell of a second process flow of example 1, in which a boron-doped silicon oxynitride dielectric layer 202 shown in fig. 2b is deposited on the front surface of the N-type single crystal silicon substrate shown in fig. 2a by plasma-enhanced chemical vapor deposition at a temperature of 430-520 ℃, wherein the thickness of the boron-doped silicon oxynitride dielectric layer 202 is 110nm, and a deposition gas source is silane, ammonia, laughing gas, or borane.
Fig. 2c is a schematic cross-sectional structure diagram of a cell in the third process flow of example 1, in which a chemical cleaning process is used to remove the plating layer formed by depositing the boron-doped silicon oxynitride dielectric layer 202 on the front surface of the N-type monocrystalline silicon substrate 201 shown in fig. 2b, and then a back surface acid polishing process is performed on the back surface of the N-type monocrystalline silicon substrate 201 to obtain the N-type monocrystalline silicon substrate 201 shown in fig. 2c, where the reflectivity of the back surface of the N-type monocrystalline silicon substrate 201 is about 30%.
Fig. 2d is a schematic cross-sectional structure diagram of a cell of the fourth process flow of example 1, in which a silicon oxide tunneling layer 203 shown in fig. 2d is formed by plasma-enhanced chemical vapor deposition on the back surface of the N-type single-crystal silicon substrate 201 shown in fig. 2c, wherein the thickness of the silicon oxide tunneling layer 203 is 1nm to 3nm, the plasma source is ozone, and the deposition process temperature of the silicon oxide tunneling layer 203 is 430 ℃ to 520 ℃.
Forming a phosphorus doped amorphous silicon layer 204 as shown in fig. 2d on the surface of the silicon oxide tunneling layer 203 by plasma enhanced chemical vapor deposition at a deposition process temperature of 430-520 ℃, wherein the thickness of the phosphorus doped amorphous silicon layer 204 is 120 nm.
Fig. 2e is a schematic cross-sectional structure diagram of the cell of the fifth process flow of example 1, which is provided in the embodiment of the present invention, and phosphorus impurities are diffused into the phosphorus-doped amorphous silicon layer 204 shown in fig. 2d through a diffusion furnace at a diffusion process temperature of 850-950 ℃, so that the phosphorus-doped amorphous silicon layer 204 is converted into the phosphorus-doped polysilicon layer 205, and the phosphorus doping concentration in the phosphorus-doped polysilicon layer 205 is increased, thereby forming a phosphorus-silicon glass layer 206 on the surface of the phosphorus-doped polysilicon layer 205 as shown in fig. 2 e. At the above temperature, the boron impurity of the boron-doped silicon oxynitride dielectric layer 202 on the front surface of the N-type single crystal silicon substrate 201 will also diffuse towards the N-type single crystal silicon substrate 201, thereby forming the P-type emitter 207 as shown in fig. 2 e.
Fig. 2f is a schematic cross-sectional view of a cell in a sixth process flow of example 1, in which the wraparound plating layer on the front surface of the N-type single crystal silicon substrate 201 from the back phosphorus-doped polysilicon layer 205 and the phosphosilicate glass layer 206 is removed by a chemical etching method, and the boron-doped silicon oxynitride dielectric layer 202 on the front surface is removed, as shown in fig. 2 f.
Fig. 2g is a schematic cross-sectional view of a cell in a seventh process flow of example 1, in which the phosphosilicate glass layer 206 on the back surface of the N-type single crystal silicon substrate 201 is removed by chemical etching, as shown in fig. 2 g;
fig. 2h is a schematic cross-sectional structure diagram of a cell of an eighth process flow of example 1, in which a 2nm to 3nm aluminum oxide passivation Layer 208 is deposited on the front surface of the N-type single crystal silicon substrate 201 by ALD (Atomic Layer Deposition), as shown in fig. 2 h;
fig. 2i is a schematic cross-sectional structure diagram of a cell of a ninth process flow in example 1, in which a first silicon nitride anti-reflection layer 209 and a second silicon nitride anti-reflection layer 210 are deposited on the front and back surfaces of an N-type single crystal silicon substrate 201 by plasma enhanced chemical vapor deposition, respectively, as shown in fig. 2 i;
fig. 2j is a schematic cross-sectional structural view of an N-type monocrystalline silicon solar cell prepared in example 1, wherein an aluminum electrode 211 is printed on the front surface of an N-type monocrystalline silicon substrate 201 by screen printing, and a silver electrode 212 is printed on the back surface of the N-type monocrystalline silicon substrate, as shown in fig. 2j, so as to obtain the N-type monocrystalline silicon solar cell.
Example 2
Fig. 3a is a schematic cross-sectional structure diagram of a cell of a first step process flow of example 2, which is provided by an embodiment of the present invention, and is used for cleaning and texturing a P-type monocrystalline silicon wafer to obtain a P-type monocrystalline silicon substrate 301 shown in fig. 3 a.
Fig. 3b is a schematic cross-sectional structure diagram of a cell of a second process flow of example 2 according to an embodiment of the present invention, in which a phosphorus-doped silicon oxynitride dielectric layer 302 shown in fig. 3b is deposited on the front surface of the P-type single crystal silicon substrate shown in fig. 3a by plasma-enhanced chemical vapor deposition at a temperature of 430 to 520 ℃, wherein the thickness of the phosphorus-doped silicon oxynitride dielectric layer 302 is 110nm, and a deposition gas source is silane, ammonia, laughing gas, or phosphane.
Fig. 3c is a schematic cross-sectional structure diagram of a cell in a third process flow of example 2, in which a chemical cleaning process is performed to remove a plating layer formed by depositing a phosphorus-doped silicon oxynitride dielectric layer 302 on the front surface of the P-type monocrystalline silicon substrate 301 shown in fig. 3b, and then a back surface acid polishing process is performed on the back surface of the P-type monocrystalline silicon substrate 301 to obtain the P-type monocrystalline silicon substrate 301 shown in fig. 3c, where the reflectivity of the back surface of the P-type monocrystalline silicon substrate 301 is about 30%.
Fig. 3d is a schematic cross-sectional structure diagram of a cell of the fourth process flow of example 2 according to the embodiment of the present invention, in which a silicon oxynitride tunneling layer 303 shown in fig. 3d is formed by plasma-enhanced chemical vapor deposition on the back surface of the P-type single-crystal silicon substrate 301 shown in fig. 3c, wherein the thickness of the silicon oxynitride tunneling layer 303 is 1nm to 3nm, the plasma gas source is ozone or nitrogen, and the deposition process temperature of the silicon oxynitride tunneling layer 303 is 430 ℃ to 520 ℃.
Forming a boron doped amorphous silicon layer 304 on the surface of the silicon oxynitride tunneling layer 303 by plasma enhanced chemical vapor deposition at a deposition process temperature of 430-520 ℃, wherein the thickness of the boron doped amorphous silicon layer 304 is 120nm, as shown in fig. 3 d.
Fig. 3e is a schematic cross-sectional structure diagram of a cell of the fifth process flow of example 2, in which boron impurities are diffused into the boron-doped amorphous silicon layer 304 shown in fig. 3d through a diffusion furnace at a diffusion process temperature of 850-950 ℃, so that the boron-doped amorphous silicon layer 304 is converted into the boron-doped polysilicon layer 305, and the boron doping concentration in the boron-doped polysilicon layer 305 is increased, thereby forming a borosilicate glass layer 306 on the surface of the boron-doped polysilicon layer 305 as shown in fig. 3 e. At the above temperature, the phosphorus impurity of the phosphorus-doped silicon oxynitride dielectric layer 302 on the front surface of the P-type single crystal silicon substrate 301 will also diffuse toward the P-type single crystal silicon substrate 301, thereby forming the N-type emitter 307 as shown in fig. 3 e.
Fig. 3f is a schematic cross-sectional view of a cell in a sixth process flow of example 2, in which the cladding layer on the front surface of the P-type single crystal silicon substrate 301 from the backside boron-doped polysilicon layer 305 and the borosilicate glass layer 306 is removed by chemical etching, and the phosphorus-doped silicon oxynitride dielectric layer 302 on the front surface is removed, as shown in fig. 3 f.
Fig. 3g is a schematic cross-sectional view of a cell of the seventh process flow of example 2, in which the borosilicate glass layer 306 on the back surface of the P-type single crystal silicon substrate 301 is removed by chemical etching, as shown in fig. 3 g;
fig. 3h is a schematic cross-sectional view of a cell of the eighth process flow of example 2 according to an embodiment of the present invention, in which a 2nm to 3nm aluminum oxide passivation layer 308 is deposited on the surface of the boron-doped polysilicon layer 305 by ALD, as shown in fig. 3 h;
fig. 3i is a schematic cross-sectional structure diagram of a cell of a ninth process flow in example 2, in which a first silicon nitride anti-reflection layer 309 and a second silicon nitride anti-reflection layer 310 are deposited on the front and back surfaces of a P-type single crystal silicon substrate 301 by plasma enhanced chemical vapor deposition, respectively, as shown in fig. 3 i;
fig. 3j is a schematic cross-sectional structural view of a P-type monocrystalline silicon solar cell prepared in example 2, and the P-type monocrystalline silicon solar cell is obtained by printing a silver electrode 311 on the front surface of a P-type monocrystalline silicon substrate 301 and printing an aluminum electrode 312 on the back surface of the P-type monocrystalline silicon substrate by screen printing, as shown in fig. 3 j.
Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the invention and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.
It will be understood that the invention is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the invention is limited only by the appended claims.
Claims (10)
1. A method for preparing a crystalline silicon solar cell, the method comprising:
depositing a doped dielectric layer on the front side of a crystalline silicon substrate at a first preset temperature, wherein the front side of the crystalline silicon substrate is provided with a textured structure;
forming a tunneling layer on the back surface of the crystalline silicon substrate;
depositing a conductive polar semiconductor on the surface of the tunneling layer;
performing crystallization degree treatment and polarity increasing treatment on the conductive polarity semiconductor at a second preset temperature, wherein the second preset temperature is higher than the first preset temperature, and the doped impurities of the doped dielectric layer diffuse into the crystalline silicon substrate at the second preset temperature;
and respectively forming a first electrode structure and a second electrode structure on the two sides of the crystalline silicon substrate to obtain the crystalline silicon solar cell.
2. The method of claim 1, wherein the first predetermined temperature is 200 ℃ to 700 ℃.
3. The method according to claim 1, wherein the second predetermined temperature is 800 ℃ to 1100 ℃.
4. The method of claim 1, wherein the doped dielectric layer is at least one film layer of silicon oxide, silicon oxynitride, and silicon nitride doped with a doping impurity, wherein the doping impurity is boron or phosphorus.
5. The method of claim 1, wherein the tunneling layer is at least one of a silicon nitride layer and a silicon oxide layer.
6. The method of claim 1, wherein depositing a conductive polar semiconductor on a surface of the tunneling layer comprises:
and depositing a conductive polar semiconductor on the surface of the tunneling layer by any one of a plasma enhanced chemical vapor deposition mode, an atmospheric pressure chemical vapor deposition mode, a medium pressure chemical vapor deposition mode and a low pressure chemical vapor deposition mode.
7. The method according to claim 1, wherein in the case where the conductivity type of the crystalline silicon substrate is N-type, the conductive polar semiconductor is at least one of phosphorus-doped amorphous silicon, amorphous silicon carbide, or an N-type transparent conductive film layer;
under the condition that the conductive type of the crystalline silicon substrate is P type, the conductive electrode semiconductor is at least one film layer of boron-doped amorphous silicon, amorphous silicon carbide or a P type transparent conductive film layer.
8. The method of claim 1, further comprising, before forming a tunneling layer on a backside of the crystalline silicon substrate:
removing a winding plating layer formed when the doped dielectric layer is deposited on the front side of the back surface of the crystalline silicon substrate;
and carrying out surface topography treatment on the back surface of the crystalline silicon substrate to enable the surface reflectivity of the back surface of the crystalline silicon substrate to be 15% -60%, wherein the surface topography treatment is any one of surface polishing, surface pyramid rounding treatment and surface pyramid enlarging structure.
9. The method according to claim 1, wherein the forming of the first electrode structure and the second electrode structure on both sides of the crystalline silicon substrate, respectively, results in a crystalline silicon solar cell comprising:
removing the doped dielectric layer;
depositing a passivation layer and a first anti-reflection layer on the P-type side surface of the crystalline silicon substrate in sequence, and preparing a first metal electrode;
and depositing a second anti-reflection layer on the N-type side surface of the crystalline silicon substrate, and preparing a second metal electrode to obtain the crystalline silicon solar cell.
10. A crystalline silicon solar cell, characterized in that the crystalline silicon solar cell is prepared by the method for preparing a crystalline silicon solar cell according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011053547.XA CN114335237A (en) | 2020-09-29 | 2020-09-29 | Preparation method of crystalline silicon solar cell and crystalline silicon solar cell |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011053547.XA CN114335237A (en) | 2020-09-29 | 2020-09-29 | Preparation method of crystalline silicon solar cell and crystalline silicon solar cell |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114335237A true CN114335237A (en) | 2022-04-12 |
Family
ID=81010665
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011053547.XA Pending CN114335237A (en) | 2020-09-29 | 2020-09-29 | Preparation method of crystalline silicon solar cell and crystalline silicon solar cell |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114335237A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115148861A (en) * | 2022-09-01 | 2022-10-04 | 福建金石能源有限公司 | Manufacturing method of heterojunction solar cell |
| CN116344632A (en) * | 2023-02-17 | 2023-06-27 | 扬州大学 | POLO-IBC passivation contact battery and preparation method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110021008A1 (en) * | 2009-07-22 | 2011-01-27 | Applied Materials, Inc. | Directional Solid Phase Crystallization of Thin Amorphous Silicon for Solar Cell Applications |
| CN105405899A (en) * | 2015-09-28 | 2016-03-16 | 上海大族新能源科技有限公司 | N-type double-side battery and manufacturing method thereof |
| WO2017020689A1 (en) * | 2015-08-06 | 2017-02-09 | 王能青 | Back contact type solar cell based on p-type silicon substrate and preparation method therefor |
| CN111029438A (en) * | 2019-12-04 | 2020-04-17 | 江苏杰太光电技术有限公司 | Preparation method of N-type passivated contact solar cell |
-
2020
- 2020-09-29 CN CN202011053547.XA patent/CN114335237A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110277682A1 (en) * | 2008-07-22 | 2011-11-17 | Rana Virnedra V | Directional solid phase crystallization of thin amorphous silicon for solar cell applications |
| US20110021008A1 (en) * | 2009-07-22 | 2011-01-27 | Applied Materials, Inc. | Directional Solid Phase Crystallization of Thin Amorphous Silicon for Solar Cell Applications |
| WO2017020689A1 (en) * | 2015-08-06 | 2017-02-09 | 王能青 | Back contact type solar cell based on p-type silicon substrate and preparation method therefor |
| CN105405899A (en) * | 2015-09-28 | 2016-03-16 | 上海大族新能源科技有限公司 | N-type double-side battery and manufacturing method thereof |
| CN111029438A (en) * | 2019-12-04 | 2020-04-17 | 江苏杰太光电技术有限公司 | Preparation method of N-type passivated contact solar cell |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115148861A (en) * | 2022-09-01 | 2022-10-04 | 福建金石能源有限公司 | Manufacturing method of heterojunction solar cell |
| CN116344632A (en) * | 2023-02-17 | 2023-06-27 | 扬州大学 | POLO-IBC passivation contact battery and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111029438B (en) | Preparation method of N-type passivated contact solar cell | |
| EP4203081A1 (en) | Topcon battery and preparation method therefor, and electrical appliance | |
| CN110518088B (en) | Preparation method of SE solar cell | |
| CN108963005B (en) | Novel composite-structure full-back-face heterojunction solar cell and preparation method | |
| CN111933752A (en) | Solar cell and preparation method thereof | |
| WO2024066884A1 (en) | Solar cell and manufacturing method therefor | |
| WO2024066207A1 (en) | New solar cell and fabrication method therefor | |
| CN114335237A (en) | Preparation method of crystalline silicon solar cell and crystalline silicon solar cell | |
| WO2023092977A1 (en) | Method for preparing tunnel oxide layer and amorphous silicon thin film, and topcon cell | |
| CN115020546A (en) | Double-sided passivation contact solar cell and preparation method thereof | |
| CN116741877A (en) | TBC battery preparation method and TBC battery | |
| CN115332366A (en) | Back passivation contact heterojunction solar cell and preparation method thereof | |
| CN111261751A (en) | Deposition method of single-sided amorphous silicon | |
| CN117133834B (en) | Short-process preparation method and application of combined passivation back contact battery | |
| CN114267753A (en) | TOPCon solar cell, preparation method thereof and photovoltaic module | |
| CN116666479B (en) | Efficient selective emitter crystalline silicon battery with double-sided power generation and preparation method thereof | |
| CN112687762A (en) | Solar cell surface passivation method | |
| CN218160392U (en) | Solar cell | |
| CN116247123A (en) | Preparation method of P-type back tunneling oxidation passivation contact solar cell | |
| CN115985991A (en) | Solar cell and preparation method thereof | |
| CN113571411B (en) | Manufacturing method of N-type TOPCON solar cell | |
| CN114005907A (en) | Manufacturing method of Topcon battery | |
| CN114583016A (en) | TOPCon battery and preparation method thereof | |
| CN115020508A (en) | Full back contact solar cell and manufacturing method thereof | |
| CN114823969A (en) | Low-temperature hydrogen plasma auxiliary annealing method for improving performance of passivation contact structure and TOPCon solar cell |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: No. 43 Bailing South Road, Quzhou City, Zhejiang Province 324022 Applicant after: Yidao New Energy Technology Co.,Ltd. Address before: No. 43, bailing South Road, Donggang District, green industry cluster district, Quzhou City, Zhejiang Province Applicant before: A New Energy Technology (Quzhou) Co.,Ltd. |
|
| CB02 | Change of applicant information |